1 /*
2 * Copyright (c) 2015-2019, Renesas Electronics Corporation
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <stdint.h>
9
10 #include <common/debug.h>
11
12 #include "../qos_common.h"
13 #include "../qos_reg.h"
14 #include "qos_init_v3m.h"
15
16 #define RCAR_QOS_VERSION "rev.0.01"
17
18 #include "qos_init_v3m_mstat.h"
19
20 struct rcar_gen3_dbsc_qos_settings v3m_qos[] = {
21 /* BUFCAM settings */
22 { DBSC_DBCAM0CNF1, 0x00044218 },
23 { DBSC_DBCAM0CNF2, 0x000000F4 },
24 { DBSC_DBSCHCNT0, 0x080F003F },
25 { DBSC_DBSCHCNT1, 0x00001010 },
26
27 { DBSC_DBSCHSZ0, 0x00000001 },
28 { DBSC_DBSCHRW0, 0x22421111 },
29 { DBSC_DBSCHRW1, 0x00180034 },
30 { DBSC_SCFCTST0, 0x180B1708 },
31 { DBSC_SCFCTST1, 0x0808070C },
32 { DBSC_SCFCTST2, 0x012F1123 },
33
34 /* QoS Settings */
35 { DBSC_DBSCHQOS00, 0x0000F000 },
36 { DBSC_DBSCHQOS01, 0x0000E000 },
37 { DBSC_DBSCHQOS02, 0x00007000 },
38 { DBSC_DBSCHQOS03, 0x00000000 },
39 { DBSC_DBSCHQOS40, 0x0000F000 },
40 { DBSC_DBSCHQOS41, 0x0000EFFF },
41 { DBSC_DBSCHQOS42, 0x0000B000 },
42 { DBSC_DBSCHQOS43, 0x00000000 },
43 { DBSC_DBSCHQOS90, 0x0000F000 },
44 { DBSC_DBSCHQOS91, 0x0000EFFF },
45 { DBSC_DBSCHQOS92, 0x0000D000 },
46 { DBSC_DBSCHQOS93, 0x00000000 },
47 { DBSC_DBSCHQOS130, 0x0000F000 },
48 { DBSC_DBSCHQOS131, 0x0000EFFF },
49 { DBSC_DBSCHQOS132, 0x0000E800 },
50 { DBSC_DBSCHQOS133, 0x00007000 },
51 { DBSC_DBSCHQOS140, 0x0000F000 },
52 { DBSC_DBSCHQOS141, 0x0000EFFF },
53 { DBSC_DBSCHQOS142, 0x0000E800 },
54 { DBSC_DBSCHQOS143, 0x0000B000 },
55 { DBSC_DBSCHQOS150, 0x000007D0 },
56 { DBSC_DBSCHQOS151, 0x000007CF },
57 { DBSC_DBSCHQOS152, 0x000005D0 },
58 { DBSC_DBSCHQOS153, 0x000003D0 },
59 };
60
qos_init_v3m(void)61 void qos_init_v3m(void)
62 {
63 return;
64
65 rcar_qos_dbsc_setting(v3m_qos, ARRAY_SIZE(v3m_qos), false);
66
67 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
68 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
69 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
70 #endif
71
72 /* Resource Alloc setting */
73 io_write_32(QOSCTRL_RAS, 0x00000020U);
74 io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
75 io_write_32(QOSCTRL_REGGD, 0x00000004U);
76 io_write_64(QOSCTRL_DANN, 0x0202020104040200U);
77 io_write_32(QOSCTRL_DANT, 0x00201008U);
78 io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 ES1 */
79 io_write_64(QOSCTRL_EMS, 0x0000000000000000U);
80 io_write_32(QOSCTRL_INSFC, 0x63C20001U);
81 io_write_32(QOSCTRL_BERR, 0x00000000U);
82
83 /* QOSBW setting */
84 io_write_32(QOSCTRL_SL_INIT, 0x0305007DU);
85 io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
86
87 /* QOSBW SRAM setting */
88 uint32_t i;
89
90 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
91 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
92 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
93 }
94 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
95 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
96 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
97 }
98
99 /* AXI-IF arbitration setting */
100 io_write_32(DBSC_AXARB, 0x18010000U);
101
102 /* Resource Alloc start */
103 io_write_32(QOSCTRL_RAEN, 0x00000001U);
104
105 /* QOSBW start */
106 io_write_32(QOSCTRL_STATQC, 0x00000001U);
107
108 #else
109 NOTICE("BL2: QoS is None\n");
110 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
111 }
112