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1 /**************************************************************************
2  *
3  * Copyright 2017 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include "radeon_vcn_enc.h"
29 
30 #include "pipe/p_video_codec.h"
31 #include "radeon_video.h"
32 #include "radeonsi/si_pipe.h"
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35 #include "vl/vl_video_buffer.h"
36 
37 #include <stdio.h>
38 
39 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
40 
radeon_vcn_enc_get_param(struct radeon_encoder * enc,struct pipe_picture_desc * picture)41 static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
42 {
43    if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
44       struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
45       enc->enc_pic.picture_type = pic->picture_type;
46       enc->enc_pic.frame_num = pic->frame_num;
47       enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
48       enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
49       enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
50       enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
51       enc->enc_pic.not_referenced = pic->not_referenced;
52       enc->enc_pic.is_idr = (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR);
53       if (pic->pic_ctrl.enc_frame_cropping_flag) {
54          enc->enc_pic.crop_left = pic->pic_ctrl.enc_frame_crop_left_offset;
55          enc->enc_pic.crop_right = pic->pic_ctrl.enc_frame_crop_right_offset;
56          enc->enc_pic.crop_top = pic->pic_ctrl.enc_frame_crop_top_offset;
57          enc->enc_pic.crop_bottom = pic->pic_ctrl.enc_frame_crop_bottom_offset;
58       } else {
59          enc->enc_pic.crop_left = 0;
60          enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
61          enc->enc_pic.crop_top = 0;
62          enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
63       }
64       enc->enc_pic.rc_layer_init.target_bit_rate = pic->rate_ctrl.target_bitrate;
65       enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rate_ctrl.peak_bitrate;
66       enc->enc_pic.rc_layer_init.frame_rate_num = pic->rate_ctrl.frame_rate_num;
67       enc->enc_pic.rc_layer_init.frame_rate_den = pic->rate_ctrl.frame_rate_den;
68       enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
69       enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rate_ctrl.target_bits_picture;
70       enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer =
71          pic->rate_ctrl.peak_bits_picture_integer;
72       enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional =
73          pic->rate_ctrl.peak_bits_picture_fraction;
74       enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl.vbv_buf_lv;
75       enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
76       enc->enc_pic.rc_per_pic.min_qp_app = 0;
77       enc->enc_pic.rc_per_pic.max_qp_app = 51;
78       enc->enc_pic.rc_per_pic.max_au_size = 0;
79       enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl.fill_data_enable;
80       enc->enc_pic.rc_per_pic.skip_frame_enable = false;
81       enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl.enforce_hrd;
82       switch (pic->rate_ctrl.rate_ctrl_method) {
83       case PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE:
84          enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
85          break;
86       case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
87       case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT:
88          enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
89          break;
90       case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
91       case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE:
92          enc->enc_pic.rc_session_init.rate_control_method =
93             RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
94          break;
95       default:
96          enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
97       }
98    } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
99       struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
100       enc->enc_pic.picture_type = pic->picture_type;
101       enc->enc_pic.frame_num = pic->frame_num;
102       enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
103       enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
104       enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
105       enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
106       enc->enc_pic.not_referenced = pic->not_referenced;
107       enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
108                             (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
109 
110       if (pic->seq.conformance_window_flag) {
111           enc->enc_pic.crop_left = pic->seq.conf_win_left_offset;
112           enc->enc_pic.crop_right = pic->seq.conf_win_right_offset;
113           enc->enc_pic.crop_top = pic->seq.conf_win_top_offset;
114           enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset;
115       } else {
116           enc->enc_pic.crop_left = 0;
117           enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
118           enc->enc_pic.crop_top = 0;
119           enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
120       }
121 
122       enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
123       enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
124       enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
125       enc->enc_pic.max_poc = MAX2(16, util_next_power_of_two(pic->seq.intra_period));
126       enc->enc_pic.log2_max_poc = 0;
127       for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
128          i = (i >> 1);
129       enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
130       enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
131       enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
132       enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
133          pic->seq.log2_diff_max_min_luma_coding_block_size;
134       enc->enc_pic.log2_min_transform_block_size_minus2 =
135          pic->seq.log2_min_transform_block_size_minus2;
136       enc->enc_pic.log2_diff_max_min_transform_block_size =
137          pic->seq.log2_diff_max_min_transform_block_size;
138       enc->enc_pic.max_transform_hierarchy_depth_inter =
139          pic->seq.max_transform_hierarchy_depth_inter;
140       enc->enc_pic.max_transform_hierarchy_depth_intra =
141          pic->seq.max_transform_hierarchy_depth_intra;
142       enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
143       enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
144       enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
145       enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
146       enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
147       enc->enc_pic.sample_adaptive_offset_enabled_flag =
148          pic->seq.sample_adaptive_offset_enabled_flag;
149       enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
150       enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
151       enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
152          pic->slice.slice_loop_filter_across_slices_enabled_flag;
153       enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
154          pic->slice.slice_deblocking_filter_disabled_flag;
155       enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
156       enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
157       enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
158       enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
159       enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
160          pic->seq.log2_min_luma_coding_block_size_minus3;
161       enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
162       enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
163          pic->seq.strong_intra_smoothing_enabled_flag;
164       enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag =
165          pic->pic.constrained_intra_pred_flag;
166       enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
167       enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
168       enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
169       enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
170       enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
171       enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
172       enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
173       enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
174       enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
175       enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
176       enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional =
177          pic->rc.peak_bits_picture_fraction;
178       enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
179       enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
180       enc->enc_pic.rc_per_pic.min_qp_app = 0;
181       enc->enc_pic.rc_per_pic.max_qp_app = 51;
182       enc->enc_pic.rc_per_pic.max_au_size = 0;
183       enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
184       enc->enc_pic.rc_per_pic.skip_frame_enable = false;
185       enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
186       switch (pic->rc.rate_ctrl_method) {
187       case PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE:
188          enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
189          break;
190       case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
191       case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT:
192          enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
193          break;
194       case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
195       case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
196          enc->enc_pic.rc_session_init.rate_control_method =
197             RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
198          break;
199       default:
200          enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
201       }
202    }
203 }
204 
flush(struct radeon_encoder * enc)205 static void flush(struct radeon_encoder *enc)
206 {
207    enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
208 }
209 
radeon_enc_flush(struct pipe_video_codec * encoder)210 static void radeon_enc_flush(struct pipe_video_codec *encoder)
211 {
212    struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
213    flush(enc);
214 }
215 
radeon_enc_cs_flush(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)216 static void radeon_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
217 {
218    // just ignored
219 }
220 
get_cpb_num(struct radeon_encoder * enc)221 static unsigned get_cpb_num(struct radeon_encoder *enc)
222 {
223    unsigned w = align(enc->base.width, 16) / 16;
224    unsigned h = align(enc->base.height, 16) / 16;
225    unsigned dpb;
226 
227    switch (enc->base.level) {
228    case 10:
229       dpb = 396;
230       break;
231    case 11:
232       dpb = 900;
233       break;
234    case 12:
235    case 13:
236    case 20:
237       dpb = 2376;
238       break;
239    case 21:
240       dpb = 4752;
241       break;
242    case 22:
243    case 30:
244       dpb = 8100;
245       break;
246    case 31:
247       dpb = 18000;
248       break;
249    case 32:
250       dpb = 20480;
251       break;
252    case 40:
253    case 41:
254       dpb = 32768;
255       break;
256    case 42:
257       dpb = 34816;
258       break;
259    case 50:
260       dpb = 110400;
261       break;
262    default:
263    case 51:
264    case 52:
265       dpb = 184320;
266       break;
267    }
268 
269    return MIN2(dpb / (w * h), 16);
270 }
271 
radeon_enc_begin_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)272 static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
273                                    struct pipe_video_buffer *source,
274                                    struct pipe_picture_desc *picture)
275 {
276    struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
277    struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
278    bool need_rate_control = false;
279 
280    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
281       struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
282       need_rate_control =
283          (enc->enc_pic.rc_layer_init.target_bit_rate != pic->rate_ctrl.target_bitrate) ||
284          (enc->enc_pic.rc_layer_init.frame_rate_num != pic->rate_ctrl.frame_rate_num) ||
285          (enc->enc_pic.rc_layer_init.frame_rate_den != pic->rate_ctrl.frame_rate_den);
286    } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
287       struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
288       need_rate_control = enc->enc_pic.rc_layer_init.target_bit_rate != pic->rc.target_bitrate;
289    }
290 
291    radeon_vcn_enc_get_param(enc, picture);
292 
293    enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
294    enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
295 
296    enc->need_feedback = false;
297 
298    if (!enc->stream_handle) {
299       struct rvid_buffer fb;
300       enc->stream_handle = si_vid_alloc_stream_handle();
301       enc->si = CALLOC_STRUCT(rvid_buffer);
302       si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_STAGING);
303       si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
304       enc->fb = &fb;
305       enc->begin(enc);
306       flush(enc);
307       si_vid_destroy_buffer(&fb);
308    }
309    if (need_rate_control) {
310       enc->begin(enc);
311       flush(enc);
312    }
313 }
314 
radeon_enc_encode_bitstream(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_resource * destination,void ** fb)315 static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
316                                         struct pipe_video_buffer *source,
317                                         struct pipe_resource *destination, void **fb)
318 {
319    struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
320    enc->get_buffer(destination, &enc->bs_handle, NULL);
321    enc->bs_size = destination->width0;
322 
323    *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
324 
325    if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) {
326       RVID_ERR("Can't create feedback buffer.\n");
327       return;
328    }
329 
330    enc->need_feedback = true;
331    enc->encode(enc);
332 }
333 
radeon_enc_end_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)334 static void radeon_enc_end_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source,
335                                  struct pipe_picture_desc *picture)
336 {
337    struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
338    flush(enc);
339 }
340 
radeon_enc_destroy(struct pipe_video_codec * encoder)341 static void radeon_enc_destroy(struct pipe_video_codec *encoder)
342 {
343    struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
344 
345    if (enc->stream_handle) {
346       struct rvid_buffer fb;
347       enc->need_feedback = false;
348       si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
349       enc->fb = &fb;
350       enc->destroy(enc);
351       flush(enc);
352       si_vid_destroy_buffer(&fb);
353    }
354 
355    si_vid_destroy_buffer(&enc->cpb);
356    enc->ws->cs_destroy(enc->cs);
357    FREE(enc);
358 }
359 
radeon_enc_get_feedback(struct pipe_video_codec * encoder,void * feedback,unsigned * size)360 static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
361                                     unsigned *size)
362 {
363    struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
364    struct rvid_buffer *fb = feedback;
365 
366    if (size) {
367       uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs,
368                                           PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
369       if (ptr[1])
370          *size = ptr[6];
371       else
372          *size = 0;
373       enc->ws->buffer_unmap(fb->res->buf);
374    }
375 
376    si_vid_destroy_buffer(fb);
377    FREE(fb);
378 }
379 
radeon_create_encoder(struct pipe_context * context,const struct pipe_video_codec * templ,struct radeon_winsys * ws,radeon_enc_get_buffer get_buffer)380 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
381                                                const struct pipe_video_codec *templ,
382                                                struct radeon_winsys *ws,
383                                                radeon_enc_get_buffer get_buffer)
384 {
385    struct si_screen *sscreen = (struct si_screen *)context->screen;
386    struct si_context *sctx = (struct si_context *)context;
387    struct radeon_encoder *enc;
388    struct pipe_video_buffer *tmp_buf, templat = {};
389    struct radeon_surf *tmp_surf;
390    unsigned cpb_size;
391 
392    enc = CALLOC_STRUCT(radeon_encoder);
393 
394    if (!enc)
395       return NULL;
396 
397    enc->alignment = 256;
398    enc->base = *templ;
399    enc->base.context = context;
400    enc->base.destroy = radeon_enc_destroy;
401    enc->base.begin_frame = radeon_enc_begin_frame;
402    enc->base.encode_bitstream = radeon_enc_encode_bitstream;
403    enc->base.end_frame = radeon_enc_end_frame;
404    enc->base.flush = radeon_enc_flush;
405    enc->base.get_feedback = radeon_enc_get_feedback;
406    enc->get_buffer = get_buffer;
407    enc->bits_in_shifter = 0;
408    enc->screen = context->screen;
409    enc->ws = ws;
410    enc->cs = ws->cs_create(sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc, false);
411 
412    if (!enc->cs) {
413       RVID_ERR("Can't get command submission context.\n");
414       goto error;
415    }
416 
417    struct rvid_buffer si;
418    si_vid_create_buffer(enc->screen, &si, 128 * 1024, PIPE_USAGE_STAGING);
419    enc->si = &si;
420 
421    templat.buffer_format = PIPE_FORMAT_NV12;
422    if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
423       templat.buffer_format = PIPE_FORMAT_P010;
424    templat.width = enc->base.width;
425    templat.height = enc->base.height;
426    templat.interlaced = false;
427 
428    if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
429       RVID_ERR("Can't create video buffer.\n");
430       goto error;
431    }
432 
433    enc->cpb_num = get_cpb_num(enc);
434 
435    if (!enc->cpb_num)
436       goto error;
437 
438    get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
439 
440    cpb_size = (sscreen->info.chip_class < GFX9)
441                  ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
442                       align(tmp_surf->u.legacy.level[0].nblk_y, 32)
443                  : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
444                       align(tmp_surf->u.gfx9.surf_height, 32);
445 
446    cpb_size = cpb_size * 3 / 2;
447    cpb_size = cpb_size * enc->cpb_num;
448    tmp_buf->destroy(tmp_buf);
449 
450    if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
451       RVID_ERR("Can't create CPB buffer.\n");
452       goto error;
453    }
454 
455    if (sscreen->info.family >= CHIP_SIENNA_CICHLID)
456       radeon_enc_3_0_init(enc);
457    else if (sscreen->info.family >= CHIP_RENOIR)
458       radeon_enc_2_0_init(enc);
459    else
460       radeon_enc_1_2_init(enc);
461 
462    return &enc->base;
463 
464 error:
465    if (enc->cs)
466       enc->ws->cs_destroy(enc->cs);
467 
468    si_vid_destroy_buffer(&enc->cpb);
469 
470    FREE(enc);
471    return NULL;
472 }
473 
radeon_enc_add_buffer(struct radeon_encoder * enc,struct pb_buffer * buf,enum radeon_bo_usage usage,enum radeon_bo_domain domain,signed offset)474 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
475                            enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset)
476 {
477    enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
478    uint64_t addr;
479    addr = enc->ws->buffer_get_virtual_address(buf);
480    addr = addr + offset;
481    RADEON_ENC_CS(addr >> 32);
482    RADEON_ENC_CS(addr);
483 }
484 
radeon_enc_set_emulation_prevention(struct radeon_encoder * enc,bool set)485 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
486 {
487    if (set != enc->emulation_prevention) {
488       enc->emulation_prevention = set;
489       enc->num_zeros = 0;
490    }
491 }
492 
radeon_enc_output_one_byte(struct radeon_encoder * enc,unsigned char byte)493 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
494 {
495    if (enc->byte_index == 0)
496       enc->cs->current.buf[enc->cs->current.cdw] = 0;
497    enc->cs->current.buf[enc->cs->current.cdw] |=
498       ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
499    enc->byte_index++;
500 
501    if (enc->byte_index >= 4) {
502       enc->byte_index = 0;
503       enc->cs->current.cdw++;
504    }
505 }
506 
radeon_enc_emulation_prevention(struct radeon_encoder * enc,unsigned char byte)507 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
508 {
509    if (enc->emulation_prevention) {
510       if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
511          radeon_enc_output_one_byte(enc, 0x03);
512          enc->bits_output += 8;
513          enc->num_zeros = 0;
514       }
515       enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
516    }
517 }
518 
radeon_enc_code_fixed_bits(struct radeon_encoder * enc,unsigned int value,unsigned int num_bits)519 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
520                                 unsigned int num_bits)
521 {
522    unsigned int bits_to_pack = 0;
523 
524    while (num_bits > 0) {
525       unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
526       bits_to_pack =
527          num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
528 
529       if (bits_to_pack < num_bits)
530          value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
531 
532       enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
533       num_bits -= bits_to_pack;
534       enc->bits_in_shifter += bits_to_pack;
535 
536       while (enc->bits_in_shifter >= 8) {
537          unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
538          enc->shifter <<= 8;
539          radeon_enc_emulation_prevention(enc, output_byte);
540          radeon_enc_output_one_byte(enc, output_byte);
541          enc->bits_in_shifter -= 8;
542          enc->bits_output += 8;
543       }
544    }
545 }
546 
radeon_enc_reset(struct radeon_encoder * enc)547 void radeon_enc_reset(struct radeon_encoder *enc)
548 {
549    enc->emulation_prevention = false;
550    enc->shifter = 0;
551    enc->bits_in_shifter = 0;
552    enc->bits_output = 0;
553    enc->num_zeros = 0;
554    enc->byte_index = 0;
555 }
556 
radeon_enc_byte_align(struct radeon_encoder * enc)557 void radeon_enc_byte_align(struct radeon_encoder *enc)
558 {
559    unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
560 
561    if (num_padding_zeros > 0)
562       radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
563 }
564 
radeon_enc_flush_headers(struct radeon_encoder * enc)565 void radeon_enc_flush_headers(struct radeon_encoder *enc)
566 {
567    if (enc->bits_in_shifter != 0) {
568       unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
569       radeon_enc_emulation_prevention(enc, output_byte);
570       radeon_enc_output_one_byte(enc, output_byte);
571       enc->bits_output += enc->bits_in_shifter;
572       enc->shifter = 0;
573       enc->bits_in_shifter = 0;
574       enc->num_zeros = 0;
575    }
576 
577    if (enc->byte_index > 0) {
578       enc->cs->current.cdw++;
579       enc->byte_index = 0;
580    }
581 }
582 
radeon_enc_code_ue(struct radeon_encoder * enc,unsigned int value)583 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
584 {
585    int x = -1;
586    unsigned int ue_code = value + 1;
587    value += 1;
588 
589    while (value) {
590       value = (value >> 1);
591       x += 1;
592    }
593 
594    unsigned int ue_length = (x << 1) + 1;
595    radeon_enc_code_fixed_bits(enc, ue_code, ue_length);
596 }
597 
radeon_enc_code_se(struct radeon_encoder * enc,int value)598 void radeon_enc_code_se(struct radeon_encoder *enc, int value)
599 {
600    unsigned int v = 0;
601 
602    if (value != 0)
603       v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
604 
605    radeon_enc_code_ue(enc, v);
606 }
607