1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #ifndef RADV_CS_H
26 #define RADV_CS_H
27
28 #include <string.h>
29 #include <stdint.h>
30 #include <assert.h>
31 #include "radv_private.h"
32 #include "sid.h"
33
radeon_check_space(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,unsigned needed)34 static inline unsigned radeon_check_space(struct radeon_winsys *ws,
35 struct radeon_cmdbuf *cs,
36 unsigned needed)
37 {
38 if (cs->max_dw - cs->cdw < needed)
39 ws->cs_grow(cs, needed);
40 return cs->cdw + needed;
41 }
42
radeon_set_config_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)43 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
44 {
45 assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END);
46 assert(cs->cdw + 2 + num <= cs->max_dw);
47 assert(num);
48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
50 }
51
radeon_set_config_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
53 {
54 radeon_set_config_reg_seq(cs, reg, 1);
55 radeon_emit(cs, value);
56 }
57
radeon_set_context_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)58 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
59 {
60 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
61 assert(cs->cdw + 2 + num <= cs->max_dw);
62 assert(num);
63 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
64 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
65 }
66
radeon_set_context_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)67 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
68 {
69 radeon_set_context_reg_seq(cs, reg, 1);
70 radeon_emit(cs, value);
71 }
72
73
radeon_set_context_reg_idx(struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value)74 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
75 unsigned reg, unsigned idx,
76 unsigned value)
77 {
78 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
79 assert(cs->cdw + 3 <= cs->max_dw);
80 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
81 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
82 radeon_emit(cs, value);
83 }
84
radeon_set_context_reg_rmw(struct radeon_cmdbuf * cs,unsigned reg,unsigned value,unsigned mask)85 static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs,
86 unsigned reg, unsigned value,
87 unsigned mask)
88 {
89 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
90 assert(cs->cdw + 4 <= cs->max_dw);
91 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
92 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
93 radeon_emit(cs, mask);
94 radeon_emit(cs, value);
95 }
96
radeon_set_sh_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)97 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
98 {
99 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
100 assert(cs->cdw + 2 + num <= cs->max_dw);
101 assert(num);
102 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
103 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
104 }
105
radeon_set_sh_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)106 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
107 {
108 radeon_set_sh_reg_seq(cs, reg, 1);
109 radeon_emit(cs, value);
110 }
111
radeon_set_sh_reg_idx(const struct radv_physical_device * pdevice,struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value)112 static inline void radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice,
113 struct radeon_cmdbuf *cs,
114 unsigned reg, unsigned idx,
115 unsigned value)
116 {
117 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
118 assert(cs->cdw + 3 <= cs->max_dw);
119 assert(idx);
120
121 unsigned opcode = PKT3_SET_SH_REG_INDEX;
122 if (pdevice->rad_info.chip_class < GFX10)
123 opcode = PKT3_SET_SH_REG;
124
125 radeon_emit(cs, PKT3(opcode, 1, 0));
126 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));
127 radeon_emit(cs, value);
128 }
129
radeon_set_uconfig_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)130 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
131 {
132 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
133 assert(cs->cdw + 2 + num <= cs->max_dw);
134 assert(num);
135 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
136 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
137 }
138
radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)139 static inline void radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs,
140 unsigned reg, unsigned num)
141 {
142 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
143 assert(cs->cdw + 2 + num <= cs->max_dw);
144 assert(num);
145 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1));
146 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
147 }
148
radeon_set_uconfig_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)149 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
150 {
151 radeon_set_uconfig_reg_seq(cs, reg, 1);
152 radeon_emit(cs, value);
153 }
154
radeon_set_uconfig_reg_idx(const struct radv_physical_device * pdevice,struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value)155 static inline void radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice,
156 struct radeon_cmdbuf *cs,
157 unsigned reg, unsigned idx,
158 unsigned value)
159 {
160 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
161 assert(cs->cdw + 3 <= cs->max_dw);
162 assert(idx);
163
164 unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
165 if (pdevice->rad_info.chip_class < GFX9 ||
166 (pdevice->rad_info.chip_class == GFX9 && pdevice->rad_info.me_fw_version < 26))
167 opcode = PKT3_SET_UCONFIG_REG;
168
169 radeon_emit(cs, PKT3(opcode, 1, 0));
170 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
171 radeon_emit(cs, value);
172 }
173
radeon_set_privileged_config_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)174 static inline void radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs,
175 unsigned reg,
176 unsigned value)
177 {
178 assert(reg < CIK_UCONFIG_REG_OFFSET);
179 assert(cs->cdw + 6 <= cs->max_dw);
180
181 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
182 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
183 COPY_DATA_DST_SEL(COPY_DATA_PERF));
184 radeon_emit(cs, value);
185 radeon_emit(cs, 0); /* unused */
186 radeon_emit(cs, reg >> 2);
187 radeon_emit(cs, 0); /* unused */
188 }
189
190 #endif /* RADV_CS_H */
191