| /external/libffi/include/ |
| D | ffi_cfi.h | 14 # define cfi_def_cfa(reg, off) .cfi_def_cfa reg, off argument
15 # define cfi_def_cfa_register(reg) .cfi_def_cfa_register reg argument
18 # define cfi_offset(reg, off) .cfi_offset reg, off argument
19 # define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off argument
21 # define cfi_return_column(reg) .cfi_return_column reg argument
22 # define cfi_restore(reg) .cfi_restore reg argument
23 # define cfi_same_value(reg) .cfi_same_value reg argument
24 # define cfi_undefined(reg) .cfi_undefined reg argument
36 # define cfi_def_cfa(reg, off) argument
37 # define cfi_def_cfa_register(reg) argument
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_cs.h | 43 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
58 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
67 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
75 unsigned reg, unsigned idx, in radeon_set_context_reg_idx()
86 unsigned reg, unsigned value, in radeon_set_context_reg_rmw()
97 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
106 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
114 unsigned reg, unsigned idx, in radeon_set_sh_reg_idx()
130 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq()
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| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | RegisterInfos_x86_64.h | 44 #define FPR_SIZE(reg) sizeof(((FXSAVE *)nullptr)->reg) argument
64 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ argument
73 #define DEFINE_FPR(name, reg, kind1, kind2, kind3, kind4) \ argument
81 #define DEFINE_FP_ST(reg, i) \ argument
91 #define DEFINE_FP_MM(reg, i, streg) \ argument
101 #define DEFINE_XMM(reg, i) \ argument
112 #define DEFINE_YMM(reg, i) \ argument
123 #define DEFINE_BNDR(reg, i) \ argument
143 #define DEFINE_DR(reg, i) \ argument
197 #define DEFINE_FPR_32(name, reg, kind1, kind2, kind3, kind4, reg64) \ argument
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| D | RegisterContextPOSIX_ppc64le.cpp | 98 bool RegisterContextPOSIX_ppc64le::IsGPR(unsigned reg) { in IsGPR()
102 bool RegisterContextPOSIX_ppc64le::IsFPR(unsigned reg) { in IsFPR()
106 bool RegisterContextPOSIX_ppc64le::IsVMX(unsigned reg) { in IsVMX()
110 bool RegisterContextPOSIX_ppc64le::IsVSX(unsigned reg) { in IsVSX()
123 unsigned RegisterContextPOSIX_ppc64le::GetRegisterOffset(unsigned reg) { in GetRegisterOffset()
128 unsigned RegisterContextPOSIX_ppc64le::GetRegisterSize(unsigned reg) { in GetRegisterSize()
150 RegisterContextPOSIX_ppc64le::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex()
174 const char *RegisterContextPOSIX_ppc64le::GetRegisterName(unsigned reg) { in GetRegisterName()
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| D | RegisterContextPOSIX_arm.cpp | 28 bool RegisterContextPOSIX_arm::IsGPR(unsigned reg) { in IsGPR()
35 bool RegisterContextPOSIX_arm::IsFPR(unsigned reg) { in IsFPR()
54 unsigned RegisterContextPOSIX_arm::GetRegisterOffset(unsigned reg) { in GetRegisterOffset()
58 unsigned RegisterContextPOSIX_arm::GetRegisterSize(unsigned reg) { in GetRegisterSize()
78 RegisterContextPOSIX_arm::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex()
94 const char *RegisterContextPOSIX_arm::GetRegisterName(unsigned reg) { in GetRegisterName()
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| D | RegisterContextPOSIX_arm64.cpp | 28 bool RegisterContextPOSIX_arm64::IsGPR(unsigned reg) { in IsGPR()
35 bool RegisterContextPOSIX_arm64::IsFPR(unsigned reg) { in IsFPR()
61 unsigned RegisterContextPOSIX_arm64::GetRegisterOffset(unsigned reg) { in GetRegisterOffset()
65 unsigned RegisterContextPOSIX_arm64::GetRegisterSize(unsigned reg) { in GetRegisterSize()
86 RegisterContextPOSIX_arm64::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex()
102 const char *RegisterContextPOSIX_arm64::GetRegisterName(unsigned reg) { in GetRegisterName()
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| D | RegisterContextPOSIX_powerpc.cpp | 79 bool RegisterContextPOSIX_powerpc::IsGPR(unsigned reg) { in IsGPR()
83 bool RegisterContextPOSIX_powerpc::IsFPR(unsigned reg) { in IsFPR()
87 bool RegisterContextPOSIX_powerpc::IsVMX(unsigned reg) { in IsVMX()
104 unsigned RegisterContextPOSIX_powerpc::GetRegisterOffset(unsigned reg) { in GetRegisterOffset()
109 unsigned RegisterContextPOSIX_powerpc::GetRegisterSize(unsigned reg) { in GetRegisterSize()
131 RegisterContextPOSIX_powerpc::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex()
155 const char *RegisterContextPOSIX_powerpc::GetRegisterName(unsigned reg) { in GetRegisterName()
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| D | RegisterInfos_i386.h | 44 #define FPR_SIZE(reg) sizeof(((FXSAVE *)nullptr)->reg) argument
61 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ argument
70 #define DEFINE_FPR(name, reg, kind1, kind2, kind3, kind4) \ argument
80 #define DEFINE_FP_ST(reg, i) \ argument
90 #define DEFINE_FP_MM(reg, i, streg) \ argument
100 #define DEFINE_XMM(reg, i) \ argument
112 #define DEFINE_YMM(reg, i) \ argument
122 #define DEFINE_BNDR(reg, i) \ argument
141 #define DEFINE_DR(reg, i) \ argument
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| D | RegisterContextPOSIX_s390x.cpp | 72 bool RegisterContextPOSIX_s390x::IsGPR(unsigned reg) { in IsGPR()
76 bool RegisterContextPOSIX_s390x::IsFPR(unsigned reg) { in IsFPR()
112 RegisterContextPOSIX_s390x::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex()
123 unsigned RegisterContextPOSIX_s390x::GetRegisterOffset(unsigned reg) { in GetRegisterOffset()
128 unsigned RegisterContextPOSIX_s390x::GetRegisterSize(unsigned reg) { in GetRegisterSize()
133 const char *RegisterContextPOSIX_s390x::GetRegisterName(unsigned reg) { in GetRegisterName()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_build_pm4.h | 42 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
57 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
66 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
72 static inline void radeon_set_context_reg_seq_array(struct radeon_cmdbuf *cs, unsigned reg, in radeon_set_context_reg_seq_array()
79 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, in radeon_set_context_reg_idx()
90 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
99 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
105 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq()
114 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg()
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 66 scan_register_key(const scan_register *reg) in scan_register_key()
76 fill_scan_register1d(scan_register *reg, in fill_scan_register1d()
86 fill_scan_register2d(scan_register *reg, in fill_scan_register2d()
96 scan_register_dst(scan_register *reg, in scan_register_dst()
114 scan_register_src(scan_register *reg, in scan_register_src()
134 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_src() local
143 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_dst() local
202 const scan_register *reg) in is_register_declared()
219 scan_register *reg = (scan_register *)cso_hash_iter_data(iter); in is_any_register_declared() local
231 scan_register *reg) in is_register_used()
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 67 scan_register_key(const scan_register *reg) in scan_register_key()
77 fill_scan_register1d(scan_register *reg, in fill_scan_register1d()
87 fill_scan_register2d(scan_register *reg, in fill_scan_register2d()
97 scan_register_dst(scan_register *reg, in scan_register_dst()
115 scan_register_src(scan_register *reg, in scan_register_src()
135 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_src() local
144 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_dst() local
203 const scan_register *reg) in is_register_declared()
220 scan_register *reg = (scan_register *)cso_hash_iter_data(iter); in is_any_register_declared() local
232 scan_register *reg) in is_register_used()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_sanity.c | 322 struct reg { struct
324 struct reg_names *closest; argument
334 static struct reg regs[ARRAY_SIZE(reg_names)+1]; argument
370 static int find_or_add_value( struct reg *reg, int val ) in find_or_add_value()
388 static struct reg *lookup_reg( struct reg *tab, int reg ) in lookup_reg()
402 static const char *get_reg_name( struct reg *reg ) in get_reg_name()
429 static int print_int_reg_assignment( struct reg *reg, int data ) in print_int_reg_assignment()
453 static int print_float_reg_assignment( struct reg *reg, float data ) in print_float_reg_assignment()
484 static int print_reg_assignment( struct reg *reg, int data ) in print_reg_assignment()
495 static void print_reg( struct reg *reg ) in print_reg()
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| /external/tensorflow/tensorflow/lite/kernels/internal/optimized/ |
| D | depthwiseconv_uint8_transitional.h | 40 inline void util_vst1_x8(uint8* data_addr, int8x8_t reg) { in util_vst1_x8()
43 inline void util_vst1_x8(int8* data_addr, int8x8_t reg) { in util_vst1_x8()
51 #define vst1_lane_8x4(dst, reg, lane_num) \ argument
54 #define vst1q_lane_8x4(dst, reg, lane_num) \ argument
61 #define vld1q_lane_s8x8(src, reg, lane_num) \ argument
63 #define vld1_lane_8x4(src, reg, lane_num) \ argument
65 #define vld1q_lane_8x4(src, reg, lane_num) \ argument
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| /external/google-breakpad/src/common/ |
| D | dwarf_cfi_to_module.cc | 178 unsigned reg = i; in RegisterName() local
192 void DwarfCFIToModule::Record(Module::Address address, int reg, in Record()
212 bool DwarfCFIToModule::UndefinedRule(uint64_t address, int reg) { in UndefinedRule()
218 bool DwarfCFIToModule::SameValueRule(uint64_t address, int reg) { in SameValueRule()
225 bool DwarfCFIToModule::OffsetRule(uint64_t address, int reg, in OffsetRule()
233 bool DwarfCFIToModule::ValOffsetRule(uint64_t address, int reg, in ValOffsetRule()
241 bool DwarfCFIToModule::RegisterRule(uint64_t address, int reg, in RegisterRule()
249 bool DwarfCFIToModule::ExpressionRule(uint64_t address, int reg, in ExpressionRule()
256 bool DwarfCFIToModule::ValExpressionRule(uint64_t address, int reg, in ValExpressionRule()
269 void DwarfCFIToModule::Reporter::UnnamedRegister(size_t offset, int reg) { in UnnamedRegister()
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| /external/llvm-project/lldb/source/Plugins/Process/Windows/Common/arm64/ |
| D | RegisterContextWindows_arm64.cpp | 26 #define GPR_OFFSET_NAME(reg) 0 argument
29 #define FPU_OFFSET_NAME(reg) 0 argument
31 #define EXC_OFFSET_NAME(reg) 0 argument
32 #define DBG_OFFSET_NAME(reg) 0 argument
34 #define DEFINE_DBG(reg, i) \ argument
103 RegisterContextWindows_arm64::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex()
126 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; in ReadRegister() local
340 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; in WriteRegister() local
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_sanity.c | 600 struct reg { struct
602 struct reg_names *closest; argument
612 static struct reg regs[ARRAY_SIZE(reg_names)+1]; argument
648 static int find_or_add_value( struct reg *reg, int val ) in find_or_add_value()
666 static struct reg *lookup_reg( struct reg *tab, int reg ) in lookup_reg()
680 static const char *get_reg_name( struct reg *reg ) in get_reg_name()
707 static int print_int_reg_assignment( struct reg *reg, int data ) in print_int_reg_assignment()
731 static int print_float_reg_assignment( struct reg *reg, float data ) in print_float_reg_assignment()
762 static int print_reg_assignment( struct reg *reg, int data ) in print_reg_assignment()
773 static void print_reg( struct reg *reg ) in print_reg()
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| /external/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_asm.h | 27 # define CFI_REL_OFFSET(reg, n) .cfi_rel_offset reg, n argument
28 # define CFI_OFFSET(reg, n) .cfi_offset reg, n argument
29 # define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
30 # define CFI_DEF_CFA(reg, n) .cfi_def_cfa reg, n argument
31 # define CFI_RESTORE(reg) .cfi_restore reg argument
39 # define CFI_REL_OFFSET(reg, n) argument
40 # define CFI_OFFSET(reg, n) argument
41 # define CFI_DEF_CFA_REGISTER(reg) argument
42 # define CFI_DEF_CFA(reg, n) argument
43 # define CFI_RESTORE(reg) argument
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_ir_vec4.h | 57 retype(src_reg reg, enum brw_reg_type type) in retype()
66 add_byte_offset(backend_reg *reg, unsigned bytes) in add_byte_offset()
100 byte_offset(src_reg reg, unsigned bytes) in byte_offset()
107 offset(src_reg reg, unsigned width, unsigned delta) in offset()
115 horiz_offset(src_reg reg, unsigned delta) in horiz_offset()
125 swizzle(src_reg reg, unsigned swizzle) in swizzle()
136 negate(src_reg reg) in negate()
144 is_uniform(const src_reg ®) in is_uniform()
174 retype(dst_reg reg, enum brw_reg_type type) in retype()
181 byte_offset(dst_reg reg, unsigned bytes) in byte_offset()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_cs.h | 131 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
139 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
145 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
153 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
160 unsigned reg, unsigned idx, in radeon_set_context_reg_idx()
170 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
178 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
184 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq()
192 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg()
199 unsigned reg, unsigned idx, in radeon_set_uconfig_reg_idx()
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| /external/llvm-project/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_asm.h | 26 # define CFI_REL_OFFSET(reg, n) .cfi_rel_offset reg, n argument
27 # define CFI_OFFSET(reg, n) .cfi_offset reg, n argument
28 # define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
29 # define CFI_DEF_CFA(reg, n) .cfi_def_cfa reg, n argument
30 # define CFI_RESTORE(reg) .cfi_restore reg argument
38 # define CFI_REL_OFFSET(reg, n) argument
39 # define CFI_OFFSET(reg, n) argument
40 # define CFI_DEF_CFA_REGISTER(reg) argument
41 # define CFI_DEF_CFA(reg, n) argument
42 # define CFI_RESTORE(reg) argument
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | i915_program.c | 42 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
43 #define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
44 #define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
45 #define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT) argument
46 #define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT) argument
47 #define A1_SRC1( reg ) (((reg)&UREG_MASK)>>UREG_A1_SRC1_SHIFT_LEFT) argument
48 #define A2_SRC1( reg ) (((reg)&UREG_MASK)<<UREG_A2_SRC1_SHIFT_RIGHT) argument
49 #define A2_SRC2( reg ) (((reg)&UREG_MASK)>>UREG_A2_SRC2_SHIFT_LEFT) argument
53 #define T0_SAMPLER( reg ) (GET_UREG_NR(reg)<<T0_SAMPLER_NR_SHIFT) argument
54 #define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \ argument
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi_private.cpp | 54 st_src_reg *reg = ralloc(input, st_src_reg); in dup_reladdr() local
141 st_src_reg::st_src_reg(const st_src_reg ®) in st_src_reg()
146 void st_src_reg::operator=(const st_src_reg ®) in operator =()
163 st_src_reg::st_src_reg(st_dst_reg reg) in st_src_reg()
182 st_src_reg reg = *this; in get_abs() local
226 std::ostream& operator << (std::ostream& os, const st_src_reg& reg) in operator <<()
262 st_dst_reg::st_dst_reg(st_src_reg reg) in st_dst_reg()
316 st_dst_reg::st_dst_reg(const st_dst_reg ®) in st_dst_reg()
321 void st_dst_reg::operator=(const st_dst_reg ®) in operator =()
366 std::ostream& operator << (std::ostream& os, const st_dst_reg& reg) in operator <<()
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| /external/llvm-project/lldb/source/Plugins/Process/Windows/Common/arm/ |
| D | RegisterContextWindows_arm.cpp | 28 #define EXC_OFFSET(reg) 0 argument
29 #define DBG_OFFSET_NAME(reg) 0 argument
31 #define DEFINE_DBG(reg, i) \ argument
89 RegisterContextWindows_arm::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex()
111 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; in ReadRegister() local
276 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; in WriteRegister() local
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| /external/igt-gpu-tools/lib/ |
| D | intel_mmio.c | 245 intel_register_read(uint32_t reg) in intel_register_read()
286 intel_register_write(uint32_t reg, uint32_t val) in intel_register_write()
322 uint32_t INREG(uint32_t reg) in INREG()
339 uint16_t INREG16(uint32_t reg) in INREG16()
356 uint8_t INREG8(uint32_t reg) in INREG8()
372 void OUTREG(uint32_t reg, uint32_t val) in OUTREG()
388 void OUTREG16(uint32_t reg, uint16_t val) in OUTREG16()
404 void OUTREG8(uint32_t reg, uint8_t val) in OUTREG8()
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