| /external/vixl/src/aarch64/ |
| D | registers-aarch64.cc | 175 const CPURegister& reg3, in AreAliased()
226 const CPURegister& reg3, in AreSameSizeAndType()
246 const CPURegister& reg3, in AreEven()
266 const CPURegister& reg3, in AreConsecutive()
296 const CPURegister& reg3, in AreSameFormat()
308 const CPURegister& reg3, in AreSameLaneSize()
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| D | macro-assembler-aarch64.cc | 2951 const Register& reg3, in Include()
2965 const VRegister& reg3, in Include()
2975 const CPURegister& reg3, in Include()
3015 const Register& reg3, in Exclude()
3025 const VRegister& reg3, in Exclude()
3035 const CPURegister& reg3, in Exclude()
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| /external/libvpx/libvpx/vpx_ports/ |
| D | asmdefs_mmi.h | 21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
50 #define MMI_ADDU(reg1, reg2, reg3) \ argument
59 #define MMI_SUBU(reg1, reg2, reg3) \ argument
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 45 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
129 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
355 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
435 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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| D | idct16x16_msa.c | 17 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
111 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_columns_addblk_msa() local
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| /external/libyuv/files/source/ |
| D | compare_msa.cc | 59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1089 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1163 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1379 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
1512 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1561 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1660 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
[all …]
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | compare_msa.cc | 59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1089 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1163 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1379 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
1512 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1561 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1660 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
[all …]
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| /external/tensorflow/tensorflow/lite/tools/serialization/ |
| D | writer_lib_test.cc | 215 const TfLiteRegistration* reg3 = resolver.FindOp(BuiltinOperator_RELU6, 1); in TEST_P() local
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| /external/mesa3d/src/panfrost/bifrost/ |
| D | bifrost.h | 257 unsigned reg3 : 6; member
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 554 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList()
557 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList()
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| D | macro-assembler-aarch32.cc | 449 CPURegister reg3, in Printf()
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| /external/libaom/libaom/av1/common/arm/ |
| D | convolve_neon.c | 1168 int16x4_t reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, in av1_convolve_2d_sr_neon() local
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 72 #define IS_3_LO_REGS(reg1, reg2, reg3) \ argument
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