| /external/vixl/src/aarch64/ |
| D | registers-aarch64.cc | 176 const CPURegister& reg4, in AreAliased()
227 const CPURegister& reg4, in AreSameSizeAndType()
247 const CPURegister& reg4, in AreEven()
267 const CPURegister& reg4) { in AreConsecutive()
297 const CPURegister& reg4) { in AreSameFormat()
309 const CPURegister& reg4) { in AreSameLaneSize()
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| D | macro-assembler-aarch64.cc | 2952 const Register& reg4) { in Include()
2966 const VRegister& reg4) { in Include()
2976 const CPURegister& reg4) { in Include()
3016 const Register& reg4) { in Exclude()
3026 const VRegister& reg4) { in Exclude()
3036 const CPURegister& reg4) { in Exclude()
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 45 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
129 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
355 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
435 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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| D | idct16x16_msa.c | 16 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
110 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_columns_addblk_msa() local
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| /external/libyuv/files/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1512 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1561 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1660 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
1717 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToYRow_MSA() local
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1512 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1561 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1660 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
1717 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToYRow_MSA() local
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| /external/libaom/libaom/av1/common/arm/ |
| D | convolve_neon.c | 1168 int16x4_t reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, in av1_convolve_2d_sr_neon() local
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 450 CPURegister reg4) { in Printf()
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| D | instructions-aarch32.h | 557 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList()
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