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Searched defs:reg8 (Results 1 – 11 of 11) sorted by relevance

/external/vixl/src/aarch64/
Dregisters-aarch64.cc180 const CPURegister& reg8) { in AreAliased()
231 const CPURegister& reg8) { in AreSameSizeAndType()
251 const CPURegister& reg8) { in AreEven()
/external/llvm-project/lldb/source/Plugins/Process/Utility/
DRegisterInfos_i386.h162 #define DEFINE_GPR_PSEUDO_8H(reg8, reg32) \ argument
173 #define DEFINE_GPR_PSEUDO_8L(reg8, reg32) \ argument
DRegisterInfos_x86_64.h175 #define DEFINE_GPR_PSEUDO_8H(reg8, reg64) \ argument
186 #define DEFINE_GPR_PSEUDO_8L(reg8, reg64) \ argument
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c16 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
110 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_columns_addblk_msa() local
/external/libvpx/libvpx/third_party/libyuv/source/
Dscale_msa.cc767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
Drow_msa.cc826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
/external/libyuv/files/source/
Dscale_msa.cc767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
Drow_msa.cc826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
/external/llvm-project/lldb/tools/debugserver/source/MacOSX/i386/
DDNBArchImplI386.cpp1186 #define DEFINE_GPR_PSEUDO_8H(reg8, reg32) \ argument
1192 #define DEFINE_GPR_PSEUDO_8L(reg8, reg32) \ argument
/external/llvm-project/lldb/tools/debugserver/source/MacOSX/x86_64/
DDNBArchImplX86_64.cpp1622 #define DEFINE_GPR_PSEUDO_8H(reg8, reg64) \ argument
1628 #define DEFINE_GPR_PSEUDO_8L(reg8, reg64) \ argument
/external/libaom/libaom/av1/common/arm/
Dconvolve_neon.c1168 int16x4_t reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, in av1_convolve_2d_sr_neon() local