| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
| D | pr38575.s | 12 ror x1, x2, x3 label
|
| /external/llvm-project/llvm/test/MC/RISCV/ |
| D | rv32zbbp-valid.s | 36 ror t0, t1, t2 label
|
| D | rv32zbbp-invalid.s | 12 ror t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction label
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 74 ShiftType ror; member
1233 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 74 ShiftType ror; member
1345 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 139 ShiftType ror; member
597 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 139 ShiftType ror; member
597 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 140 ShiftType ror; member
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 140 ShiftType ror; member
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| /external/capstone/arch/AArch64/ |
| D | AArch64AddressingModes.h | 119 static inline uint64_t ror(uint64_t elt, unsigned size) in ror() function
|
| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 639 static inline uint32_t ror(uint32_t x, int i) { in ror() function
|
| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 475 ror w0, w1, w2 label
476 ror x3, x4, x5 label
483 ror w24, w25, w26 label
484 ror x27, x28, x29 label
550 ror x19, x23, #24 label
551 ror x29, xzr, #63 label
552 ror w9, w13, #31 label
|
| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | ARMUtils.h | 273 static uint32_t ror(uint32_t val, uint32_t N, uint32_t shift) { in ror() function
|
| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 32 ror, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 32 ror, enumerator
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 32 ror, enumerator
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 205 static inline uint64_t ror(uint64_t elt, unsigned size) { in ror() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 205 static inline uint64_t ror(uint64_t elt, unsigned size) { in ror() function
|
| /external/mesa3d/src/intel/isl/ |
| D | isl_tiled_memcpy.c | 62 ror(uint32_t n, uint32_t d) in ror() function
|
| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 205 static inline uint64_t ror(uint64_t elt, unsigned size) { in ror() function
|
| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 225 ror r0, r1, #1 label
|
| D | m4-int.s | 232 ror r0, r1, #1 label
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 918 void ror(const Register& rd, const Register& rs, unsigned shift) { in ror() function
|