| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 243 sbcs r0, r1, #1 label
244 sbcs r0, r1 label
246 sbcs r0, r1, r2 label
248 sbcs r0, r1, r2, LSL #1 label
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| D | m4-int.s | 250 sbcs r0, r1, #1 label
251 sbcs r0, r1 label
253 sbcs r0, r1, r2 label
255 sbcs r0, r1, r2, LSL #1 label
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| /external/python/cpython3/Tools/unicode/ |
| D | genmap_support.py | 183 def loadmap(fo, natcol=0, unicol=1, sbcs=0): argument
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| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 219 sbcs w29, w27, w25 label
220 sbcs wzr, w3, w4 label
222 sbcs w20, w0, wzr label
223 sbcs x29, x27, x25 label
224 sbcs xzr, x3, x4 label
226 sbcs x20, x0, xzr label
|
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 234 void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) { in sbcs() function in dart::Assembler
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| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 283 __ sbcs(w10, w11, w12); in GenerateTestSequenceBase() local
284 __ sbcs(x13, x14, x15); in GenerateTestSequenceBase() local
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3004 void sbcs(Register rd, Register rn, const Operand& operand) { in sbcs() function
3007 void sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { in sbcs() function
3010 void sbcs(EncodingSize size, in sbcs() function
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| D | assembler-aarch32.cc | 9516 void Assembler::sbcs(Condition cond, in sbcs() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 2440 void Disassembler::sbcs(Condition cond, in sbcs() function in vixl::aarch32::Disassembler
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 542 void Assembler::sbcs(const Register& rd, in sbcs() function in vixl::aarch64::Assembler
|