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1 /**************************************************************************
2  *
3  * Copyright 2017 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include "radeon_vcn_dec.h"
29 
30 #include "pipe/p_video_codec.h"
31 #include "radeon_video.h"
32 #include "radeonsi/si_pipe.h"
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35 #include "vl/vl_mpeg12_decoder.h"
36 #include "vl/vl_probs_table.h"
37 #include "pspdecryptionparam.h"
38 
39 #include <assert.h>
40 #include <stdio.h>
41 
42 #define FB_BUFFER_OFFSET             0x1000
43 #define FB_BUFFER_SIZE               2048
44 #define IT_SCALING_TABLE_SIZE        992
45 #define VP9_PROBS_TABLE_SIZE         (RDECODE_VP9_PROBS_DATA_SIZE + 256)
46 #define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024)
47 
48 #define RDECODE_VCN1_GPCOM_VCPU_CMD   0x2070c
49 #define RDECODE_VCN1_GPCOM_VCPU_DATA0 0x20710
50 #define RDECODE_VCN1_GPCOM_VCPU_DATA1 0x20714
51 #define RDECODE_VCN1_ENGINE_CNTL      0x20718
52 
53 #define RDECODE_VCN2_GPCOM_VCPU_CMD   (0x503 << 2)
54 #define RDECODE_VCN2_GPCOM_VCPU_DATA0 (0x504 << 2)
55 #define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2)
56 #define RDECODE_VCN2_ENGINE_CNTL      (0x506 << 2)
57 
58 #define RDECODE_VCN2_5_GPCOM_VCPU_CMD   0x3c
59 #define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40
60 #define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44
61 #define RDECODE_VCN2_5_ENGINE_CNTL      0x9b4
62 
63 #define NUM_MPEG2_REFS 6
64 #define NUM_H264_REFS  17
65 #define NUM_VC1_REFS   5
66 #define NUM_VP9_REFS   8
67 
68 static unsigned calc_dpb_size(struct radeon_decoder *dec);
69 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec);
70 static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec);
71 static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec,
72                                           struct pipe_h265_picture_desc *pic);
73 
get_h264_msg(struct radeon_decoder * dec,struct pipe_h264_picture_desc * pic)74 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
75                                            struct pipe_h264_picture_desc *pic)
76 {
77    rvcn_dec_message_avc_t result;
78 
79    memset(&result, 0, sizeof(result));
80    switch (pic->base.profile) {
81    case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
82    case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
83       result.profile = RDECODE_H264_PROFILE_BASELINE;
84       break;
85 
86    case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
87       result.profile = RDECODE_H264_PROFILE_MAIN;
88       break;
89 
90    case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
91       result.profile = RDECODE_H264_PROFILE_HIGH;
92       break;
93 
94    default:
95       assert(0);
96       break;
97    }
98 
99    result.level = dec->base.level;
100 
101    result.sps_info_flags = 0;
102    result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
103    result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
104    result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
105    result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
106    result.sps_info_flags |= 1 << RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT;
107 
108    result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
109    result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
110    result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
111    result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
112    result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
113 
114    switch (dec->base.chroma_format) {
115    case PIPE_VIDEO_CHROMA_FORMAT_NONE:
116       break;
117    case PIPE_VIDEO_CHROMA_FORMAT_400:
118       result.chroma_format = 0;
119       break;
120    case PIPE_VIDEO_CHROMA_FORMAT_420:
121       result.chroma_format = 1;
122       break;
123    case PIPE_VIDEO_CHROMA_FORMAT_422:
124       result.chroma_format = 2;
125       break;
126    case PIPE_VIDEO_CHROMA_FORMAT_444:
127       result.chroma_format = 3;
128       break;
129    }
130 
131    result.pps_info_flags = 0;
132    result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
133    result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
134    result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
135    result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
136    result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
137    result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
138    result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
139    result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
140 
141    result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
142    result.slice_group_map_type = pic->pps->slice_group_map_type;
143    result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
144    result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
145    result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
146    result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
147 
148    memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6 * 16);
149    memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2 * 64);
150 
151    memcpy(dec->it, result.scaling_list_4x4, 6 * 16);
152    memcpy((dec->it + 96), result.scaling_list_8x8, 2 * 64);
153 
154    result.num_ref_frames = pic->num_ref_frames;
155 
156    result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
157    result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
158 
159    result.frame_num = pic->frame_num;
160    memcpy(result.frame_num_list, pic->frame_num_list, 4 * 16);
161    result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
162    result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
163    memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4 * 16 * 2);
164 
165    result.decoded_pic_idx = pic->frame_num;
166 
167    return result;
168 }
169 
radeon_dec_destroy_associated_data(void * data)170 static void radeon_dec_destroy_associated_data(void *data)
171 {
172    /* NOOP, since we only use an intptr */
173 }
174 
get_h265_msg(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_h265_picture_desc * pic)175 static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
176                                             struct pipe_video_buffer *target,
177                                             struct pipe_h265_picture_desc *pic)
178 {
179    rvcn_dec_message_hevc_t result;
180    unsigned i, j;
181 
182    memset(&result, 0, sizeof(result));
183    result.sps_info_flags = 0;
184    result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
185    result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
186    result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
187    result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
188    result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
189    result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
190    result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
191    result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
192    result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
193    if (((struct si_screen *)dec->screen)->info.family == CHIP_CARRIZO)
194       result.sps_info_flags |= 1 << 9;
195    if (pic->UseRefPicList == true)
196       result.sps_info_flags |= 1 << 10;
197 
198    result.chroma_format = pic->pps->sps->chroma_format_idc;
199    result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
200    result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
201    result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
202    result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
203    result.log2_min_luma_coding_block_size_minus3 =
204       pic->pps->sps->log2_min_luma_coding_block_size_minus3;
205    result.log2_diff_max_min_luma_coding_block_size =
206       pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
207    result.log2_min_transform_block_size_minus2 =
208       pic->pps->sps->log2_min_transform_block_size_minus2;
209    result.log2_diff_max_min_transform_block_size =
210       pic->pps->sps->log2_diff_max_min_transform_block_size;
211    result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
212    result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
213    result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
214    result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
215    result.log2_min_pcm_luma_coding_block_size_minus3 =
216       pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
217    result.log2_diff_max_min_pcm_luma_coding_block_size =
218       pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
219    result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
220 
221    result.pps_info_flags = 0;
222    result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
223    result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
224    result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
225    result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
226    result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
227    result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
228    result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
229    result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
230    result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
231    result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
232    result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
233    result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
234    result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
235    result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
236    result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
237    result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
238    result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
239    result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
240    result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
241    result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
242 
243    result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
244    result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
245    result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
246    result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
247    result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
248    result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
249    result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
250    result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
251    result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
252    result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
253    result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
254    result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
255    result.init_qp_minus26 = pic->pps->init_qp_minus26;
256 
257    for (i = 0; i < 19; ++i)
258       result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
259 
260    for (i = 0; i < 21; ++i)
261       result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
262 
263    result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
264    result.curr_poc = pic->CurrPicOrderCntVal;
265 
266    for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); i++) {
267       for (j = 0;
268            (pic->ref[j] != NULL) && (j < ARRAY_SIZE(dec->render_pic_list));
269            j++) {
270          if (dec->render_pic_list[i] == pic->ref[j])
271             break;
272          if (j == ARRAY_SIZE(dec->render_pic_list) - 1)
273             dec->render_pic_list[i] = NULL;
274          else if (pic->ref[j + 1] == NULL)
275             dec->render_pic_list[i] = NULL;
276       }
277    }
278    for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); i++) {
279       if (dec->render_pic_list[i] == NULL) {
280          dec->render_pic_list[i] = target;
281          result.curr_idx = i;
282          break;
283       }
284    }
285 
286    vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)result.curr_idx,
287                                        &radeon_dec_destroy_associated_data);
288 
289    for (i = 0; i < 16; ++i) {
290       struct pipe_video_buffer *ref = pic->ref[i];
291       uintptr_t ref_pic = 0;
292 
293       result.poc_list[i] = pic->PicOrderCntVal[i];
294 
295       if (ref)
296          ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
297       else
298          ref_pic = 0x7F;
299       result.ref_pic_list[i] = ref_pic;
300    }
301 
302    for (i = 0; i < 8; ++i) {
303       result.ref_pic_set_st_curr_before[i] = 0xFF;
304       result.ref_pic_set_st_curr_after[i] = 0xFF;
305       result.ref_pic_set_lt_curr[i] = 0xFF;
306    }
307 
308    for (i = 0; i < pic->NumPocStCurrBefore; ++i)
309       result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
310 
311    for (i = 0; i < pic->NumPocStCurrAfter; ++i)
312       result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
313 
314    for (i = 0; i < pic->NumPocLtCurr; ++i)
315       result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
316 
317    for (i = 0; i < 6; ++i)
318       result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
319 
320    for (i = 0; i < 2; ++i)
321       result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
322 
323    memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
324    memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
325    memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
326    memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
327 
328    for (i = 0; i < 2; i++) {
329       for (j = 0; j < 15; j++)
330          result.direct_reflist[i][j] = pic->RefPicList[i][j];
331    }
332 
333    if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
334       if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
335          result.p010_mode = 1;
336          result.msb_mode = 1;
337       } else {
338          result.p010_mode = 0;
339          result.luma_10to8 = 5;
340          result.chroma_10to8 = 5;
341          result.hevc_reserved[0] = 4; /* sclr_luma10to8 */
342          result.hevc_reserved[1] = 4; /* sclr_chroma10to8 */
343       }
344    }
345 
346    return result;
347 }
348 
fill_probs_table(void * ptr)349 static void fill_probs_table(void *ptr)
350 {
351    rvcn_dec_vp9_probs_t *probs = (rvcn_dec_vp9_probs_t *)ptr;
352 
353    memcpy(&probs->coef_probs[0], default_coef_probs_4x4, sizeof(default_coef_probs_4x4));
354    memcpy(&probs->coef_probs[1], default_coef_probs_8x8, sizeof(default_coef_probs_8x8));
355    memcpy(&probs->coef_probs[2], default_coef_probs_16x16, sizeof(default_coef_probs_16x16));
356    memcpy(&probs->coef_probs[3], default_coef_probs_32x32, sizeof(default_coef_probs_32x32));
357    memcpy(probs->y_mode_prob, default_if_y_probs, sizeof(default_if_y_probs));
358    memcpy(probs->uv_mode_prob, default_if_uv_probs, sizeof(default_if_uv_probs));
359    memcpy(probs->single_ref_prob, default_single_ref_p, sizeof(default_single_ref_p));
360    memcpy(probs->switchable_interp_prob, default_switchable_interp_prob,
361           sizeof(default_switchable_interp_prob));
362    memcpy(probs->partition_prob, default_partition_probs, sizeof(default_partition_probs));
363    memcpy(probs->inter_mode_probs, default_inter_mode_probs, sizeof(default_inter_mode_probs));
364    memcpy(probs->mbskip_probs, default_skip_probs, sizeof(default_skip_probs));
365    memcpy(probs->intra_inter_prob, default_intra_inter_p, sizeof(default_intra_inter_p));
366    memcpy(probs->comp_inter_prob, default_comp_inter_p, sizeof(default_comp_inter_p));
367    memcpy(probs->comp_ref_prob, default_comp_ref_p, sizeof(default_comp_ref_p));
368    memcpy(probs->tx_probs_32x32, default_tx_probs_32x32, sizeof(default_tx_probs_32x32));
369    memcpy(probs->tx_probs_16x16, default_tx_probs_16x16, sizeof(default_tx_probs_16x16));
370    memcpy(probs->tx_probs_8x8, default_tx_probs_8x8, sizeof(default_tx_probs_8x8));
371    memcpy(probs->mv_joints, default_nmv_joints, sizeof(default_nmv_joints));
372    memcpy(&probs->mv_comps[0], default_nmv_components, sizeof(default_nmv_components));
373    memset(&probs->nmvc_mask, 0, sizeof(rvcn_dec_vp9_nmv_ctx_mask_t));
374 }
375 
get_vp9_msg(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_vp9_picture_desc * pic)376 static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
377                                           struct pipe_video_buffer *target,
378                                           struct pipe_vp9_picture_desc *pic)
379 {
380    rvcn_dec_message_vp9_t result;
381    unsigned i ,j;
382 
383    memset(&result, 0, sizeof(result));
384 
385    /* segment table */
386    rvcn_dec_vp9_probs_segment_t *prbs = (rvcn_dec_vp9_probs_segment_t *)(dec->probs);
387 
388    if (pic->picture_parameter.pic_fields.segmentation_enabled) {
389       for (i = 0; i < 8; ++i) {
390          prbs->seg.feature_data[i] =
391             (pic->slice_parameter.seg_param[i].alt_quant & 0xffff) |
392             ((pic->slice_parameter.seg_param[i].alt_lf & 0xff) << 16) |
393             ((pic->slice_parameter.seg_param[i].segment_flags.segment_reference & 0xf) << 24);
394          prbs->seg.feature_mask[i] =
395             (pic->slice_parameter.seg_param[i].alt_quant_enabled << 0) |
396             (pic->slice_parameter.seg_param[i].alt_lf_enabled << 1) |
397             (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_enabled << 2) |
398             (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_skipped << 3);
399       }
400 
401       for (i = 0; i < 7; ++i)
402          prbs->seg.tree_probs[i] = pic->picture_parameter.mb_segment_tree_probs[i];
403 
404       for (i = 0; i < 3; ++i)
405          prbs->seg.pred_probs[i] = pic->picture_parameter.segment_pred_probs[i];
406 
407       prbs->seg.abs_delta = pic->picture_parameter.abs_delta;
408    } else
409       memset(&prbs->seg, 0, 256);
410 
411    result.frame_header_flags = (pic->picture_parameter.pic_fields.frame_type
412                                 << RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT) &
413                                RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK;
414 
415    result.frame_header_flags |= (pic->picture_parameter.pic_fields.error_resilient_mode
416                                  << RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT) &
417                                 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK;
418 
419    result.frame_header_flags |= (pic->picture_parameter.pic_fields.intra_only
420                                  << RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT) &
421                                 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK;
422 
423    result.frame_header_flags |= (pic->picture_parameter.pic_fields.allow_high_precision_mv
424                                  << RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT) &
425                                 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK;
426 
427    result.frame_header_flags |= (pic->picture_parameter.pic_fields.frame_parallel_decoding_mode
428                                  << RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT) &
429                                 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK;
430 
431    result.frame_header_flags |= (pic->picture_parameter.pic_fields.refresh_frame_context
432                                  << RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT) &
433                                 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK;
434 
435    result.frame_header_flags |= (pic->picture_parameter.pic_fields.segmentation_enabled
436                                  << RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT) &
437                                 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK;
438 
439    result.frame_header_flags |= (pic->picture_parameter.pic_fields.segmentation_update_map
440                                  << RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT) &
441                                 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK;
442 
443    result.frame_header_flags |= (pic->picture_parameter.pic_fields.segmentation_temporal_update
444                                  << RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT) &
445                                 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK;
446 
447    result.frame_header_flags |= (pic->picture_parameter.mode_ref_delta_enabled
448                                  << RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT) &
449                                 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK;
450 
451    result.frame_header_flags |= (pic->picture_parameter.mode_ref_delta_update
452                                  << RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT) &
453                                 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK;
454 
455    result.frame_header_flags |=
456       ((dec->show_frame && !pic->picture_parameter.pic_fields.error_resilient_mode)
457        << RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT) &
458       RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK;
459    dec->show_frame = pic->picture_parameter.pic_fields.show_frame;
460 
461    result.interp_filter = pic->picture_parameter.pic_fields.mcomp_filter_type;
462 
463    result.frame_context_idx = pic->picture_parameter.pic_fields.frame_context_idx;
464    result.reset_frame_context = pic->picture_parameter.pic_fields.reset_frame_context;
465 
466    result.filter_level = pic->picture_parameter.filter_level;
467    result.sharpness_level = pic->picture_parameter.sharpness_level;
468 
469    for (i = 0; i < 8; ++i)
470       memcpy(result.lf_adj_level[i], pic->slice_parameter.seg_param[i].filter_level, 4 * 2);
471 
472    if (pic->picture_parameter.pic_fields.lossless_flag) {
473       result.base_qindex = 0;
474       result.y_dc_delta_q = 0;
475       result.uv_ac_delta_q = 0;
476       result.uv_dc_delta_q = 0;
477    } else {
478       result.base_qindex = pic->picture_parameter.base_qindex;
479       result.y_dc_delta_q = pic->picture_parameter.y_dc_delta_q;
480       result.uv_ac_delta_q = pic->picture_parameter.uv_ac_delta_q;
481       result.uv_dc_delta_q = pic->picture_parameter.uv_dc_delta_q;
482    }
483 
484    result.log2_tile_cols = pic->picture_parameter.log2_tile_columns;
485    result.log2_tile_rows = pic->picture_parameter.log2_tile_rows;
486    result.chroma_format = 1;
487    result.bit_depth_luma_minus8 = result.bit_depth_chroma_minus8 =
488       (pic->picture_parameter.bit_depth - 8);
489 
490    result.vp9_frame_size = align(dec->bs_size, 128);
491    result.uncompressed_header_size = pic->picture_parameter.frame_header_length_in_bytes;
492    result.compressed_header_size = pic->picture_parameter.first_partition_size;
493 
494    assert(dec->base.max_references + 1 <= ARRAY_SIZE(dec->render_pic_list));
495 
496    //clear the dec->render list if it is not used as a reference
497    for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); i++) {
498       if (dec->render_pic_list[i]) {
499           for (j=0;j<8;j++) {
500             if (dec->render_pic_list[i] == pic->ref[j])
501                  break;
502 	  }
503 	  if(j == 8)
504              dec->render_pic_list[i] = NULL;
505       }
506    }
507 
508    for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); ++i) {
509       if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
510 	if (target->codec != NULL){
511 	    result.curr_pic_idx =(uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
512 	} else {
513 	    result.curr_pic_idx = i;
514 	    vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)i,
515 						&radeon_dec_destroy_associated_data);
516 	}
517 	break;
518       } else if (!dec->render_pic_list[i]) {
519          dec->render_pic_list[i] = target;
520          result.curr_pic_idx = i;
521          vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)i,
522                                              &radeon_dec_destroy_associated_data);
523          break;
524       }
525    }
526 
527    for (i = 0; i < 8; i++) {
528       result.ref_frame_map[i] =
529          (pic->ref[i]) ? (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base)
530                        : 0x7f;
531    }
532 
533    result.frame_refs[0] = result.ref_frame_map[pic->picture_parameter.pic_fields.last_ref_frame];
534    result.ref_frame_sign_bias[0] = pic->picture_parameter.pic_fields.last_ref_frame_sign_bias;
535    result.frame_refs[1] = result.ref_frame_map[pic->picture_parameter.pic_fields.golden_ref_frame];
536    result.ref_frame_sign_bias[1] = pic->picture_parameter.pic_fields.golden_ref_frame_sign_bias;
537    result.frame_refs[2] = result.ref_frame_map[pic->picture_parameter.pic_fields.alt_ref_frame];
538    result.ref_frame_sign_bias[2] = pic->picture_parameter.pic_fields.alt_ref_frame_sign_bias;
539 
540    if (pic->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
541       if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
542          result.p010_mode = 1;
543          result.msb_mode = 1;
544       } else {
545          result.p010_mode = 0;
546          result.luma_10to8 = 1;
547          result.chroma_10to8 = 1;
548       }
549    }
550 
551    return result;
552 }
553 
set_drm_keys(rvcn_dec_message_drm_t * drm,DECRYPT_PARAMETERS * decrypted)554 static void set_drm_keys(rvcn_dec_message_drm_t *drm, DECRYPT_PARAMETERS *decrypted)
555 {
556    int cbc = decrypted->u.s.cbc;
557    int ctr = decrypted->u.s.ctr;
558    int id = decrypted->u.s.drm_id;
559    int ekc = 1;
560    int data1 = 1;
561    int data2 = 1;
562 
563    drm->drm_cmd = 0;
564    drm->drm_cntl = 0;
565 
566    drm->drm_cntl = 1 << DRM_CNTL_BYPASS_SHIFT;
567 
568    if (cbc || ctr) {
569       drm->drm_cntl = 0 << DRM_CNTL_BYPASS_SHIFT;
570       drm->drm_cmd |= 0xff << DRM_CMD_BYTE_MASK_SHIFT;
571 
572       if (ctr)
573          drm->drm_cmd |= 0x00 << DRM_CMD_ALGORITHM_SHIFT;
574       else if (cbc)
575          drm->drm_cmd |= 0x02 << DRM_CMD_ALGORITHM_SHIFT;
576 
577       drm->drm_cmd |= 1 << DRM_CMD_GEN_MASK_SHIFT;
578       drm->drm_cmd |= ekc << DRM_CMD_UNWRAP_KEY_SHIFT;
579       drm->drm_cmd |= 0 << DRM_CMD_OFFSET_SHIFT;
580       drm->drm_cmd |= data2 << DRM_CMD_CNT_DATA_SHIFT;
581       drm->drm_cmd |= data1 << DRM_CMD_CNT_KEY_SHIFT;
582       drm->drm_cmd |= ekc << DRM_CMD_KEY_SHIFT;
583       drm->drm_cmd |= id << DRM_CMD_SESSION_SEL_SHIFT;
584 
585       if (ekc)
586          memcpy(drm->drm_wrapped_key, decrypted->encrypted_key, 16);
587       if (data1)
588          memcpy(drm->drm_key, decrypted->session_iv, 16);
589       if (data2)
590          memcpy(drm->drm_counter, decrypted->encrypted_iv, 16);
591       drm->drm_offset = 0;
592    }
593 }
594 
calc_ctx_size_h265_main(struct radeon_decoder * dec)595 static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec)
596 {
597    unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
598    unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
599 
600    unsigned max_references = dec->base.max_references + 1;
601 
602    if (dec->base.width * dec->base.height >= 4096 * 2000)
603       max_references = MAX2(max_references, 8);
604    else
605       max_references = MAX2(max_references, 17);
606 
607    width = align(width, 16);
608    height = align(height, 16);
609    return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
610 }
611 
calc_ctx_size_h265_main10(struct radeon_decoder * dec,struct pipe_h265_picture_desc * pic)612 static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec,
613                                           struct pipe_h265_picture_desc *pic)
614 {
615    unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
616    unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
617    unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
618 
619    unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
620    unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
621    unsigned coeff_10bit =
622       (pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
623 
624    unsigned max_references = dec->base.max_references + 1;
625 
626    if (dec->base.width * dec->base.height >= 4096 * 2000)
627       max_references = MAX2(max_references, 8);
628    else
629       max_references = MAX2(max_references, 17);
630 
631    log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
632                    pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
633 
634    width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
635    height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
636 
637    num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
638    context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
639    max_mb_address = (unsigned)ceil(height * 8 / 2048.0);
640 
641    cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
642    db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
643 
644    return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
645 }
646 
get_vc1_msg(struct pipe_vc1_picture_desc * pic)647 static rvcn_dec_message_vc1_t get_vc1_msg(struct pipe_vc1_picture_desc *pic)
648 {
649    rvcn_dec_message_vc1_t result;
650 
651    memset(&result, 0, sizeof(result));
652    switch (pic->base.profile) {
653    case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
654       result.profile = RDECODE_VC1_PROFILE_SIMPLE;
655       result.level = 1;
656       break;
657 
658    case PIPE_VIDEO_PROFILE_VC1_MAIN:
659       result.profile = RDECODE_VC1_PROFILE_MAIN;
660       result.level = 2;
661       break;
662 
663    case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
664       result.profile = RDECODE_VC1_PROFILE_ADVANCED;
665       result.level = 4;
666       break;
667 
668    default:
669       assert(0);
670    }
671 
672    result.sps_info_flags |= pic->postprocflag << 7;
673    result.sps_info_flags |= pic->pulldown << 6;
674    result.sps_info_flags |= pic->interlace << 5;
675    result.sps_info_flags |= pic->tfcntrflag << 4;
676    result.sps_info_flags |= pic->finterpflag << 3;
677    result.sps_info_flags |= pic->psf << 1;
678 
679    result.pps_info_flags |= pic->range_mapy_flag << 31;
680    result.pps_info_flags |= pic->range_mapy << 28;
681    result.pps_info_flags |= pic->range_mapuv_flag << 27;
682    result.pps_info_flags |= pic->range_mapuv << 24;
683    result.pps_info_flags |= pic->multires << 21;
684    result.pps_info_flags |= pic->maxbframes << 16;
685    result.pps_info_flags |= pic->overlap << 11;
686    result.pps_info_flags |= pic->quantizer << 9;
687    result.pps_info_flags |= pic->panscan_flag << 7;
688    result.pps_info_flags |= pic->refdist_flag << 6;
689    result.pps_info_flags |= pic->vstransform << 0;
690 
691    if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
692       result.pps_info_flags |= pic->syncmarker << 20;
693       result.pps_info_flags |= pic->rangered << 19;
694       result.pps_info_flags |= pic->loopfilter << 5;
695       result.pps_info_flags |= pic->fastuvmc << 4;
696       result.pps_info_flags |= pic->extended_mv << 3;
697       result.pps_info_flags |= pic->extended_dmv << 8;
698       result.pps_info_flags |= pic->dquant << 1;
699    }
700 
701    result.chroma_format = 1;
702 
703    return result;
704 }
705 
get_ref_pic_idx(struct radeon_decoder * dec,struct pipe_video_buffer * ref)706 static uint32_t get_ref_pic_idx(struct radeon_decoder *dec, struct pipe_video_buffer *ref)
707 {
708    uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
709    uint32_t max = MAX2(dec->frame_number, 1) - 1;
710    uintptr_t frame;
711 
712    /* seems to be the most sane fallback */
713    if (!ref)
714       return max;
715 
716    /* get the frame number from the associated data */
717    frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
718 
719    /* limit the frame number to a valid range */
720    return MAX2(MIN2(frame, max), min);
721 }
722 
get_mpeg2_msg(struct radeon_decoder * dec,struct pipe_mpeg12_picture_desc * pic)723 static rvcn_dec_message_mpeg2_vld_t get_mpeg2_msg(struct radeon_decoder *dec,
724                                                   struct pipe_mpeg12_picture_desc *pic)
725 {
726    const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
727    rvcn_dec_message_mpeg2_vld_t result;
728    unsigned i;
729 
730    memset(&result, 0, sizeof(result));
731    result.decoded_pic_idx = dec->frame_number;
732 
733    result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
734    result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
735 
736    if (pic->intra_matrix) {
737       result.load_intra_quantiser_matrix = 1;
738       for (i = 0; i < 64; ++i) {
739          result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
740       }
741    }
742    if (pic->non_intra_matrix) {
743       result.load_nonintra_quantiser_matrix = 1;
744       for (i = 0; i < 64; ++i) {
745          result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
746       }
747    }
748 
749    result.profile_and_level_indication = 0;
750    result.chroma_format = 0x1;
751 
752    result.picture_coding_type = pic->picture_coding_type;
753    result.f_code[0][0] = pic->f_code[0][0] + 1;
754    result.f_code[0][1] = pic->f_code[0][1] + 1;
755    result.f_code[1][0] = pic->f_code[1][0] + 1;
756    result.f_code[1][1] = pic->f_code[1][1] + 1;
757    result.intra_dc_precision = pic->intra_dc_precision;
758    result.pic_structure = pic->picture_structure;
759    result.top_field_first = pic->top_field_first;
760    result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
761    result.concealment_motion_vectors = pic->concealment_motion_vectors;
762    result.q_scale_type = pic->q_scale_type;
763    result.intra_vlc_format = pic->intra_vlc_format;
764    result.alternate_scan = pic->alternate_scan;
765 
766    return result;
767 }
768 
get_mpeg4_msg(struct radeon_decoder * dec,struct pipe_mpeg4_picture_desc * pic)769 static rvcn_dec_message_mpeg4_asp_vld_t get_mpeg4_msg(struct radeon_decoder *dec,
770                                                       struct pipe_mpeg4_picture_desc *pic)
771 {
772    rvcn_dec_message_mpeg4_asp_vld_t result;
773    unsigned i;
774 
775    memset(&result, 0, sizeof(result));
776    result.decoded_pic_idx = dec->frame_number;
777 
778    result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
779    result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
780 
781    result.variant_type = 0;
782    result.profile_and_level_indication = 0xF0;
783 
784    result.video_object_layer_verid = 0x5;
785    result.video_object_layer_shape = 0x0;
786 
787    result.video_object_layer_width = dec->base.width;
788    result.video_object_layer_height = dec->base.height;
789 
790    result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
791 
792    result.short_video_header = pic->short_video_header;
793    result.interlaced = pic->interlaced;
794    result.load_intra_quant_mat = 1;
795    result.load_nonintra_quant_mat = 1;
796    result.quarter_sample = pic->quarter_sample;
797    result.complexity_estimation_disable = 1;
798    result.resync_marker_disable = pic->resync_marker_disable;
799    result.newpred_enable = 0;
800    result.reduced_resolution_vop_enable = 0;
801 
802    result.quant_type = pic->quant_type;
803 
804    for (i = 0; i < 64; ++i) {
805       result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
806       result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
807    }
808 
809    return result;
810 }
811 
rvcn_dec_message_create(struct radeon_decoder * dec)812 static void rvcn_dec_message_create(struct radeon_decoder *dec)
813 {
814    rvcn_dec_message_header_t *header = dec->msg;
815    rvcn_dec_message_create_t *create = dec->msg + sizeof(rvcn_dec_message_header_t);
816    unsigned sizes = sizeof(rvcn_dec_message_header_t) + sizeof(rvcn_dec_message_create_t);
817 
818    memset(dec->msg, 0, sizes);
819    header->header_size = sizeof(rvcn_dec_message_header_t);
820    header->total_size = sizes;
821    header->num_buffers = 1;
822    header->msg_type = RDECODE_MSG_CREATE;
823    header->stream_handle = dec->stream_handle;
824    header->status_report_feedback_number = 0;
825 
826    header->index[0].message_id = RDECODE_MESSAGE_CREATE;
827    header->index[0].offset = sizeof(rvcn_dec_message_header_t);
828    header->index[0].size = sizeof(rvcn_dec_message_create_t);
829    header->index[0].filled = 0;
830 
831    create->stream_type = dec->stream_type;
832    create->session_flags = 0;
833    create->width_in_samples = dec->base.width;
834    create->height_in_samples = dec->base.height;
835 }
836 
rvcn_dec_message_decode(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)837 static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
838                                                  struct pipe_video_buffer *target,
839                                                  struct pipe_picture_desc *picture)
840 {
841    DECRYPT_PARAMETERS *decrypt = (DECRYPT_PARAMETERS *)picture->decrypt_key;
842    bool encrypted = (DECRYPT_PARAMETERS *)picture->protected_playback;
843    struct si_texture *luma = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
844    struct si_texture *chroma =
845       (struct si_texture *)((struct vl_video_buffer *)target)->resources[1];
846    ASSERTED struct si_screen *sscreen = (struct si_screen *)dec->screen;
847    rvcn_dec_message_header_t *header;
848    rvcn_dec_message_index_t *index_drm;
849    rvcn_dec_message_index_t *index;
850    rvcn_dec_message_decode_t *decode;
851    unsigned sizes = 0, offset_decode, offset_codec;
852    unsigned int offset_drm;
853    void *codec;
854    rvcn_dec_message_drm_t *drm = NULL;
855 
856    header = dec->msg;
857    sizes += sizeof(rvcn_dec_message_header_t);
858    if (encrypted) {
859       index_drm = (void*)header + sizeof(rvcn_dec_message_header_t);
860       sizes += sizeof(rvcn_dec_message_index_t);
861       index = (void*)index_drm + sizeof(rvcn_dec_message_index_t);
862       sizes += sizeof(rvcn_dec_message_index_t);
863    } else {
864       index = (void*)header + sizeof(rvcn_dec_message_header_t);
865       sizes += sizeof(rvcn_dec_message_index_t);
866    }
867    offset_decode = sizes;
868    decode = (void *)index + sizeof(rvcn_dec_message_index_t);
869    sizes += sizeof(rvcn_dec_message_decode_t);
870    if (encrypted) {
871       offset_drm = sizes;
872       drm = (void*)decode + sizeof(rvcn_dec_message_decode_t);
873       sizes += sizeof(rvcn_dec_message_drm_t);
874       codec = (void*)drm + sizeof(rvcn_dec_message_drm_t);
875    } else
876       codec = (void*)decode + sizeof(rvcn_dec_message_decode_t);
877    offset_codec = sizes;
878 
879    memset(dec->msg, 0, sizes);
880    header->header_size = sizeof(rvcn_dec_message_header_t);
881    header->total_size = sizes;
882    if (encrypted)
883       header->num_buffers = 3;
884    else
885       header->num_buffers = 2;
886    header->msg_type = RDECODE_MSG_DECODE;
887    header->stream_handle = dec->stream_handle;
888    header->status_report_feedback_number = dec->frame_number;
889 
890    header->index[0].message_id = RDECODE_MESSAGE_DECODE;
891    header->index[0].offset = offset_decode;
892    header->index[0].size = sizeof(rvcn_dec_message_decode_t);
893    header->index[0].filled = 0;
894    if (encrypted) {
895       index_drm->message_id = RDECODE_MESSAGE_DRM;
896       index_drm->offset = offset_drm;
897       index_drm->size = sizeof(rvcn_dec_message_drm_t);
898       index_drm->filled = 0;
899    }
900 
901    index->offset = offset_codec;
902    index->size = sizeof(rvcn_dec_message_avc_t);
903    index->filled = 0;
904 
905    decode->stream_type = dec->stream_type;
906    decode->decode_flags = 0;
907    decode->width_in_samples = dec->base.width;
908    decode->height_in_samples = dec->base.height;
909 
910    decode->bsd_size = align(dec->bs_size, 128);
911 
912    if (!dec->dpb.res) {
913       unsigned dpb_size = calc_dpb_size(dec);
914       bool r;
915       if (dpb_size) {
916          if (encrypted) {
917             r = si_vid_create_tmz_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT);
918          } else {
919             r = si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT);
920          }
921          assert(encrypted == (bool)(dec->dpb.res->flags & RADEON_FLAG_ENCRYPTED));
922          if (!r) {
923             RVID_ERR("Can't allocated dpb.\n");
924             return NULL;
925          }
926          si_vid_clear_buffer(dec->base.context, &dec->dpb);
927       }
928    }
929 
930    if (!dec->ctx.res) {
931       enum pipe_video_format fmt = u_reduce_video_profile(picture->profile);
932       if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
933          unsigned ctx_size = calc_ctx_size_h264_perf(dec);
934          bool r;
935          if (encrypted) {
936             r = si_vid_create_tmz_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT);
937          } else {
938             r = si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT);
939          }
940          assert(encrypted == (bool)(dec->ctx.res->flags & RADEON_FLAG_ENCRYPTED));
941 
942          if (!r) {
943             RVID_ERR("Can't allocated context buffer.\n");
944             return NULL;
945          }
946          si_vid_clear_buffer(dec->base.context, &dec->ctx);
947       } else if (fmt == PIPE_VIDEO_FORMAT_VP9) {
948          unsigned ctx_size;
949          uint8_t *ptr;
950          bool r;
951 
952          /* default probability + probability data */
953          ctx_size = 2304 * 5;
954 
955          if (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR) {
956             /* SRE collocated context data */
957             ctx_size += 32 * 2 * 128 * 68;
958             /* SMP collocated context data */
959             ctx_size += 9 * 64 * 2 * 128 * 68;
960             /* SDB left tile pixel */
961             ctx_size += 8 * 2 * 2 * 8192;
962          } else {
963             ctx_size += 32 * 2 * 64 * 64;
964             ctx_size += 9 * 64 * 2 * 64 * 64;
965             ctx_size += 8 * 2 * 4096;
966          }
967 
968          if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
969             ctx_size += 8 * 2 * 4096;
970 
971          if (encrypted) {
972             r = si_vid_create_tmz_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT);
973          } else {
974             r = si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT);
975          }
976          if (!r) {
977             RVID_ERR("Can't allocated context buffer.\n");
978             return NULL;
979          }
980          si_vid_clear_buffer(dec->base.context, &dec->ctx);
981 
982          /* ctx needs probs table */
983          ptr = dec->ws->buffer_map(dec->ctx.res->buf, dec->cs,
984                                    PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
985          fill_probs_table(ptr);
986          dec->ws->buffer_unmap(dec->ctx.res->buf);
987          dec->bs_ptr = NULL;
988       } else if (fmt == PIPE_VIDEO_FORMAT_HEVC) {
989          unsigned ctx_size;
990          bool r;
991          if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
992             ctx_size = calc_ctx_size_h265_main10(dec, (struct pipe_h265_picture_desc *)picture);
993          else
994             ctx_size = calc_ctx_size_h265_main(dec);
995 
996          if (encrypted) {
997             r = si_vid_create_tmz_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT);
998          } else {
999             r = si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT);
1000          }
1001          if (!r) {
1002             RVID_ERR("Can't allocated context buffer.\n");
1003             return NULL;
1004          }
1005          si_vid_clear_buffer(dec->base.context, &dec->ctx);
1006       }
1007    }
1008    if (encrypted != dec->ws->cs_is_secure(dec->cs)) {
1009       dec->ws->cs_flush(dec->cs, RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION, NULL);
1010    }
1011 
1012    decode->dpb_size = dec->dpb.res->buf->size;
1013    decode->dt_size = si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
1014                      si_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
1015 
1016    decode->sct_size = 0;
1017    decode->sc_coeff_size = 0;
1018 
1019    decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
1020    decode->db_pitch = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR &&
1021                        dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9)
1022                          ? align(dec->base.width, 64)
1023                          : align(dec->base.width, 32);
1024    if (((struct si_screen*)dec->screen)->info.family >= CHIP_SIENNA_CICHLID &&
1025        dec->stream_type == RDECODE_CODEC_VP9)
1026       decode->db_aligned_height = align(dec->base.height, 64);
1027 
1028    decode->db_surf_tile_config = 0;
1029 
1030    decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
1031    decode->dt_uv_pitch = decode->dt_pitch / 2;
1032 
1033    decode->dt_tiling_mode = 0;
1034    decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR;
1035    decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR;
1036    decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced;
1037    decode->dt_surf_tile_config = 0;
1038    decode->dt_uv_surf_tile_config = 0;
1039 
1040    decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
1041    decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
1042    if (decode->dt_field_mode) {
1043       decode->dt_luma_bottom_offset =
1044          luma->surface.u.gfx9.surf_offset + luma->surface.u.gfx9.surf_slice_size;
1045       decode->dt_chroma_bottom_offset =
1046          chroma->surface.u.gfx9.surf_offset + chroma->surface.u.gfx9.surf_slice_size;
1047    } else {
1048       decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
1049       decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
1050    }
1051 
1052    if (encrypted) {
1053       assert(sscreen->info.has_tmz_support);
1054       set_drm_keys(drm, decrypt);
1055    }
1056 
1057    switch (u_reduce_video_profile(picture->profile)) {
1058    case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
1059       rvcn_dec_message_avc_t avc = get_h264_msg(dec, (struct pipe_h264_picture_desc *)picture);
1060       memcpy(codec, (void *)&avc, sizeof(rvcn_dec_message_avc_t));
1061       index->message_id = RDECODE_MESSAGE_AVC;
1062       break;
1063    }
1064    case PIPE_VIDEO_FORMAT_HEVC: {
1065       rvcn_dec_message_hevc_t hevc =
1066          get_h265_msg(dec, target, (struct pipe_h265_picture_desc *)picture);
1067 
1068       memcpy(codec, (void *)&hevc, sizeof(rvcn_dec_message_hevc_t));
1069       index->message_id = RDECODE_MESSAGE_HEVC;
1070       break;
1071    }
1072    case PIPE_VIDEO_FORMAT_VC1: {
1073       rvcn_dec_message_vc1_t vc1 = get_vc1_msg((struct pipe_vc1_picture_desc *)picture);
1074 
1075       memcpy(codec, (void *)&vc1, sizeof(rvcn_dec_message_vc1_t));
1076       if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
1077           (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
1078          decode->width_in_samples = align(decode->width_in_samples, 16) / 16;
1079          decode->height_in_samples = align(decode->height_in_samples, 16) / 16;
1080       }
1081       index->message_id = RDECODE_MESSAGE_VC1;
1082       break;
1083    }
1084    case PIPE_VIDEO_FORMAT_MPEG12: {
1085       rvcn_dec_message_mpeg2_vld_t mpeg2 =
1086          get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc *)picture);
1087 
1088       memcpy(codec, (void *)&mpeg2, sizeof(rvcn_dec_message_mpeg2_vld_t));
1089       index->message_id = RDECODE_MESSAGE_MPEG2_VLD;
1090       break;
1091    }
1092    case PIPE_VIDEO_FORMAT_MPEG4: {
1093       rvcn_dec_message_mpeg4_asp_vld_t mpeg4 =
1094          get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc *)picture);
1095 
1096       memcpy(codec, (void *)&mpeg4, sizeof(rvcn_dec_message_mpeg4_asp_vld_t));
1097       index->message_id = RDECODE_MESSAGE_MPEG4_ASP_VLD;
1098       break;
1099    }
1100    case PIPE_VIDEO_FORMAT_VP9: {
1101       rvcn_dec_message_vp9_t vp9 =
1102          get_vp9_msg(dec, target, (struct pipe_vp9_picture_desc *)picture);
1103 
1104       memcpy(codec, (void *)&vp9, sizeof(rvcn_dec_message_vp9_t));
1105       index->message_id = RDECODE_MESSAGE_VP9;
1106       break;
1107    }
1108    default:
1109       assert(0);
1110       return NULL;
1111    }
1112 
1113    if (dec->ctx.res)
1114       decode->hw_ctxt_size = dec->ctx.res->buf->size;
1115 
1116    return luma->buffer.buf;
1117 }
1118 
rvcn_dec_message_destroy(struct radeon_decoder * dec)1119 static void rvcn_dec_message_destroy(struct radeon_decoder *dec)
1120 {
1121    rvcn_dec_message_header_t *header = dec->msg;
1122 
1123    memset(dec->msg, 0, sizeof(rvcn_dec_message_header_t));
1124    header->header_size = sizeof(rvcn_dec_message_header_t);
1125    header->total_size = sizeof(rvcn_dec_message_header_t) - sizeof(rvcn_dec_message_index_t);
1126    header->num_buffers = 0;
1127    header->msg_type = RDECODE_MSG_DESTROY;
1128    header->stream_handle = dec->stream_handle;
1129    header->status_report_feedback_number = 0;
1130 }
1131 
rvcn_dec_message_feedback(struct radeon_decoder * dec)1132 static void rvcn_dec_message_feedback(struct radeon_decoder *dec)
1133 {
1134    rvcn_dec_feedback_header_t *header = (void *)dec->fb;
1135 
1136    header->header_size = sizeof(rvcn_dec_feedback_header_t);
1137    header->total_size = sizeof(rvcn_dec_feedback_header_t);
1138    header->num_buffers = 0;
1139 }
1140 
1141 /* flush IB to the hardware */
flush(struct radeon_decoder * dec,unsigned flags)1142 static int flush(struct radeon_decoder *dec, unsigned flags)
1143 {
1144    return dec->ws->cs_flush(dec->cs, flags, NULL);
1145 }
1146 
1147 /* add a new set register command to the IB */
set_reg(struct radeon_decoder * dec,unsigned reg,uint32_t val)1148 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
1149 {
1150    radeon_emit(dec->cs, RDECODE_PKT0(reg >> 2, 0));
1151    radeon_emit(dec->cs, val);
1152 }
1153 
1154 /* send a command to the VCPU through the GPCOM registers */
send_cmd(struct radeon_decoder * dec,unsigned cmd,struct pb_buffer * buf,uint32_t off,enum radeon_bo_usage usage,enum radeon_bo_domain domain)1155 static void send_cmd(struct radeon_decoder *dec, unsigned cmd, struct pb_buffer *buf, uint32_t off,
1156                      enum radeon_bo_usage usage, enum radeon_bo_domain domain)
1157 {
1158    uint64_t addr;
1159 
1160    dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
1161    addr = dec->ws->buffer_get_virtual_address(buf);
1162    addr = addr + off;
1163 
1164    set_reg(dec, dec->reg.data0, addr);
1165    set_reg(dec, dec->reg.data1, addr >> 32);
1166    set_reg(dec, dec->reg.cmd, cmd << 1);
1167 }
1168 
1169 /* do the codec needs an IT buffer ?*/
have_it(struct radeon_decoder * dec)1170 static bool have_it(struct radeon_decoder *dec)
1171 {
1172    return dec->stream_type == RDECODE_CODEC_H264_PERF || dec->stream_type == RDECODE_CODEC_H265;
1173 }
1174 
1175 /* do the codec needs an probs buffer? */
have_probs(struct radeon_decoder * dec)1176 static bool have_probs(struct radeon_decoder *dec)
1177 {
1178    return dec->stream_type == RDECODE_CODEC_VP9;
1179 }
1180 
1181 /* map the next available message/feedback/itscaling buffer */
map_msg_fb_it_probs_buf(struct radeon_decoder * dec)1182 static void map_msg_fb_it_probs_buf(struct radeon_decoder *dec)
1183 {
1184    struct rvid_buffer *buf;
1185    uint8_t *ptr;
1186 
1187    /* grab the current message/feedback buffer */
1188    buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1189 
1190    /* and map it for CPU access */
1191    ptr =
1192       dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1193 
1194    /* calc buffer offsets */
1195    dec->msg = ptr;
1196 
1197    dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
1198    if (have_it(dec))
1199       dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1200    else if (have_probs(dec))
1201       dec->probs = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1202 }
1203 
1204 /* unmap and send a message command to the VCPU */
send_msg_buf(struct radeon_decoder * dec)1205 static void send_msg_buf(struct radeon_decoder *dec)
1206 {
1207    struct rvid_buffer *buf;
1208 
1209    /* ignore the request if message/feedback buffer isn't mapped */
1210    if (!dec->msg || !dec->fb)
1211       return;
1212 
1213    /* grab the current message buffer */
1214    buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1215 
1216    /* unmap the buffer */
1217    dec->ws->buffer_unmap(buf->res->buf);
1218    dec->bs_ptr = NULL;
1219    dec->msg = NULL;
1220    dec->fb = NULL;
1221    dec->it = NULL;
1222    dec->probs = NULL;
1223 
1224    if (dec->sessionctx.res)
1225       send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER, dec->sessionctx.res->buf, 0,
1226                RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1227 
1228    /* and send it to the hardware */
1229    send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1230 }
1231 
1232 /* cycle to the next set of buffers */
next_buffer(struct radeon_decoder * dec)1233 static void next_buffer(struct radeon_decoder *dec)
1234 {
1235    ++dec->cur_buffer;
1236    dec->cur_buffer %= NUM_BUFFERS;
1237 }
1238 
calc_ctx_size_h264_perf(struct radeon_decoder * dec)1239 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
1240 {
1241    unsigned width_in_mb, height_in_mb, ctx_size;
1242    unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1243    unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1244 
1245    unsigned max_references = dec->base.max_references + 1;
1246 
1247    // picture width & height in 16 pixel units
1248    width_in_mb = width / VL_MACROBLOCK_WIDTH;
1249    height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1250 
1251    unsigned fs_in_mb = width_in_mb * height_in_mb;
1252    unsigned num_dpb_buffer;
1253    switch (dec->base.level) {
1254    case 30:
1255       num_dpb_buffer = 8100 / fs_in_mb;
1256       break;
1257    case 31:
1258       num_dpb_buffer = 18000 / fs_in_mb;
1259       break;
1260    case 32:
1261       num_dpb_buffer = 20480 / fs_in_mb;
1262       break;
1263    case 41:
1264       num_dpb_buffer = 32768 / fs_in_mb;
1265       break;
1266    case 42:
1267       num_dpb_buffer = 34816 / fs_in_mb;
1268       break;
1269    case 50:
1270       num_dpb_buffer = 110400 / fs_in_mb;
1271       break;
1272    case 51:
1273       num_dpb_buffer = 184320 / fs_in_mb;
1274       break;
1275    default:
1276       num_dpb_buffer = 184320 / fs_in_mb;
1277       break;
1278    }
1279    num_dpb_buffer++;
1280    max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1281    ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
1282 
1283    return ctx_size;
1284 }
1285 
1286 /* calculate size of reference picture buffer */
calc_dpb_size(struct radeon_decoder * dec)1287 static unsigned calc_dpb_size(struct radeon_decoder *dec)
1288 {
1289    unsigned width_in_mb, height_in_mb, image_size, dpb_size;
1290 
1291    // always align them to MB size for dpb calculation
1292    unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1293    unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1294 
1295    // always one more for currently decoded picture
1296    unsigned max_references = dec->base.max_references + 1;
1297 
1298    // aligned size of a single frame
1299    image_size = align(width, 32) * height;
1300    image_size += image_size / 2;
1301    image_size = align(image_size, 1024);
1302 
1303    // picture width & height in 16 pixel units
1304    width_in_mb = width / VL_MACROBLOCK_WIDTH;
1305    height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1306 
1307    switch (u_reduce_video_profile(dec->base.profile)) {
1308    case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
1309       unsigned fs_in_mb = width_in_mb * height_in_mb;
1310       unsigned num_dpb_buffer;
1311 
1312       switch (dec->base.level) {
1313       case 30:
1314          num_dpb_buffer = 8100 / fs_in_mb;
1315          break;
1316       case 31:
1317          num_dpb_buffer = 18000 / fs_in_mb;
1318          break;
1319       case 32:
1320          num_dpb_buffer = 20480 / fs_in_mb;
1321          break;
1322       case 41:
1323          num_dpb_buffer = 32768 / fs_in_mb;
1324          break;
1325       case 42:
1326          num_dpb_buffer = 34816 / fs_in_mb;
1327          break;
1328       case 50:
1329          num_dpb_buffer = 110400 / fs_in_mb;
1330          break;
1331       case 51:
1332          num_dpb_buffer = 184320 / fs_in_mb;
1333          break;
1334       default:
1335          num_dpb_buffer = 184320 / fs_in_mb;
1336          break;
1337       }
1338       num_dpb_buffer++;
1339       max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1340       dpb_size = image_size * max_references;
1341       break;
1342    }
1343 
1344    case PIPE_VIDEO_FORMAT_HEVC:
1345       if (dec->base.width * dec->base.height >= 4096 * 2000)
1346          max_references = MAX2(max_references, 8);
1347       else
1348          max_references = MAX2(max_references, 17);
1349 
1350       width = align(width, 16);
1351       height = align(height, 16);
1352       if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1353          dpb_size = align((align(width, 32) * height * 9) / 4, 256) * max_references;
1354       else
1355          dpb_size = align((align(width, 32) * height * 3) / 2, 256) * max_references;
1356       break;
1357 
1358    case PIPE_VIDEO_FORMAT_VC1:
1359       // the firmware seems to allways assume a minimum of ref frames
1360       max_references = MAX2(NUM_VC1_REFS, max_references);
1361 
1362       // reference picture buffer
1363       dpb_size = image_size * max_references;
1364 
1365       // CONTEXT_BUFFER
1366       dpb_size += width_in_mb * height_in_mb * 128;
1367 
1368       // IT surface buffer
1369       dpb_size += width_in_mb * 64;
1370 
1371       // DB surface buffer
1372       dpb_size += width_in_mb * 128;
1373 
1374       // BP
1375       dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
1376       break;
1377 
1378    case PIPE_VIDEO_FORMAT_MPEG12:
1379       // reference picture buffer, must be big enough for all frames
1380       dpb_size = image_size * NUM_MPEG2_REFS;
1381       break;
1382 
1383    case PIPE_VIDEO_FORMAT_MPEG4:
1384       // reference picture buffer
1385       dpb_size = image_size * max_references;
1386 
1387       // CM
1388       dpb_size += width_in_mb * height_in_mb * 64;
1389 
1390       // IT surface buffer
1391       dpb_size += align(width_in_mb * height_in_mb * 32, 64);
1392 
1393       dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
1394       break;
1395 
1396    case PIPE_VIDEO_FORMAT_VP9:
1397       max_references = MAX2(max_references, 9);
1398 
1399       dpb_size = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR)
1400                     ? (8192 * 4320 * 3 / 2) * max_references
1401                     : (4096 * 3000 * 3 / 2) * max_references;
1402 
1403       if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1404          dpb_size = dpb_size * 3 / 2;
1405       break;
1406 
1407    case PIPE_VIDEO_FORMAT_JPEG:
1408       dpb_size = 0;
1409       break;
1410 
1411    default:
1412       // something is missing here
1413       assert(0);
1414 
1415       // at least use a sane default value
1416       dpb_size = 32 * 1024 * 1024;
1417       break;
1418    }
1419    return dpb_size;
1420 }
1421 
1422 /**
1423  * destroy this video decoder
1424  */
radeon_dec_destroy(struct pipe_video_codec * decoder)1425 static void radeon_dec_destroy(struct pipe_video_codec *decoder)
1426 {
1427    struct radeon_decoder *dec = (struct radeon_decoder *)decoder;
1428    unsigned i;
1429 
1430    assert(decoder);
1431 
1432    map_msg_fb_it_probs_buf(dec);
1433    rvcn_dec_message_destroy(dec);
1434    send_msg_buf(dec);
1435 
1436    flush(dec, 0);
1437 
1438    dec->ws->cs_destroy(dec->cs);
1439 
1440    for (i = 0; i < NUM_BUFFERS; ++i) {
1441       si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1442       si_vid_destroy_buffer(&dec->bs_buffers[i]);
1443    }
1444 
1445    si_vid_destroy_buffer(&dec->dpb);
1446    si_vid_destroy_buffer(&dec->ctx);
1447    si_vid_destroy_buffer(&dec->sessionctx);
1448 
1449    FREE(dec);
1450 }
1451 
1452 /**
1453  * start decoding of a new frame
1454  */
radeon_dec_begin_frame(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)1455 static void radeon_dec_begin_frame(struct pipe_video_codec *decoder,
1456                                    struct pipe_video_buffer *target,
1457                                    struct pipe_picture_desc *picture)
1458 {
1459    struct radeon_decoder *dec = (struct radeon_decoder *)decoder;
1460    uintptr_t frame;
1461 
1462    assert(decoder);
1463 
1464    frame = ++dec->frame_number;
1465    if (dec->stream_type != RDECODE_CODEC_VP9)
1466       vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
1467                                           &radeon_dec_destroy_associated_data);
1468 
1469    dec->bs_size = 0;
1470    dec->bs_ptr = dec->ws->buffer_map(dec->bs_buffers[dec->cur_buffer].res->buf, dec->cs,
1471                                      PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1472 }
1473 
1474 /**
1475  * decode a macroblock
1476  */
radeon_dec_decode_macroblock(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture,const struct pipe_macroblock * macroblocks,unsigned num_macroblocks)1477 static void radeon_dec_decode_macroblock(struct pipe_video_codec *decoder,
1478                                          struct pipe_video_buffer *target,
1479                                          struct pipe_picture_desc *picture,
1480                                          const struct pipe_macroblock *macroblocks,
1481                                          unsigned num_macroblocks)
1482 {
1483    /* not supported (yet) */
1484    assert(0);
1485 }
1486 
1487 /**
1488  * decode a bitstream
1489  */
radeon_dec_decode_bitstream(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture,unsigned num_buffers,const void * const * buffers,const unsigned * sizes)1490 static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
1491                                         struct pipe_video_buffer *target,
1492                                         struct pipe_picture_desc *picture, unsigned num_buffers,
1493                                         const void *const *buffers, const unsigned *sizes)
1494 {
1495    struct radeon_decoder *dec = (struct radeon_decoder *)decoder;
1496    unsigned i;
1497 
1498    assert(decoder);
1499 
1500    if (!dec->bs_ptr)
1501       return;
1502 
1503    for (i = 0; i < num_buffers; ++i) {
1504       struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1505       unsigned new_size = dec->bs_size + sizes[i];
1506 
1507       if (new_size > buf->res->buf->size) {
1508          dec->ws->buffer_unmap(buf->res->buf);
1509          dec->bs_ptr = NULL;
1510          if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
1511             RVID_ERR("Can't resize bitstream buffer!");
1512             return;
1513          }
1514 
1515          dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1516                                            PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1517          if (!dec->bs_ptr)
1518             return;
1519 
1520          dec->bs_ptr += dec->bs_size;
1521       }
1522 
1523       memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1524       dec->bs_size += sizes[i];
1525       dec->bs_ptr += sizes[i];
1526    }
1527 }
1528 
1529 /**
1530  * send cmd for vcn dec
1531  */
send_cmd_dec(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)1532 void send_cmd_dec(struct radeon_decoder *dec, struct pipe_video_buffer *target,
1533                   struct pipe_picture_desc *picture)
1534 {
1535    struct pb_buffer *dt;
1536    struct rvid_buffer *msg_fb_it_probs_buf, *bs_buf;
1537 
1538    msg_fb_it_probs_buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1539    bs_buf = &dec->bs_buffers[dec->cur_buffer];
1540 
1541    memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
1542    dec->ws->buffer_unmap(bs_buf->res->buf);
1543    dec->bs_ptr = NULL;
1544 
1545    map_msg_fb_it_probs_buf(dec);
1546    dt = rvcn_dec_message_decode(dec, target, picture);
1547    rvcn_dec_message_feedback(dec);
1548    send_msg_buf(dec);
1549 
1550    send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0, RADEON_USAGE_READWRITE,
1551             RADEON_DOMAIN_VRAM);
1552    if (dec->ctx.res)
1553       send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0, RADEON_USAGE_READWRITE,
1554                RADEON_DOMAIN_VRAM);
1555    send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf, 0, RADEON_USAGE_READ,
1556             RADEON_DOMAIN_GTT);
1557    send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1558    send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_probs_buf->res->buf, FB_BUFFER_OFFSET,
1559             RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1560    if (have_it(dec))
1561       send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, msg_fb_it_probs_buf->res->buf,
1562                FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1563    else if (have_probs(dec))
1564       send_cmd(dec, RDECODE_CMD_PROB_TBL_BUFFER, msg_fb_it_probs_buf->res->buf,
1565                FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1566    set_reg(dec, dec->reg.cntl, 1);
1567 }
1568 
1569 /**
1570  * end decoding of the current frame
1571  */
radeon_dec_end_frame(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)1572 static void radeon_dec_end_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
1573                                  struct pipe_picture_desc *picture)
1574 {
1575    struct radeon_decoder *dec = (struct radeon_decoder *)decoder;
1576 
1577    assert(decoder);
1578 
1579    if (!dec->bs_ptr)
1580       return;
1581 
1582    dec->send_cmd(dec, target, picture);
1583    flush(dec, PIPE_FLUSH_ASYNC);
1584    next_buffer(dec);
1585 }
1586 
1587 /**
1588  * flush any outstanding command buffers to the hardware
1589  */
radeon_dec_flush(struct pipe_video_codec * decoder)1590 static void radeon_dec_flush(struct pipe_video_codec *decoder)
1591 {
1592 }
1593 
1594 /**
1595  * create and HW decoder
1596  */
radeon_create_decoder(struct pipe_context * context,const struct pipe_video_codec * templ)1597 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
1598                                                const struct pipe_video_codec *templ)
1599 {
1600    struct si_context *sctx = (struct si_context *)context;
1601    struct radeon_winsys *ws = sctx->ws;
1602    unsigned width = templ->width, height = templ->height;
1603    unsigned bs_buf_size, stream_type = 0, ring = RING_VCN_DEC;
1604    struct radeon_decoder *dec;
1605    int r, i;
1606 
1607    switch (u_reduce_video_profile(templ->profile)) {
1608    case PIPE_VIDEO_FORMAT_MPEG12:
1609       if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1610          return vl_create_mpeg12_decoder(context, templ);
1611       stream_type = RDECODE_CODEC_MPEG2_VLD;
1612       break;
1613    case PIPE_VIDEO_FORMAT_MPEG4:
1614       width = align(width, VL_MACROBLOCK_WIDTH);
1615       height = align(height, VL_MACROBLOCK_HEIGHT);
1616       stream_type = RDECODE_CODEC_MPEG4;
1617       break;
1618    case PIPE_VIDEO_FORMAT_VC1:
1619       stream_type = RDECODE_CODEC_VC1;
1620       break;
1621    case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1622       width = align(width, VL_MACROBLOCK_WIDTH);
1623       height = align(height, VL_MACROBLOCK_HEIGHT);
1624       stream_type = RDECODE_CODEC_H264_PERF;
1625       break;
1626    case PIPE_VIDEO_FORMAT_HEVC:
1627       stream_type = RDECODE_CODEC_H265;
1628       break;
1629    case PIPE_VIDEO_FORMAT_VP9:
1630       stream_type = RDECODE_CODEC_VP9;
1631       break;
1632    case PIPE_VIDEO_FORMAT_JPEG:
1633       stream_type = RDECODE_CODEC_JPEG;
1634       ring = RING_VCN_JPEG;
1635       break;
1636    default:
1637       assert(0);
1638       break;
1639    }
1640 
1641    dec = CALLOC_STRUCT(radeon_decoder);
1642 
1643    if (!dec)
1644       return NULL;
1645 
1646    dec->base = *templ;
1647    dec->base.context = context;
1648    dec->base.width = width;
1649    dec->base.height = height;
1650 
1651    dec->base.destroy = radeon_dec_destroy;
1652    dec->base.begin_frame = radeon_dec_begin_frame;
1653    dec->base.decode_macroblock = radeon_dec_decode_macroblock;
1654    dec->base.decode_bitstream = radeon_dec_decode_bitstream;
1655    dec->base.end_frame = radeon_dec_end_frame;
1656    dec->base.flush = radeon_dec_flush;
1657 
1658    dec->stream_type = stream_type;
1659    dec->stream_handle = si_vid_alloc_stream_handle();
1660    dec->screen = context->screen;
1661    dec->ws = ws;
1662    dec->cs = ws->cs_create(sctx->ctx, ring, NULL, NULL, false);
1663    if (!dec->cs) {
1664       RVID_ERR("Can't get command submission context.\n");
1665       goto error;
1666    }
1667 
1668    for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); i++)
1669       dec->render_pic_list[i] = NULL;
1670    bs_buf_size = width * height * (512 / (16 * 16));
1671    for (i = 0; i < NUM_BUFFERS; ++i) {
1672       unsigned msg_fb_it_probs_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1673       if (have_it(dec))
1674          msg_fb_it_probs_size += IT_SCALING_TABLE_SIZE;
1675       else if (have_probs(dec))
1676          msg_fb_it_probs_size += VP9_PROBS_TABLE_SIZE;
1677       /* use vram to improve performance, workaround an unknown bug */
1678       if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_probs_buffers[i], msg_fb_it_probs_size,
1679                                 PIPE_USAGE_DEFAULT)) {
1680          RVID_ERR("Can't allocated message buffers.\n");
1681          goto error;
1682       }
1683 
1684       if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i], bs_buf_size,
1685                                 PIPE_USAGE_STAGING)) {
1686          RVID_ERR("Can't allocated bitstream buffers.\n");
1687          goto error;
1688       }
1689 
1690       si_vid_clear_buffer(context, &dec->msg_fb_it_probs_buffers[i]);
1691       si_vid_clear_buffer(context, &dec->bs_buffers[i]);
1692 
1693       if (have_probs(dec)) {
1694          struct rvid_buffer *buf;
1695          void *ptr;
1696 
1697          buf = &dec->msg_fb_it_probs_buffers[i];
1698          ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1699                                    PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1700          ptr += FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1701          fill_probs_table(ptr);
1702          dec->ws->buffer_unmap(buf->res->buf);
1703          dec->bs_ptr = NULL;
1704       }
1705    }
1706 
1707    if (!si_vid_create_buffer(dec->screen, &dec->sessionctx, RDECODE_SESSION_CONTEXT_SIZE,
1708                              PIPE_USAGE_DEFAULT)) {
1709       RVID_ERR("Can't allocated session ctx.\n");
1710       goto error;
1711    }
1712    si_vid_clear_buffer(context, &dec->sessionctx);
1713 
1714    switch (sctx->family) {
1715    case CHIP_RAVEN:
1716    case CHIP_RAVEN2:
1717       dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
1718       dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
1719       dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
1720       dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
1721       dec->jpg.direct_reg = false;
1722       break;
1723    case CHIP_NAVI10:
1724    case CHIP_NAVI12:
1725    case CHIP_NAVI14:
1726    case CHIP_RENOIR:
1727       dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
1728       dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
1729       dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
1730       dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
1731       dec->jpg.direct_reg = true;
1732       break;
1733    case CHIP_ARCTURUS:
1734    case CHIP_SIENNA_CICHLID:
1735    case CHIP_NAVY_FLOUNDER:
1736    case CHIP_DIMGREY_CAVEFISH:
1737    case CHIP_VANGOGH:
1738       dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
1739       dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
1740       dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
1741       dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
1742       dec->jpg.direct_reg = true;
1743       break;
1744    default:
1745       RVID_ERR("VCN is not supported.\n");
1746       goto error;
1747    }
1748 
1749    map_msg_fb_it_probs_buf(dec);
1750    rvcn_dec_message_create(dec);
1751    send_msg_buf(dec);
1752    r = flush(dec, 0);
1753    if (r)
1754       goto error;
1755 
1756    next_buffer(dec);
1757 
1758    if (stream_type == RDECODE_CODEC_JPEG)
1759       dec->send_cmd = send_cmd_jpeg;
1760    else
1761       dec->send_cmd = send_cmd_dec;
1762 
1763    return &dec->base;
1764 
1765 error:
1766    if (dec->cs)
1767       dec->ws->cs_destroy(dec->cs);
1768 
1769    for (i = 0; i < NUM_BUFFERS; ++i) {
1770       si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1771       si_vid_destroy_buffer(&dec->bs_buffers[i]);
1772    }
1773 
1774    si_vid_destroy_buffer(&dec->dpb);
1775    si_vid_destroy_buffer(&dec->ctx);
1776    si_vid_destroy_buffer(&dec->sessionctx);
1777 
1778    FREE(dec);
1779 
1780    return NULL;
1781 }
1782