1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_build_pm4.h"
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "util/os_time.h"
30 #include "util/u_upload_mgr.h"
31
32 /* initialize */
si_need_gfx_cs_space(struct si_context * ctx,unsigned num_draws)33 void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws)
34 {
35 struct radeon_cmdbuf *cs = ctx->gfx_cs;
36
37 /* There is no need to flush the DMA IB here, because
38 * si_need_dma_space always flushes the GFX IB if there is
39 * a conflict, which means any unflushed DMA commands automatically
40 * precede the GFX IB (= they had no dependency on the GFX IB when
41 * they were submitted).
42 */
43
44 /* There are two memory usage counters in the winsys for all buffers
45 * that have been added (cs_add_buffer) and two counters in the pipe
46 * driver for those that haven't been added yet.
47 */
48 if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs, ctx->vram, ctx->gtt))) {
49 ctx->gtt = 0;
50 ctx->vram = 0;
51 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
52 return;
53 }
54 ctx->gtt = 0;
55 ctx->vram = 0;
56
57 unsigned need_dwords = si_get_minimum_num_gfx_cs_dwords(ctx, num_draws);
58 if (!ctx->ws->cs_check_space(cs, need_dwords, false))
59 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
60 }
61
si_unref_sdma_uploads(struct si_context * sctx)62 void si_unref_sdma_uploads(struct si_context *sctx)
63 {
64 for (unsigned i = 0; i < sctx->num_sdma_uploads; i++) {
65 si_resource_reference(&sctx->sdma_uploads[i].dst, NULL);
66 si_resource_reference(&sctx->sdma_uploads[i].src, NULL);
67 }
68 sctx->num_sdma_uploads = 0;
69 }
70
si_flush_gfx_cs(struct si_context * ctx,unsigned flags,struct pipe_fence_handle ** fence)71 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence)
72 {
73 struct radeon_cmdbuf *cs = ctx->gfx_cs;
74 struct radeon_winsys *ws = ctx->ws;
75 struct si_screen *sscreen = ctx->screen;
76 const unsigned wait_ps_cs = SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
77 unsigned wait_flags = 0;
78
79 if (ctx->gfx_flush_in_progress)
80 return;
81
82 /* The amdgpu kernel driver synchronizes execution for shared DMABUFs between
83 * processes on DRM >= 3.39.0, so we don't have to wait at the end of IBs to
84 * make sure everything is idle.
85 *
86 * The amdgpu winsys synchronizes execution for buffers shared by different
87 * contexts within the same process.
88 *
89 * Interop with AMDVLK, RADV, or OpenCL within the same process requires
90 * explicit fences or glFinish.
91 */
92 if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 39)
93 flags |= RADEON_FLUSH_START_NEXT_GFX_IB_NOW;
94
95 if (!sscreen->info.kernel_flushes_tc_l2_after_ib) {
96 wait_flags |= wait_ps_cs | SI_CONTEXT_INV_L2;
97 } else if (ctx->chip_class == GFX6) {
98 /* The kernel flushes L2 before shaders are finished. */
99 wait_flags |= wait_ps_cs;
100 } else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW) ||
101 ((flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION) &&
102 !ws->cs_is_secure(cs))) {
103 /* TODO: this workaround fixes subtitles rendering with mpv -vo=vaapi and
104 * tmz but shouldn't be necessary.
105 */
106 wait_flags |= wait_ps_cs;
107 }
108
109 /* Drop this flush if it's a no-op. */
110 if (!radeon_emitted(cs, ctx->initial_gfx_cs_size) &&
111 (!wait_flags || !ctx->gfx_last_ib_is_busy) &&
112 !(flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION))
113 return;
114
115 if (ctx->b.get_device_reset_status(&ctx->b) != PIPE_NO_RESET)
116 return;
117
118 if (sscreen->debug_flags & DBG(CHECK_VM))
119 flags &= ~PIPE_FLUSH_ASYNC;
120
121 ctx->gfx_flush_in_progress = true;
122
123 /* If the gallium frontend is flushing the GFX IB, si_flush_from_st is
124 * responsible for flushing the DMA IB and merging the fences from both.
125 * If the driver flushes the GFX IB internally, and it should never ask
126 * for a fence handle.
127 */
128 assert(!radeon_emitted(ctx->sdma_cs, 0) || fence == NULL);
129
130 /* Update the sdma_uploads list by flushing the uploader. */
131 u_upload_unmap(ctx->b.const_uploader);
132
133 /* Execute SDMA uploads. */
134 ctx->sdma_uploads_in_progress = true;
135 for (unsigned i = 0; i < ctx->num_sdma_uploads; i++) {
136 struct si_sdma_upload *up = &ctx->sdma_uploads[i];
137
138 assert(up->src_offset % 4 == 0 && up->dst_offset % 4 == 0 && up->size % 4 == 0);
139
140 si_sdma_copy_buffer(ctx, &up->dst->b.b, &up->src->b.b, up->dst_offset, up->src_offset,
141 up->size);
142 }
143 ctx->sdma_uploads_in_progress = false;
144 si_unref_sdma_uploads(ctx);
145
146 /* Flush SDMA (preamble IB). */
147 if (radeon_emitted(ctx->sdma_cs, 0))
148 si_flush_dma_cs(ctx, flags, NULL);
149
150 if (radeon_emitted(ctx->prim_discard_compute_cs, 0)) {
151 struct radeon_cmdbuf *compute_cs = ctx->prim_discard_compute_cs;
152 si_compute_signal_gfx(ctx);
153
154 /* Make sure compute shaders are idle before leaving the IB, so that
155 * the next IB doesn't overwrite GDS that might be in use. */
156 radeon_emit(compute_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
157 radeon_emit(compute_cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
158
159 /* Save the GDS prim restart counter if needed. */
160 if (ctx->preserve_prim_restart_gds_at_flush) {
161 si_cp_copy_data(ctx, compute_cs, COPY_DATA_DST_MEM, ctx->wait_mem_scratch, 4,
162 COPY_DATA_GDS, NULL, 4);
163 }
164 }
165
166 if (ctx->has_graphics) {
167 if (!list_is_empty(&ctx->active_queries))
168 si_suspend_queries(ctx);
169
170 ctx->streamout.suspended = false;
171 if (ctx->streamout.begin_emitted) {
172 si_emit_streamout_end(ctx);
173 ctx->streamout.suspended = true;
174
175 /* Since NGG streamout uses GDS, we need to make GDS
176 * idle when we leave the IB, otherwise another process
177 * might overwrite it while our shaders are busy.
178 */
179 if (sscreen->use_ngg_streamout)
180 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
181 }
182 }
183
184 /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
185 * because the kernel doesn't wait for it. */
186 if (ctx->chip_class >= GFX7)
187 si_cp_dma_wait_for_idle(ctx);
188
189 /* Wait for draw calls to finish if needed. */
190 if (wait_flags) {
191 ctx->flags |= wait_flags;
192 ctx->emit_cache_flush(ctx);
193 }
194 ctx->gfx_last_ib_is_busy = (wait_flags & wait_ps_cs) != wait_ps_cs;
195
196 if (ctx->current_saved_cs) {
197 si_trace_emit(ctx);
198
199 /* Save the IB for debug contexts. */
200 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
201 ctx->current_saved_cs->flushed = true;
202 ctx->current_saved_cs->time_flush = os_time_get_nano();
203
204 si_log_hw_flush(ctx);
205 }
206
207 if (si_compute_prim_discard_enabled(ctx)) {
208 /* The compute IB can start after the previous gfx IB starts. */
209 if (radeon_emitted(ctx->prim_discard_compute_cs, 0) && ctx->last_gfx_fence) {
210 ctx->ws->cs_add_fence_dependency(
211 ctx->gfx_cs, ctx->last_gfx_fence,
212 RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY | RADEON_DEPENDENCY_START_FENCE);
213 }
214
215 /* Remember the last execution barrier. It's in the IB.
216 * It will signal the start of the next compute IB.
217 */
218 if (flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW && ctx->last_pkt3_write_data) {
219 *ctx->last_pkt3_write_data = PKT3(PKT3_WRITE_DATA, 3, 0);
220 ctx->last_pkt3_write_data = NULL;
221
222 si_resource_reference(&ctx->last_ib_barrier_buf, ctx->barrier_buf);
223 ctx->last_ib_barrier_buf_offset = ctx->barrier_buf_offset;
224 si_resource_reference(&ctx->barrier_buf, NULL);
225
226 ws->fence_reference(&ctx->last_ib_barrier_fence, NULL);
227 }
228 }
229
230 if (ctx->is_noop)
231 flags |= RADEON_FLUSH_NOOP;
232
233 /* Flush the CS. */
234 ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
235 if (fence)
236 ws->fence_reference(fence, ctx->last_gfx_fence);
237
238 ctx->num_gfx_cs_flushes++;
239
240 if (si_compute_prim_discard_enabled(ctx)) {
241 /* Remember the last execution barrier, which is the last fence
242 * in this case.
243 */
244 if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
245 ctx->last_pkt3_write_data = NULL;
246 si_resource_reference(&ctx->last_ib_barrier_buf, NULL);
247 ws->fence_reference(&ctx->last_ib_barrier_fence, ctx->last_gfx_fence);
248 }
249 }
250
251 /* Check VM faults if needed. */
252 if (sscreen->debug_flags & DBG(CHECK_VM)) {
253 /* Use conservative timeout 800ms, after which we won't wait any
254 * longer and assume the GPU is hung.
255 */
256 ctx->ws->fence_wait(ctx->ws, ctx->last_gfx_fence, 800 * 1000 * 1000);
257
258 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
259 }
260
261 if (ctx->current_saved_cs)
262 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
263
264 si_begin_new_gfx_cs(ctx, false);
265 ctx->gfx_flush_in_progress = false;
266 }
267
si_begin_gfx_cs_debug(struct si_context * ctx)268 static void si_begin_gfx_cs_debug(struct si_context *ctx)
269 {
270 static const uint32_t zeros[1];
271 assert(!ctx->current_saved_cs);
272
273 ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
274 if (!ctx->current_saved_cs)
275 return;
276
277 pipe_reference_init(&ctx->current_saved_cs->reference, 1);
278
279 ctx->current_saved_cs->trace_buf =
280 si_resource(pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8));
281 if (!ctx->current_saved_cs->trace_buf) {
282 free(ctx->current_saved_cs);
283 ctx->current_saved_cs = NULL;
284 return;
285 }
286
287 pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b, 0, sizeof(zeros),
288 zeros);
289 ctx->current_saved_cs->trace_id = 0;
290
291 si_trace_emit(ctx);
292
293 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
294 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
295 }
296
si_add_gds_to_buffer_list(struct si_context * sctx)297 static void si_add_gds_to_buffer_list(struct si_context *sctx)
298 {
299 if (sctx->gds) {
300 sctx->ws->cs_add_buffer(sctx->gfx_cs, sctx->gds, RADEON_USAGE_READWRITE, 0, 0);
301 if (sctx->gds_oa) {
302 sctx->ws->cs_add_buffer(sctx->gfx_cs, sctx->gds_oa, RADEON_USAGE_READWRITE, 0, 0);
303 }
304 }
305 }
306
si_allocate_gds(struct si_context * sctx)307 void si_allocate_gds(struct si_context *sctx)
308 {
309 struct radeon_winsys *ws = sctx->ws;
310
311 if (sctx->gds)
312 return;
313
314 assert(sctx->screen->use_ngg_streamout);
315
316 /* 4 streamout GDS counters.
317 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
318 */
319 sctx->gds = ws->buffer_create(ws, 256, 4, RADEON_DOMAIN_GDS, RADEON_FLAG_DRIVER_INTERNAL);
320 sctx->gds_oa = ws->buffer_create(ws, 4, 1, RADEON_DOMAIN_OA, RADEON_FLAG_DRIVER_INTERNAL);
321
322 assert(sctx->gds && sctx->gds_oa);
323 si_add_gds_to_buffer_list(sctx);
324 }
325
si_set_tracked_regs_to_clear_state(struct si_context * ctx)326 void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
327 {
328 STATIC_ASSERT(SI_NUM_TRACKED_REGS <= sizeof(ctx->tracked_regs.reg_saved) * 8);
329
330 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
331 ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
332 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000;
333 ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000;
334 ctx->tracked_regs.reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff;
335 ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000;
336 ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
337 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
338 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
339 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
340 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
341 ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
342 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
343 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
344 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
345 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__VS] = 0x00000000;
346 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__CL] = 0x00000000;
347 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
348 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
349 ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
350 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ] = 0x3f800000;
351 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ] = 0x3f800000;
352 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000;
353 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ] = 0x3f800000;
354 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
355 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
356 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
357 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
358 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000;
359 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000;
360 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000;
361 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3] = 0x00000000;
362 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE] = 0x00000000;
363 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT] = 0x00000000;
364 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE] = 0x00000000;
365 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1] = 0x00000000;
366 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2] = 0x00000000;
367 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3] = 0x00000000;
368 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT] = 0x00000000;
369 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL] = 0x00000000;
370 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP] = 0x00000000;
371 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MODE] = 0x00000000;
372 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0x00000000;
373 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF] = 0x00000000;
374 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0x00000000;
375 ctx->tracked_regs.reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP] = 0x00000000;
376 ctx->tracked_regs.reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL] = 0x00000000;
377 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT] = 0x00000000;
378 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0x00000000;
379 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL] = 0x00000000;
380 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_NGG_CNTL] = 0x00000000;
381 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0x00000000;
382 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0x00000000;
383 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_BARYC_CNTL] = 0x00000000;
384 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_IN_CONTROL] = 0x00000002;
385 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0x00000000;
386 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0x00000000;
387 ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK] = 0xffffffff;
388 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000;
389 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x0000001e; /* From GFX8 */
390
391 /* Set all cleared context registers to saved. */
392 ctx->tracked_regs.reg_saved = ~(1ull << SI_TRACKED_GE_PC_ALLOC); /* uconfig reg */
393 ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
394 }
395
si_begin_new_gfx_cs(struct si_context * ctx,bool first_cs)396 void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
397 {
398 bool is_secure = false;
399
400 if (unlikely(radeon_uses_secure_bos(ctx->ws))) {
401 /* Disable features that don't work with TMZ:
402 * - primitive discard
403 */
404 ctx->prim_discard_vertex_count_threshold = UINT_MAX;
405
406 is_secure = ctx->ws->cs_is_secure(ctx->gfx_cs);
407 }
408
409 if (ctx->is_debug)
410 si_begin_gfx_cs_debug(ctx);
411
412 si_add_gds_to_buffer_list(ctx);
413
414 /* Always invalidate caches at the beginning of IBs, because external
415 * users (e.g. BO evictions and SDMA/UVD/VCE IBs) can modify our
416 * buffers.
417 *
418 * Note that the cache flush done by the kernel at the end of GFX IBs
419 * isn't useful here, because that flush can finish after the following
420 * IB starts drawing.
421 *
422 * TODO: Do we also need to invalidate CB & DB caches?
423 */
424 ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
425 SI_CONTEXT_INV_L2 | SI_CONTEXT_START_PIPELINE_STATS;
426
427 /* We don't know if the last draw call used GS fast launch, so assume it didn't. */
428 if (ctx->ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
429 ctx->flags |= SI_CONTEXT_VGT_FLUSH;
430
431 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->border_color_buffer,
432 RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
433 if (ctx->shadowed_regs) {
434 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->shadowed_regs,
435 RADEON_USAGE_READWRITE,
436 RADEON_PRIO_DESCRIPTORS);
437 }
438
439 si_add_all_descriptors_to_bo_list(ctx);
440
441 if (first_cs || !ctx->shadowed_regs) {
442 si_shader_pointers_mark_dirty(ctx);
443 ctx->cs_shader_state.initialized = false;
444 }
445
446 if (!ctx->has_graphics) {
447 ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
448 return;
449 }
450
451 if (ctx->tess_rings) {
452 radeon_add_to_buffer_list(ctx, ctx->gfx_cs,
453 unlikely(is_secure) ? si_resource(ctx->tess_rings_tmz) : si_resource(ctx->tess_rings),
454 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
455 }
456
457 /* set all valid group as dirty so they get reemited on
458 * next draw command
459 */
460 si_pm4_reset_emitted(ctx, first_cs);
461
462 /* The CS initialization should be emitted before everything else. */
463 if (ctx->cs_preamble_state)
464 si_pm4_emit(ctx, ctx->cs_preamble_state);
465 if (ctx->cs_preamble_tess_rings)
466 si_pm4_emit(ctx, unlikely(is_secure) ? ctx->cs_preamble_tess_rings_tmz :
467 ctx->cs_preamble_tess_rings);
468 if (ctx->cs_preamble_gs_rings)
469 si_pm4_emit(ctx, ctx->cs_preamble_gs_rings);
470
471 if (ctx->queued.named.ls)
472 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
473 if (ctx->queued.named.hs)
474 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
475 if (ctx->queued.named.es)
476 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
477 if (ctx->queued.named.gs)
478 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
479 if (ctx->queued.named.vs)
480 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
481 if (ctx->queued.named.ps)
482 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
483 if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
484 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
485
486 /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
487 bool has_clear_state = ctx->screen->info.has_clear_state;
488 if (has_clear_state || ctx->shadowed_regs) {
489 ctx->framebuffer.dirty_cbufs =
490 u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
491 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
492 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
493 } else {
494 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
495 ctx->framebuffer.dirty_zsbuf = true;
496 }
497
498 /* Even with shadowed registers, we have to add buffers to the buffer list.
499 * These atoms are the only ones that add buffers.
500 */
501 si_mark_atom_dirty(ctx, &ctx->atoms.s.framebuffer);
502 si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
503 if (ctx->screen->use_ngg_culling)
504 si_mark_atom_dirty(ctx, &ctx->atoms.s.ngg_cull_state);
505
506 if (first_cs || !ctx->shadowed_regs) {
507 /* These don't add any buffers, so skip them with shadowing. */
508 si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
509 /* CLEAR_STATE sets zeros. */
510 if (!has_clear_state || ctx->clip_state.any_nonzeros)
511 si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
512 ctx->sample_locs_num_samples = 0;
513 si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
514 si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_config);
515 /* CLEAR_STATE sets 0xffff. */
516 if (!has_clear_state || ctx->sample_mask != 0xffff)
517 si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
518 si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
519 /* CLEAR_STATE sets zeros. */
520 if (!has_clear_state || ctx->blend_color.any_nonzeros)
521 si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
522 si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
523 if (ctx->chip_class >= GFX9)
524 si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
525 si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
526 si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
527 if (!ctx->screen->use_ngg_streamout)
528 si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
529 /* CLEAR_STATE disables all window rectangles. */
530 if (!has_clear_state || ctx->num_window_rectangles > 0)
531 si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
532 si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
533 si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
534 si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
535
536 /* Invalidate various draw states so that they are emitted before
537 * the first draw call. */
538 si_invalidate_draw_sh_constants(ctx);
539 ctx->last_index_size = -1;
540 ctx->last_primitive_restart_en = -1;
541 ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
542 ctx->last_prim = -1;
543 ctx->last_multi_vgt_param = -1;
544 ctx->last_vs_state = ~0;
545 ctx->last_ls = NULL;
546 ctx->last_tcs = NULL;
547 ctx->last_tes_sh_base = -1;
548 ctx->last_num_tcs_input_cp = -1;
549 ctx->last_ls_hs_config = -1; /* impossible value */
550 ctx->last_binning_enabled = -1;
551
552 if (has_clear_state) {
553 si_set_tracked_regs_to_clear_state(ctx);
554 } else {
555 /* Set all register values to unknown. */
556 ctx->tracked_regs.reg_saved = 0;
557 ctx->last_gs_out_prim = -1; /* unknown */
558 }
559
560 /* 0xffffffff is an impossible value to register SPI_PS_INPUT_CNTL_n */
561 memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
562 }
563
564 si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state);
565 if (ctx->scratch_buffer) {
566 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
567 }
568
569 if (ctx->streamout.suspended) {
570 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
571 si_streamout_buffers_dirty(ctx);
572 }
573
574 if (!list_is_empty(&ctx->active_queries))
575 si_resume_queries(ctx);
576
577 assert(!ctx->gfx_cs->prev_dw);
578 ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
579 ctx->prim_discard_compute_ib_initialized = false;
580
581 /* Compute-based primitive discard:
582 * The index ring is divided into 2 halves. Switch between the halves
583 * in the same fashion as doublebuffering.
584 */
585 if (ctx->index_ring_base)
586 ctx->index_ring_base = 0;
587 else
588 ctx->index_ring_base = ctx->index_ring_size_per_ib;
589
590 ctx->index_ring_offset = 0;
591 }
592