1 /*
2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch_helpers.h>
10 #include <context.h>
11 #include <common/debug.h>
12 #include <lib/el3_runtime/context_mgmt.h>
13 #include <plat/common/platform.h>
14 #include <smccc_helpers.h>
15
16 #include "../bl1_private.h"
17
18 /*
19 * Following arrays will be used for context management.
20 * There are 2 instances, for the Secure and Non-Secure contexts.
21 */
22 static cpu_context_t bl1_cpu_context[2];
23 static smc_ctx_t bl1_smc_context[2];
24
25 /* Following contains the next cpu context pointer. */
26 static void *bl1_next_cpu_context_ptr;
27
28 /* Following contains the next smc context pointer. */
29 static void *bl1_next_smc_context_ptr;
30
31 /* Following functions are used for SMC context handling */
smc_get_ctx(unsigned int security_state)32 void *smc_get_ctx(unsigned int security_state)
33 {
34 assert(sec_state_is_valid(security_state));
35 return &bl1_smc_context[security_state];
36 }
37
smc_set_next_ctx(unsigned int security_state)38 void smc_set_next_ctx(unsigned int security_state)
39 {
40 assert(sec_state_is_valid(security_state));
41 bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
42 }
43
smc_get_next_ctx(void)44 void *smc_get_next_ctx(void)
45 {
46 return bl1_next_smc_context_ptr;
47 }
48
49 /* Following functions are used for CPU context handling */
cm_get_context(uint32_t security_state)50 void *cm_get_context(uint32_t security_state)
51 {
52 assert(sec_state_is_valid(security_state));
53 return &bl1_cpu_context[security_state];
54 }
55
cm_set_next_context(void * context)56 void cm_set_next_context(void *context)
57 {
58 assert(context != NULL);
59 bl1_next_cpu_context_ptr = context;
60 }
61
cm_get_next_context(void)62 void *cm_get_next_context(void)
63 {
64 return bl1_next_cpu_context_ptr;
65 }
66
67 /*******************************************************************************
68 * Following function copies GP regs r0-r4, lr and spsr,
69 * from the CPU context to the SMC context structures.
70 ******************************************************************************/
copy_cpu_ctx_to_smc_ctx(const regs_t * cpu_reg_ctx,smc_ctx_t * next_smc_ctx)71 static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
72 smc_ctx_t *next_smc_ctx)
73 {
74 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
75 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
76 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
77 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
78 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
79 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
80 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
81 }
82
83 /*******************************************************************************
84 * Following function flushes the SMC & CPU context pointer and its data.
85 ******************************************************************************/
flush_smc_and_cpu_ctx(void)86 static void flush_smc_and_cpu_ctx(void)
87 {
88 flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
89 sizeof(bl1_next_smc_context_ptr));
90 flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
91 sizeof(smc_ctx_t));
92
93 flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
94 sizeof(bl1_next_cpu_context_ptr));
95 flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
96 sizeof(cpu_context_t));
97 }
98
99 /*******************************************************************************
100 * This function prepares the context for Secure/Normal world images.
101 * Normal world images are transitioned to HYP(if supported) else SVC.
102 ******************************************************************************/
bl1_prepare_next_image(unsigned int image_id)103 void bl1_prepare_next_image(unsigned int image_id)
104 {
105 unsigned int security_state, mode = MODE32_svc;
106 image_desc_t *desc;
107 entry_point_info_t *next_bl_ep;
108
109 /* Get the image descriptor. */
110 desc = bl1_plat_get_image_desc(image_id);
111 assert(desc != NULL);
112
113 /* Get the entry point info. */
114 next_bl_ep = &desc->ep_info;
115
116 /* Get the image security state. */
117 security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
118
119 /* Prepare the SPSR for the next BL image. */
120 if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()) != 0U)) {
121 mode = MODE32_hyp;
122 }
123
124 next_bl_ep->spsr = SPSR_MODE32(mode, SPSR_T_ARM,
125 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
126
127 /* Allow platform to make change */
128 bl1_plat_set_ep_info(image_id, next_bl_ep);
129
130 /* Prepare the cpu context for the next BL image. */
131 cm_init_my_context(next_bl_ep);
132 cm_prepare_el3_exit(security_state);
133 cm_set_next_context(cm_get_context(security_state));
134
135 /* Prepare the smc context for the next BL image. */
136 smc_set_next_ctx(security_state);
137 copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
138 smc_get_next_ctx());
139
140 /*
141 * If the next image is non-secure, then we need to program the banked
142 * non secure sctlr. This is not required when the next image is secure
143 * because in AArch32, we expect the secure world to have the same
144 * SCTLR settings.
145 */
146 if (security_state == NON_SECURE) {
147 cpu_context_t *ctx = cm_get_context(security_state);
148 u_register_t ns_sctlr;
149
150 /* Temporarily set the NS bit to access NS SCTLR */
151 write_scr(read_scr() | SCR_NS_BIT);
152 isb();
153
154 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
155 write_sctlr(ns_sctlr);
156 isb();
157
158 write_scr(read_scr() & ~SCR_NS_BIT);
159 isb();
160 }
161
162 /*
163 * Flush the SMC & CPU context and the (next)pointers,
164 * to access them after caches are disabled.
165 */
166 flush_smc_and_cpu_ctx();
167
168 /* Indicate that image is in execution state. */
169 desc->state = IMAGE_STATE_EXECUTED;
170
171 print_entry_point_info(next_bl_ep);
172 }
173