Home
last modified time | relevance | path

Searched defs:sqshl (Results 1 – 8 of 8) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Dsqshl-diagnostics.s3 sqshl z0.b, p0/m, z0.b, #-1 label
8 sqshl z0.b, p0/m, z0.b, #8 label
13 sqshl z0.h, p0/m, z0.h, #-1 label
18 sqshl z0.h, p0/m, z0.h, #16 label
23 sqshl z0.s, p0/m, z0.s, #-1 label
28 sqshl z0.s, p0/m, z0.s, #32 label
33 sqshl z0.d, p0/m, z0.d, #-1 label
38 sqshl z0.d, p0/m, z0.d, #64 label
47 sqshl z0.b, p0/m, z1.b, z2.b label
52 sqshl z0.b, p0/m, z1.b, #0 label
[all …]
Dsqshl.s10 sqshl z0.b, p0/m, z0.b, z1.b label
16 sqshl z0.h, p0/m, z0.h, z1.h label
22 sqshl z29.s, p7/m, z29.s, z30.s label
28 sqshl z31.d, p7/m, z31.d, z30.d label
34 sqshl z0.b, p0/m, z0.b, #0 label
40 sqshl z31.b, p0/m, z31.b, #7 label
46 sqshl z0.h, p0/m, z0.h, #0 label
52 sqshl z31.h, p0/m, z31.h, #15 label
58 sqshl z0.s, p0/m, z0.s, #0 label
64 sqshl z31.s, p0/m, z31.s, #31 label
[all …]
/external/llvm/test/MC/AArch64/
Darm64-advsimd.s1367 sqshl d0, d0, #4 define
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-advsimd.s1367 sqshl d0, d0, #4 define
/external/llvm-project/llvm/test/MC/ARM/
Dmve-scalar-shift.s124 sqshl lr, #17 label
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1636 __ sqshl(b6, b21, b8); in GenerateTestSequenceNEON() local
1637 __ sqshl(b11, b26, 2); in GenerateTestSequenceNEON() local
1638 __ sqshl(d29, d0, d4); in GenerateTestSequenceNEON() local
1639 __ sqshl(d21, d7, 35); in GenerateTestSequenceNEON() local
1640 __ sqshl(h20, h25, h17); in GenerateTestSequenceNEON() local
1641 __ sqshl(h20, h0, 8); in GenerateTestSequenceNEON() local
1642 __ sqshl(s29, s13, s4); in GenerateTestSequenceNEON() local
1643 __ sqshl(s10, s11, 20); in GenerateTestSequenceNEON() local
1644 __ sqshl(v8.V16B(), v18.V16B(), v28.V16B()); in GenerateTestSequenceNEON() local
1645 __ sqshl(v29.V16B(), v29.V16B(), 2); in GenerateTestSequenceNEON() local
[all …]
/external/vixl/src/aarch64/
Dassembler-aarch64.cc4983 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) { in sqshl() function in vixl::aarch64::Assembler
Dlogic-aarch64.cc1868 LogicVRegister Simulator::sqshl(VectorFormat vform, in sqshl() function in vixl::aarch64::Simulator