| /external/llvm-project/llvm/test/MC/AArch64/SVE2/ |
| D | sri-diagnostics.s | 3 sri z30.b, z10.b, #0 label
8 sri z18.b, z27.b, #9 label
13 sri z26.h, z4.h, #0 label
18 sri z25.h, z10.h, #17 label
23 sri z17.s, z0.s, #0 label
28 sri z0.s, z15.s, #33 label
33 sri z4.d, z13.d, #0 label
38 sri z26.d, z26.d, #65 label
47 sri z0.b, z0.d, #1 label
57 sri z31.d, z31.d, #64 label
|
| D | sri.s | 10 sri z0.b, z0.b, #1 label
16 sri z31.b, z31.b, #8 label
22 sri z0.h, z0.h, #1 label
28 sri z31.h, z31.h, #16 label
34 sri z0.s, z0.s, #1 label
40 sri z31.s, z31.s, #32 label
46 sri z0.d, z0.d, #1 label
52 sri z31.d, z31.d, #64 label
|
| /external/libgsm/src/ |
| D | short_term.c | 275 register word sri, tmp1, tmp2; variable
328 register float sri = *wt++; variable
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1374 sri d0, d0, #1 define
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1374 sri d0, d0, #1 define
|
| /external/tensorflow/tensorflow/core/common_runtime/ |
| D | hierarchical_tree_broadcaster.cc | 179 for (int sri = 0; sri < num_subdivs; sri++) { in InitializeCollectiveParams() local
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1722 __ sri(d14, d14, 49); in GenerateTestSequenceNEON() local
1723 __ sri(v23.V16B(), v8.V16B(), 4); in GenerateTestSequenceNEON() local
1724 __ sri(v20.V2D(), v13.V2D(), 20); in GenerateTestSequenceNEON() local
1725 __ sri(v16.V2S(), v2.V2S(), 24); in GenerateTestSequenceNEON() local
1726 __ sri(v5.V4H(), v23.V4H(), 11); in GenerateTestSequenceNEON() local
1727 __ sri(v27.V4S(), v15.V4S(), 23); in GenerateTestSequenceNEON() local
1728 __ sri(v19.V8B(), v29.V8B(), 4); in GenerateTestSequenceNEON() local
1729 __ sri(v7.V8H(), v29.V8H(), 3); in GenerateTestSequenceNEON() local
|
| /external/nist-sip/java/gov/nist/javax/sip/stack/ |
| D | SIPTransactionStack.java | 1313 ServerResponseInterface sri = sipMessageFactory.newSIPServerResponse( in newSIPServerResponse() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 5053 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) { in sri() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 1901 LogicVRegister Simulator::sri(VectorFormat vform, in sri() function in vixl::aarch64::Simulator
|