| /external/libhevc/common/arm64/ |
| D | ihevc_intra_pred_luma_dc.s | 138 sshr d7, d7,#32 define
257 sshr d3, d3,#8 //row 0 shift (prol) (first value to be ignored) define
266 sshr d3, d3,#8 //row 1 shift (prol) define
275 sshr d3, d3,#8 //row 2 shift (prol) define
283 sshr d3, d3,#8 //row 3 shift (prol) define
291 sshr d3, d3,#8 //row 4 shift (prol) define
299 sshr d3, d3,#8 //row 5 shift (prol) define
310 sshr d3, d3,#8 //row 6 shift (prol) define
317 sshr d3, d3,#8 //row 7 shift (prol) define
346 sshr d3, d3,#8 //row 9 shift (prol) define
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1377 sshr d0, d0, #1 define
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1377 sshr d0, d0, #1 define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1768 __ sshr(d19, d21, 20); in GenerateTestSequenceNEON() local
1769 __ sshr(v15.V16B(), v23.V16B(), 5); in GenerateTestSequenceNEON() local
1770 __ sshr(v17.V2D(), v14.V2D(), 38); in GenerateTestSequenceNEON() local
1771 __ sshr(v3.V2S(), v29.V2S(), 23); in GenerateTestSequenceNEON() local
1772 __ sshr(v23.V4H(), v27.V4H(), 4); in GenerateTestSequenceNEON() local
1773 __ sshr(v28.V4S(), v3.V4S(), 4); in GenerateTestSequenceNEON() local
1774 __ sshr(v14.V8B(), v2.V8B(), 6); in GenerateTestSequenceNEON() local
1775 __ sshr(v3.V8H(), v8.V8H(), 6); in GenerateTestSequenceNEON() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 5060 void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) { in sshr() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 1938 LogicVRegister Simulator::sshr(VectorFormat vform, in sshr() function in vixl::aarch64::Simulator
|