| /external/llvm-project/llvm/test/MC/AArch64/SVE2/ |
| D | ssra-diagnostics.s | 3 ssra z30.b, z10.b, #0 label
8 ssra z18.b, z27.b, #9 label
13 ssra z26.h, z4.h, #0 label
18 ssra z25.h, z10.h, #17 label
23 ssra z17.s, z0.s, #0 label
28 ssra z0.s, z15.s, #33 label
33 ssra z4.d, z13.d, #0 label
38 ssra z26.d, z26.d, #65 label
47 ssra z0.b, z0.d, #1 label
57 ssra z0.d, z1.d, #64 label
|
| D | ssra.s | 10 ssra z0.b, z0.b, #1 label
16 ssra z31.b, z31.b, #8 label
22 ssra z0.h, z0.h, #1 label
28 ssra z31.h, z31.h, #16 label
34 ssra z0.s, z0.s, #1 label
40 ssra z31.s, z31.s, #32 label
46 ssra z0.d, z0.d, #1 label
52 ssra z31.d, z31.d, #64 label
68 ssra z0.d, z1.d, #1 label
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1565 ssra d0, d0, #64 define
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1565 ssra d0, d0, #64 define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1776 __ ssra(d12, d28, 44); in GenerateTestSequenceNEON() local
1777 __ ssra(v29.V16B(), v31.V16B(), 4); in GenerateTestSequenceNEON() local
1778 __ ssra(v3.V2D(), v0.V2D(), 24); in GenerateTestSequenceNEON() local
1779 __ ssra(v14.V2S(), v28.V2S(), 6); in GenerateTestSequenceNEON() local
1780 __ ssra(v18.V4H(), v8.V4H(), 7); in GenerateTestSequenceNEON() local
1781 __ ssra(v31.V4S(), v14.V4S(), 24); in GenerateTestSequenceNEON() local
1782 __ ssra(v28.V8B(), v26.V8B(), 5); in GenerateTestSequenceNEON() local
1783 __ ssra(v9.V8H(), v9.V8H(), 14); in GenerateTestSequenceNEON() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 5088 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) { in ssra() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 1949 LogicVRegister Simulator::ssra(VectorFormat vform, in ssra() function in vixl::aarch64::Simulator
|