1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <stdio.h>
25
26 #include "CUnit/Basic.h"
27
28 #include "util_math.h"
29
30 #include "amdgpu_test.h"
31 #include "decode_messages.h"
32 #include "amdgpu_drm.h"
33 #include "amdgpu_internal.h"
34
35 #define IB_SIZE 4096
36 #define MAX_RESOURCES 16
37
38 static amdgpu_device_handle device_handle;
39 static uint32_t major_version;
40 static uint32_t minor_version;
41 static uint32_t family_id;
42 static uint32_t chip_rev;
43 static uint32_t chip_id;
44
45 static amdgpu_context_handle context_handle;
46 static amdgpu_bo_handle ib_handle;
47 static uint64_t ib_mc_address;
48 static uint32_t *ib_cpu;
49 static amdgpu_va_handle ib_va_handle;
50
51 static amdgpu_bo_handle resources[MAX_RESOURCES];
52 static unsigned num_resources;
53
54 static void amdgpu_cs_uvd_create(void);
55 static void amdgpu_cs_uvd_decode(void);
56 static void amdgpu_cs_uvd_destroy(void);
57
58 CU_TestInfo cs_tests[] = {
59 { "UVD create", amdgpu_cs_uvd_create },
60 { "UVD decode", amdgpu_cs_uvd_decode },
61 { "UVD destroy", amdgpu_cs_uvd_destroy },
62 CU_TEST_INFO_NULL,
63 };
64
suite_cs_tests_enable(void)65 CU_BOOL suite_cs_tests_enable(void)
66 {
67 uint32_t asic_id;
68
69 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
70 &minor_version, &device_handle))
71 return CU_FALSE;
72
73 family_id = device_handle->info.family_id;
74 asic_id = device_handle->info.asic_id;
75
76 if (amdgpu_device_deinitialize(device_handle))
77 return CU_FALSE;
78
79
80 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
81 asic_is_arcturus(asic_id)) {
82 printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
83 return CU_FALSE;
84 }
85
86 return CU_TRUE;
87 }
88
suite_cs_tests_init(void)89 int suite_cs_tests_init(void)
90 {
91 amdgpu_bo_handle ib_result_handle;
92 void *ib_result_cpu;
93 uint64_t ib_result_mc_address;
94 amdgpu_va_handle ib_result_va_handle;
95 int r;
96
97 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
98 &minor_version, &device_handle);
99 if (r) {
100 if ((r == -EACCES) && (errno == EACCES))
101 printf("\n\nError:%s. "
102 "Hint:Try to run this test program as root.",
103 strerror(errno));
104
105 return CUE_SINIT_FAILED;
106 }
107
108 family_id = device_handle->info.family_id;
109 /* VI asic POLARIS10/11 have specific external_rev_id */
110 chip_rev = device_handle->info.chip_rev;
111 chip_id = device_handle->info.chip_external_rev;
112
113 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
114 if (r)
115 return CUE_SINIT_FAILED;
116
117 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
118 AMDGPU_GEM_DOMAIN_GTT, 0,
119 &ib_result_handle, &ib_result_cpu,
120 &ib_result_mc_address,
121 &ib_result_va_handle);
122 if (r)
123 return CUE_SINIT_FAILED;
124
125 ib_handle = ib_result_handle;
126 ib_mc_address = ib_result_mc_address;
127 ib_cpu = ib_result_cpu;
128 ib_va_handle = ib_result_va_handle;
129
130 return CUE_SUCCESS;
131 }
132
suite_cs_tests_clean(void)133 int suite_cs_tests_clean(void)
134 {
135 int r;
136
137 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
138 ib_mc_address, IB_SIZE);
139 if (r)
140 return CUE_SCLEAN_FAILED;
141
142 r = amdgpu_cs_ctx_free(context_handle);
143 if (r)
144 return CUE_SCLEAN_FAILED;
145
146 r = amdgpu_device_deinitialize(device_handle);
147 if (r)
148 return CUE_SCLEAN_FAILED;
149
150 return CUE_SUCCESS;
151 }
152
submit(unsigned ndw,unsigned ip)153 static int submit(unsigned ndw, unsigned ip)
154 {
155 struct amdgpu_cs_request ibs_request = {0};
156 struct amdgpu_cs_ib_info ib_info = {0};
157 struct amdgpu_cs_fence fence_status = {0};
158 uint32_t expired;
159 int r;
160
161 ib_info.ib_mc_address = ib_mc_address;
162 ib_info.size = ndw;
163
164 ibs_request.ip_type = ip;
165
166 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
167 NULL, &ibs_request.resources);
168 if (r)
169 return r;
170
171 ibs_request.number_of_ibs = 1;
172 ibs_request.ibs = &ib_info;
173 ibs_request.fence_info.handle = NULL;
174
175 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
176 if (r)
177 return r;
178
179 r = amdgpu_bo_list_destroy(ibs_request.resources);
180 if (r)
181 return r;
182
183 fence_status.context = context_handle;
184 fence_status.ip_type = ip;
185 fence_status.fence = ibs_request.seq_no;
186
187 r = amdgpu_cs_query_fence_status(&fence_status,
188 AMDGPU_TIMEOUT_INFINITE,
189 0, &expired);
190 if (r)
191 return r;
192
193 return 0;
194 }
195
uvd_cmd(uint64_t addr,unsigned cmd,int * idx)196 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
197 {
198 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4;
199 ib_cpu[(*idx)++] = addr;
200 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5;
201 ib_cpu[(*idx)++] = addr >> 32;
202 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3;
203 ib_cpu[(*idx)++] = cmd << 1;
204 }
205
amdgpu_cs_uvd_create(void)206 static void amdgpu_cs_uvd_create(void)
207 {
208 struct amdgpu_bo_alloc_request req = {0};
209 amdgpu_bo_handle buf_handle;
210 uint64_t va = 0;
211 amdgpu_va_handle va_handle;
212 void *msg;
213 int i, r;
214
215 req.alloc_size = 4*1024;
216 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
217
218 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
219 CU_ASSERT_EQUAL(r, 0);
220
221 r = amdgpu_va_range_alloc(device_handle,
222 amdgpu_gpu_va_range_general,
223 4096, 1, 0, &va,
224 &va_handle, 0);
225 CU_ASSERT_EQUAL(r, 0);
226
227 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
228 CU_ASSERT_EQUAL(r, 0);
229
230 r = amdgpu_bo_cpu_map(buf_handle, &msg);
231 CU_ASSERT_EQUAL(r, 0);
232
233 memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
234
235 if (family_id >= AMDGPU_FAMILY_VI) {
236 ((uint8_t*)msg)[0x10] = 7;
237 /* chip beyond polaris 10/11 */
238 if ((family_id == AMDGPU_FAMILY_AI) ||
239 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
240 chip_id == chip_rev+0x64)) {
241 /* dpb size */
242 ((uint8_t*)msg)[0x28] = 0x00;
243 ((uint8_t*)msg)[0x29] = 0x94;
244 ((uint8_t*)msg)[0x2A] = 0x6B;
245 ((uint8_t*)msg)[0x2B] = 0x00;
246 }
247 }
248
249 r = amdgpu_bo_cpu_unmap(buf_handle);
250 CU_ASSERT_EQUAL(r, 0);
251
252 num_resources = 0;
253 resources[num_resources++] = buf_handle;
254 resources[num_resources++] = ib_handle;
255
256 i = 0;
257 uvd_cmd(va, 0x0, &i);
258 for (; i % 16; ++i)
259 ib_cpu[i] = 0x80000000;
260
261 r = submit(i, AMDGPU_HW_IP_UVD);
262 CU_ASSERT_EQUAL(r, 0);
263
264 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
265 CU_ASSERT_EQUAL(r, 0);
266
267 r = amdgpu_va_range_free(va_handle);
268 CU_ASSERT_EQUAL(r, 0);
269
270 r = amdgpu_bo_free(buf_handle);
271 CU_ASSERT_EQUAL(r, 0);
272 }
273
amdgpu_cs_uvd_decode(void)274 static void amdgpu_cs_uvd_decode(void)
275 {
276 const unsigned dpb_size = 15923584, dt_size = 737280;
277 uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
278 struct amdgpu_bo_alloc_request req = {0};
279 amdgpu_bo_handle buf_handle;
280 amdgpu_va_handle va_handle;
281 uint64_t va = 0;
282 uint64_t sum;
283 uint8_t *ptr;
284 int i, r;
285
286 req.alloc_size = 4*1024; /* msg */
287 req.alloc_size += 4*1024; /* fb */
288 if (family_id >= AMDGPU_FAMILY_VI)
289 req.alloc_size += 4096; /*it_scaling_table*/
290 req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
291 req.alloc_size += ALIGN(dpb_size, 4*1024);
292 req.alloc_size += ALIGN(dt_size, 4*1024);
293
294 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
295
296 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
297 CU_ASSERT_EQUAL(r, 0);
298
299 r = amdgpu_va_range_alloc(device_handle,
300 amdgpu_gpu_va_range_general,
301 req.alloc_size, 1, 0, &va,
302 &va_handle, 0);
303 CU_ASSERT_EQUAL(r, 0);
304
305 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
306 AMDGPU_VA_OP_MAP);
307 CU_ASSERT_EQUAL(r, 0);
308
309 r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
310 CU_ASSERT_EQUAL(r, 0);
311
312 memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg));
313 memcpy(ptr + sizeof(uvd_decode_msg), avc_decode_msg, sizeof(avc_decode_msg));
314
315 if (family_id >= AMDGPU_FAMILY_VI) {
316 ptr[0x10] = 7;
317 ptr[0x98] = 0x00;
318 ptr[0x99] = 0x02;
319 /* chip beyond polaris10/11 */
320 if ((family_id == AMDGPU_FAMILY_AI) ||
321 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
322 chip_id == chip_rev+0x64)) {
323 /* dpb size */
324 ptr[0x24] = 0x00;
325 ptr[0x25] = 0x94;
326 ptr[0x26] = 0x6B;
327 ptr[0x27] = 0x00;
328 /*ctx size */
329 ptr[0x2C] = 0x00;
330 ptr[0x2D] = 0xAF;
331 ptr[0x2E] = 0x50;
332 ptr[0x2F] = 0x00;
333 }
334 }
335
336 ptr += 4*1024;
337 memset(ptr, 0, 4*1024);
338 if (family_id >= AMDGPU_FAMILY_VI) {
339 ptr += 4*1024;
340 memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
341 }
342
343 ptr += 4*1024;
344 memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
345
346 ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
347 memset(ptr, 0, dpb_size);
348
349 ptr += ALIGN(dpb_size, 4*1024);
350 memset(ptr, 0, dt_size);
351
352 num_resources = 0;
353 resources[num_resources++] = buf_handle;
354 resources[num_resources++] = ib_handle;
355
356 msg_addr = va;
357 fb_addr = msg_addr + 4*1024;
358 if (family_id >= AMDGPU_FAMILY_VI) {
359 it_addr = fb_addr + 4*1024;
360 bs_addr = it_addr + 4*1024;
361 } else
362 bs_addr = fb_addr + 4*1024;
363 dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
364
365 ctx_addr = 0;
366 if (family_id >= AMDGPU_FAMILY_VI) {
367 if ((family_id == AMDGPU_FAMILY_AI) ||
368 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
369 chip_id == chip_rev+0x64)) {
370 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
371 }
372 }
373
374 dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
375
376 i = 0;
377 uvd_cmd(msg_addr, 0x0, &i);
378 uvd_cmd(dpb_addr, 0x1, &i);
379 uvd_cmd(dt_addr, 0x2, &i);
380 uvd_cmd(fb_addr, 0x3, &i);
381 uvd_cmd(bs_addr, 0x100, &i);
382
383 if (family_id >= AMDGPU_FAMILY_VI) {
384 uvd_cmd(it_addr, 0x204, &i);
385 if ((family_id == AMDGPU_FAMILY_AI) ||
386 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
387 chip_id == chip_rev+0x64))
388 uvd_cmd(ctx_addr, 0x206, &i);
389 }
390
391 ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
392 ib_cpu[i++] = 0x1;
393 for (; i % 16; ++i)
394 ib_cpu[i] = 0x80000000;
395
396 r = submit(i, AMDGPU_HW_IP_UVD);
397 CU_ASSERT_EQUAL(r, 0);
398
399 /* TODO: use a real CRC32 */
400 for (i = 0, sum = 0; i < dt_size; ++i)
401 sum += ptr[i];
402 CU_ASSERT_EQUAL(sum, SUM_DECODE);
403
404 r = amdgpu_bo_cpu_unmap(buf_handle);
405 CU_ASSERT_EQUAL(r, 0);
406
407 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
408 CU_ASSERT_EQUAL(r, 0);
409
410 r = amdgpu_va_range_free(va_handle);
411 CU_ASSERT_EQUAL(r, 0);
412
413 r = amdgpu_bo_free(buf_handle);
414 CU_ASSERT_EQUAL(r, 0);
415 }
416
amdgpu_cs_uvd_destroy(void)417 static void amdgpu_cs_uvd_destroy(void)
418 {
419 struct amdgpu_bo_alloc_request req = {0};
420 amdgpu_bo_handle buf_handle;
421 amdgpu_va_handle va_handle;
422 uint64_t va = 0;
423 void *msg;
424 int i, r;
425
426 req.alloc_size = 4*1024;
427 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
428
429 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
430 CU_ASSERT_EQUAL(r, 0);
431
432 r = amdgpu_va_range_alloc(device_handle,
433 amdgpu_gpu_va_range_general,
434 req.alloc_size, 1, 0, &va,
435 &va_handle, 0);
436 CU_ASSERT_EQUAL(r, 0);
437
438 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
439 AMDGPU_VA_OP_MAP);
440 CU_ASSERT_EQUAL(r, 0);
441
442 r = amdgpu_bo_cpu_map(buf_handle, &msg);
443 CU_ASSERT_EQUAL(r, 0);
444
445 memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
446 if (family_id >= AMDGPU_FAMILY_VI)
447 ((uint8_t*)msg)[0x10] = 7;
448
449 r = amdgpu_bo_cpu_unmap(buf_handle);
450 CU_ASSERT_EQUAL(r, 0);
451
452 num_resources = 0;
453 resources[num_resources++] = buf_handle;
454 resources[num_resources++] = ib_handle;
455
456 i = 0;
457 uvd_cmd(va, 0x0, &i);
458 for (; i % 16; ++i)
459 ib_cpu[i] = 0x80000000;
460
461 r = submit(i, AMDGPU_HW_IP_UVD);
462 CU_ASSERT_EQUAL(r, 0);
463
464 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
465 CU_ASSERT_EQUAL(r, 0);
466
467 r = amdgpu_va_range_free(va_handle);
468 CU_ASSERT_EQUAL(r, 0);
469
470 r = amdgpu_bo_free(buf_handle);
471 CU_ASSERT_EQUAL(r, 0);
472 }
473