1 /*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <drivers/delay_timer.h>
14 #include <lib/mmio.h>
15 #include <lib/utils_def.h>
16 #include <plat/common/platform.h>
17
18 #include <core_off_arisc.h>
19 #include <sunxi_cpucfg.h>
20 #include <sunxi_mmap.h>
21 #include <sunxi_private.h>
22
sunxi_cpu_disable_power(unsigned int cluster,unsigned int core)23 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
24 {
25 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
26 return;
27
28 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
29
30 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff);
31 }
32
sunxi_cpu_enable_power(unsigned int cluster,unsigned int core)33 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
34 {
35 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0)
36 return;
37
38 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
39
40 /* Power enable sequence from original Allwinner sources */
41 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe);
42 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8);
43 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0);
44 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80);
45 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
46 }
47
sunxi_cpu_off(u_register_t mpidr)48 void sunxi_cpu_off(u_register_t mpidr)
49 {
50 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
51 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
52
53 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
54
55 /* Deassert DBGPWRDUP */
56 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
57
58 /* We can't turn ourself off like this, but it works for other cores. */
59 if (read_mpidr() != mpidr) {
60 /* Activate the core output clamps, but not for core 0. */
61 if (core != 0)
62 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
63 BIT(core));
64 /* Assert CPU power-on reset */
65 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
66 /* Remove power from the CPU */
67 sunxi_cpu_disable_power(cluster, core);
68
69 return;
70 }
71
72 /* Simplifies assembly, all SoCs so far are single cluster anyway. */
73 assert(cluster == 0);
74
75 /*
76 * If we are supposed to turn ourself off, tell the arisc SCP
77 * to do that work for us. The code expects the core mask to be
78 * patched into the first instruction.
79 */
80 sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
81 BIT_32(core));
82 }
83
sunxi_cpu_on(u_register_t mpidr)84 void sunxi_cpu_on(u_register_t mpidr)
85 {
86 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
87 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
88
89 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
90
91 /* Assert CPU core reset */
92 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
93 /* Assert CPU power-on reset */
94 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
95 /* Set CPU to start in AArch64 mode */
96 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core));
97 /* Apply power to the CPU */
98 sunxi_cpu_enable_power(cluster, core);
99 /* Release the core output clamps */
100 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
101 /* Deassert CPU power-on reset */
102 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
103 /* Deassert CPU core reset */
104 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
105 /* Assert DBGPWRDUP */
106 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
107 }
108
sunxi_disable_secondary_cpus(u_register_t primary_mpidr)109 void sunxi_disable_secondary_cpus(u_register_t primary_mpidr)
110 {
111 unsigned int cluster;
112 unsigned int core;
113
114 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) {
115 for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) {
116 u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) |
117 (core << MPIDR_AFF0_SHIFT) |
118 BIT(31);
119 if (mpidr != primary_mpidr)
120 sunxi_cpu_off(mpidr);
121 }
122 }
123 }
124