1 /*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <lib/mmio.h>
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 #include <plat/common/platform.h>
16
17 #include <sunxi_def.h>
18 #include <sunxi_mmap.h>
19 #include <sunxi_private.h>
20
21 static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
22 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
23 MT_RW_DATA | MT_SECURE),
24 MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
25 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
26 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
27 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
28 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
29 MT_RW_DATA | MT_SECURE),
30 MAP_REGION(PRELOADED_BL33_BASE,
31 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE,
32 SUNXI_DRAM_MAP_SIZE,
33 MT_RO_DATA | MT_NS),
34 {},
35 };
36
plat_get_syscnt_freq2(void)37 unsigned int plat_get_syscnt_freq2(void)
38 {
39 return SUNXI_OSC24M_CLK_IN_HZ;
40 }
41
sunxi_configure_mmu_el3(int flags)42 void sunxi_configure_mmu_el3(int flags)
43 {
44 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
45 BL_CODE_END - BL_CODE_BASE,
46 MT_CODE | MT_SECURE);
47 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
48 BL_RO_DATA_END - BL_RO_DATA_BASE,
49 MT_RO_DATA | MT_SECURE);
50 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
51 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
52 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
53
54 mmap_add(sunxi_mmap);
55 init_xlat_tables();
56
57 enable_mmu_el3(0);
58 }
59
60 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24)
sunxi_read_soc_id(void)61 uint16_t sunxi_read_soc_id(void)
62 {
63 uint32_t reg = mmio_read_32(SRAM_VER_REG);
64
65 /* Set bit 15 to prepare for the SOCID read. */
66 mmio_write_32(SRAM_VER_REG, reg | BIT(15));
67
68 reg = mmio_read_32(SRAM_VER_REG);
69
70 /* deactivate the SOCID access again */
71 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15));
72
73 return reg >> 16;
74 }
75
76 /*
77 * Configure a given pin to the GPIO-OUT function and sets its level.
78 * The port is given as a capital letter, the pin is the number within
79 * this port group.
80 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true);
81 */
sunxi_set_gpio_out(char port,int pin,bool level_high)82 void sunxi_set_gpio_out(char port, int pin, bool level_high)
83 {
84 uintptr_t port_base;
85
86 if (port < 'A' || port > 'L')
87 return;
88 if (port == 'L')
89 port_base = SUNXI_R_PIO_BASE;
90 else
91 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24;
92
93 /* Set the new level first before configuring the pin. */
94 if (level_high)
95 mmio_setbits_32(port_base + 0x10, BIT(pin));
96 else
97 mmio_clrbits_32(port_base + 0x10, BIT(pin));
98
99 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */
100 mmio_clrsetbits_32(port_base + (pin / 8) * 4,
101 0x7 << ((pin % 8) * 4),
102 0x1 << ((pin % 8) * 4));
103 }
104
sunxi_init_platform_r_twi(uint16_t socid,bool use_rsb)105 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb)
106 {
107 uint32_t pin_func = 0x77;
108 uint32_t device_bit;
109 unsigned int reset_offset = 0xb0;
110
111 switch (socid) {
112 case SUNXI_SOC_H5:
113 if (use_rsb)
114 return -ENODEV;
115 pin_func = 0x22;
116 device_bit = BIT(6);
117 break;
118 case SUNXI_SOC_H6:
119 pin_func = use_rsb ? 0x22 : 0x33;
120 device_bit = BIT(16);
121 reset_offset = use_rsb ? 0x1bc : 0x19c;
122 break;
123 case SUNXI_SOC_A64:
124 pin_func = use_rsb ? 0x22 : 0x33;
125 device_bit = use_rsb ? BIT(3) : BIT(6);
126 break;
127 default:
128 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid);
129 return -ENODEV;
130 }
131
132 /* un-gate R_PIO clock */
133 if (socid != SUNXI_SOC_H6)
134 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0));
135
136 /* switch pins PL0 and PL1 to the desired function */
137 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func);
138
139 /* level 2 drive strength */
140 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU);
141
142 /* set both pins to pull-up */
143 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U);
144
145 /* un-gate clock */
146 if (socid != SUNXI_SOC_H6)
147 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
148 else
149 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0));
150
151 /* assert, then de-assert reset of I2C/RSB controller */
152 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
153 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
154
155 return 0;
156 }
157
158 /* This lock synchronises access to the arisc management processor. */
159 DEFINE_BAKERY_LOCK(arisc_lock);
160
161 /*
162 * Tell the "arisc" SCP core (an OpenRISC core) to execute some code.
163 * We don't have any service running there, so we place some OpenRISC code
164 * in SRAM, put the address of that into the reset vector and release the
165 * arisc reset line. The SCP will execute that code and pull the line up again.
166 */
sunxi_execute_arisc_code(uint32_t * code,size_t size,uint16_t param)167 void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param)
168 {
169 uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100;
170
171 do {
172 bakery_lock_get(&arisc_lock);
173 /* Wait until the arisc is in reset state. */
174 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0)))
175 break;
176
177 bakery_lock_release(&arisc_lock);
178 } while (1);
179
180 /* Patch up the code to feed in an input parameter. */
181 code[0] = (code[0] & ~0xffff) | param;
182 clean_dcache_range((uintptr_t)code, size);
183
184 /*
185 * The OpenRISC unconditional branch has opcode 0, the branch offset
186 * is in the lower 26 bits, containing the distance to the target,
187 * in instruction granularity (32 bits).
188 */
189 mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
190 clean_dcache_range(arisc_reset_vec, 4);
191
192 /* De-assert the arisc reset line to let it run. */
193 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
194
195 /*
196 * We release the lock here, although the arisc is still busy.
197 * But as long as it runs, the reset line is high, so other users
198 * won't leave the loop above.
199 * Once it has finished, the code is supposed to clear the reset line,
200 * to signal this to other users.
201 */
202 bakery_lock_release(&arisc_lock);
203 }
204