1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(__attribute__((unused)) void *data,
31 __attribute__((unused)) void *loc, uint64_t addr,
32 uint32_t delta)
33 {
34 return addr + delta;
35 }
36
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
39
40 #include "isl_priv.h"
41
42 #if GEN_GEN >= 8
43 static const uint8_t isl_to_gen_halign[] = {
44 [4] = HALIGN4,
45 [8] = HALIGN8,
46 [16] = HALIGN16,
47 };
48 #elif GEN_GEN >= 7
49 static const uint8_t isl_to_gen_halign[] = {
50 [4] = HALIGN_4,
51 [8] = HALIGN_8,
52 };
53 #endif
54
55 #if GEN_GEN >= 8
56 static const uint8_t isl_to_gen_valign[] = {
57 [4] = VALIGN4,
58 [8] = VALIGN8,
59 [16] = VALIGN16,
60 };
61 #elif GEN_GEN >= 6
62 static const uint8_t isl_to_gen_valign[] = {
63 [2] = VALIGN_2,
64 [4] = VALIGN_4,
65 };
66 #endif
67
68 #if GEN_GEN >= 8
69 static const uint8_t isl_to_gen_tiling[] = {
70 [ISL_TILING_LINEAR] = LINEAR,
71 [ISL_TILING_X] = XMAJOR,
72 [ISL_TILING_Y0] = YMAJOR,
73 [ISL_TILING_Yf] = YMAJOR,
74 [ISL_TILING_Ys] = YMAJOR,
75 #if GEN_GEN <= 11
76 [ISL_TILING_W] = WMAJOR,
77 #endif
78 };
79 #endif
80
81 #if GEN_GEN >= 7
82 static const uint32_t isl_to_gen_multisample_layout[] = {
83 [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS,
84 [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL,
85 [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS,
86 };
87 #endif
88
89 #if GEN_GEN >= 12
90 static const uint32_t isl_to_gen_aux_mode[] = {
91 [ISL_AUX_USAGE_NONE] = AUX_NONE,
92 [ISL_AUX_USAGE_MC] = AUX_NONE,
93 [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
94 [ISL_AUX_USAGE_GEN12_CCS_E] = AUX_CCS_E,
95 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
96 [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
97 [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
98 [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E,
99 };
100 #elif GEN_GEN >= 9
101 static const uint32_t isl_to_gen_aux_mode[] = {
102 [ISL_AUX_USAGE_NONE] = AUX_NONE,
103 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
104 [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
105 [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
106 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
107 };
108 #elif GEN_GEN >= 8
109 static const uint32_t isl_to_gen_aux_mode[] = {
110 [ISL_AUX_USAGE_NONE] = AUX_NONE,
111 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
112 [ISL_AUX_USAGE_MCS] = AUX_MCS,
113 [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
114 };
115 #endif
116
117 static uint8_t
get_surftype(enum isl_surf_dim dim,isl_surf_usage_flags_t usage)118 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
119 {
120 switch (dim) {
121 default:
122 unreachable("bad isl_surf_dim");
123 case ISL_SURF_DIM_1D:
124 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
125 return SURFTYPE_1D;
126 case ISL_SURF_DIM_2D:
127 if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
128 (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
129 /* We need SURFTYPE_CUBE to make cube sampling work */
130 return SURFTYPE_CUBE;
131 } else {
132 /* Everything else (render and storage) treat cubes as plain
133 * 2D array textures
134 */
135 return SURFTYPE_2D;
136 }
137 case ISL_SURF_DIM_3D:
138 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
139 return SURFTYPE_3D;
140 }
141 }
142
143 /**
144 * Get the horizontal and vertical alignment in the units expected by the
145 * hardware. Note that this does NOT give you the actual hardware enum values
146 * but an index into the isl_to_gen_[hv]align arrays above.
147 */
148 UNUSED static struct isl_extent3d
get_image_alignment(const struct isl_surf * surf)149 get_image_alignment(const struct isl_surf *surf)
150 {
151 if (GEN_GEN >= 9) {
152 if (isl_tiling_is_std_y(surf->tiling) ||
153 surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
154 /* The hardware ignores the alignment values. Anyway, the surface's
155 * true alignment is likely outside the enum range of HALIGN* and
156 * VALIGN*.
157 */
158 return isl_extent3d(4, 4, 1);
159 } else {
160 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
161 * of surface elements (not pixels nor samples). For compressed formats,
162 * a "surface element" is defined as a compression block. For example,
163 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
164 * format (ETC2 has a block height of 4), then the vertical alignment is
165 * 4 compression blocks or, equivalently, 16 pixels.
166 */
167 return isl_surf_get_image_alignment_el(surf);
168 }
169 } else {
170 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
171 * units of surface samples. For example, if SurfaceVerticalAlignment
172 * is VALIGN_4 and the surface is singlesampled, then for any surface
173 * format (compressed or not) the vertical alignment is
174 * 4 pixels.
175 */
176 return isl_surf_get_image_alignment_sa(surf);
177 }
178 }
179
180 #if GEN_GEN >= 8
181 static uint32_t
get_qpitch(const struct isl_surf * surf)182 get_qpitch(const struct isl_surf *surf)
183 {
184 switch (surf->dim_layout) {
185 default:
186 unreachable("Bad isl_surf_dim");
187 case ISL_DIM_LAYOUT_GEN4_2D:
188 if (GEN_GEN >= 9) {
189 if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
190 /* This is rather annoying and completely undocumented. It
191 * appears that the hardware has a bug (or undocumented feature)
192 * regarding stencil buffers most likely related to the way
193 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
194 * stencil buffer normally, and use texelFetch on it, the z or
195 * array index will get implicitly multiplied by 2 for no obvious
196 * reason. The fix appears to be to divide qpitch by 2 for
197 * W-tiled surfaces.
198 */
199 return isl_surf_get_array_pitch_el_rows(surf) / 2;
200 } else {
201 return isl_surf_get_array_pitch_el_rows(surf);
202 }
203 } else {
204 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
205 *
206 * "This field must be set to an integer multiple of the Surface
207 * Vertical Alignment. For compressed textures (BC*, FXT1,
208 * ETC*, and EAC* Surface Formats), this field is in units of
209 * rows in the uncompressed surface, and must be set to an
210 * integer multiple of the vertical alignment parameter "j"
211 * defined in the Common Surface Formats section."
212 */
213 return isl_surf_get_array_pitch_sa_rows(surf);
214 }
215 case ISL_DIM_LAYOUT_GEN9_1D:
216 /* QPitch is usually expressed as rows of surface elements (where
217 * a surface element is an compression block or a single surface
218 * sample). Skylake 1D is an outlier.
219 *
220 * From the Skylake BSpec >> Memory Views >> Common Surface
221 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
222 *
223 * Surface QPitch specifies the distance in pixels between array
224 * slices.
225 */
226 return isl_surf_get_array_pitch_el(surf);
227 case ISL_DIM_LAYOUT_GEN4_3D:
228 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
229 * different pitch at each LOD. Also, the QPitch field is ignored for
230 * these surfaces. From the Broadwell PRM documentation for QPitch:
231 *
232 * This field specifies the distance in rows between array slices. It
233 * is used only in the following cases:
234 * - Surface Array is enabled OR
235 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
236 * Surface Storage Format set to MSFMT_MSS OR
237 * - Surface Type is SURFTYPE_CUBE
238 *
239 * None of the three conditions above can possibly apply to a 3D surface
240 * so it is safe to just set QPitch to 0.
241 */
242 return 0;
243 }
244 }
245 #endif /* GEN_GEN >= 8 */
246
247 void
isl_genX(surf_fill_state_s)248 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
249 const struct isl_surf_fill_state_info *restrict info)
250 {
251 struct GENX(RENDER_SURFACE_STATE) s = { 0 };
252
253 s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
254
255 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
256 assert(isl_format_supports_rendering(dev->info, info->view->format));
257 else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
258 assert(isl_format_supports_sampling(dev->info, info->view->format));
259
260 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
261 *
262 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
263 * format if the Surface Type is SURFTYPE_1D
264 */
265 if (info->surf->dim == ISL_SURF_DIM_1D)
266 assert(!isl_format_is_compressed(info->view->format));
267
268 if (isl_format_is_compressed(info->surf->format)) {
269 /* You're not allowed to make a view of a compressed format with any
270 * format other than the surface format. None of the userspace APIs
271 * allow for this directly and doing so would mess up a number of
272 * surface parameters such as Width, Height, and alignments. Ideally,
273 * we'd like to assert that the two formats match. However, we have an
274 * S3TC workaround that requires us to do reinterpretation. So assert
275 * that they're at least the same bpb and block size.
276 */
277 ASSERTED const struct isl_format_layout *surf_fmtl =
278 isl_format_get_layout(info->surf->format);
279 ASSERTED const struct isl_format_layout *view_fmtl =
280 isl_format_get_layout(info->surf->format);
281 assert(surf_fmtl->bpb == view_fmtl->bpb);
282 assert(surf_fmtl->bw == view_fmtl->bw);
283 assert(surf_fmtl->bh == view_fmtl->bh);
284 }
285
286 s.SurfaceFormat = info->view->format;
287
288 #if GEN_GEN >= 12
289 /* The BSpec description of this field says:
290 *
291 * "This bit field, when set, indicates if the resource is created as
292 * Depth/Stencil resource."
293 *
294 * "SW must set this bit for any resource that was created with
295 * Depth/Stencil resource flag. Setting this bit allows HW to properly
296 * interpret the data-layout for various cases. For any resource that's
297 * created without Depth/Stencil resource flag, it must be reset."
298 *
299 * Even though the docs for this bit seem to imply that it's required for
300 * anything which might have been used for depth/stencil, empirical
301 * evidence suggests that it only affects CCS compression usage. There are
302 * a few things which back this up:
303 *
304 * 1. The docs are also pretty clear that this bit was added as part
305 * of enabling Gen12 depth/stencil lossless compression.
306 *
307 * 2. The only new difference between depth/stencil and color images on
308 * Gen12 (where the bit was added) is how they treat CCS compression.
309 * All other differences such as alignment requirements and MSAA layout
310 * are already covered by other bits.
311 *
312 * Under these assumptions, it makes sense for ISL to model this bit as
313 * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT
314 * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource
315 * == true.
316 */
317 s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
318 info->aux_usage == ISL_AUX_USAGE_STC_CCS;
319 #endif
320
321 #if GEN_GEN <= 5
322 s.ColorBufferComponentWriteDisables = info->write_disables;
323 #else
324 assert(info->write_disables == 0);
325 #endif
326
327 #if GEN_IS_HASWELL
328 s.IntegerSurfaceFormat =
329 isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
330 #endif
331
332 assert(info->surf->logical_level0_px.width > 0 &&
333 info->surf->logical_level0_px.height > 0);
334
335 s.Width = info->surf->logical_level0_px.width - 1;
336 s.Height = info->surf->logical_level0_px.height - 1;
337
338 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
339 * (Surface Arrays For all surfaces other than separate stencil buffer):
340 *
341 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
342 * calculated in the equation above , for every other odd Surface Height
343 * starting from 1 i.e. 1,5,9,13"
344 *
345 * Since this Qpitch errata only impacts the sampler, we have to adjust the
346 * input for the rendering surface to achieve the same qpitch. For the
347 * affected heights, we increment the height by 1 for the rendering
348 * surface.
349 */
350 if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
351 info->surf->samples > 1 &&
352 (info->surf->logical_level0_px.height % 4) == 1)
353 s.Height++;
354
355 switch (s.SurfaceType) {
356 case SURFTYPE_1D:
357 case SURFTYPE_2D:
358 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
359 *
360 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
361 * must be set to zero if this surface is used with sampling engine
362 * messages."
363 *
364 * This restriction appears to exist only on Ivy Bridge.
365 */
366 if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
367 (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
368 info->surf->samples > 1)
369 assert(info->view->base_array_layer == 0);
370
371 s.MinimumArrayElement = info->view->base_array_layer;
372
373 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
374 *
375 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
376 * by one for each increase from zero of Minimum Array Element. For
377 * example, if Minimum Array Element is set to 1024 on a 2D surface,
378 * the range of this field is reduced to [0,1023].
379 *
380 * In other words, 'Depth' is the number of array layers.
381 */
382 s.Depth = info->view->array_len - 1;
383
384 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
385 *
386 * For Render Target and Typed Dataport 1D and 2D Surfaces:
387 * This field must be set to the same value as the Depth field.
388 */
389 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
390 ISL_SURF_USAGE_STORAGE_BIT))
391 s.RenderTargetViewExtent = s.Depth;
392 break;
393 case SURFTYPE_CUBE:
394 s.MinimumArrayElement = info->view->base_array_layer;
395 /* Same as SURFTYPE_2D, but divided by 6 */
396 s.Depth = info->view->array_len / 6 - 1;
397 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
398 ISL_SURF_USAGE_STORAGE_BIT))
399 s.RenderTargetViewExtent = s.Depth;
400 break;
401 case SURFTYPE_3D:
402 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
403 *
404 * If the volume texture is MIP-mapped, this field specifies the
405 * depth of the base MIP level.
406 */
407 s.Depth = info->surf->logical_level0_px.depth - 1;
408
409 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
410 *
411 * For Render Target and Typed Dataport 3D Surfaces: This field
412 * indicates the extent of the accessible 'R' coordinates minus 1 on
413 * the LOD currently being rendered to.
414 *
415 * The docs specify that this only matters for render targets and
416 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
417 * Depth field has more bits than RenderTargetViewExtent so we can have
418 * textures with more levels than we can render to. In order to prevent
419 * assert-failures in the packing function below, we only set the field
420 * when it's actually going to be used by the hardware.
421 *
422 * Similaraly, the MinimumArrayElement field is ignored by all hardware
423 * prior to Sky Lake when texturing and we want it set to 0 anyway.
424 * Since it's already initialized to 0, we can just leave it alone for
425 * texture surfaces.
426 */
427 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
428 ISL_SURF_USAGE_STORAGE_BIT)) {
429 s.MinimumArrayElement = info->view->base_array_layer;
430 s.RenderTargetViewExtent = info->view->array_len - 1;
431 }
432 break;
433 default:
434 unreachable("bad SurfaceType");
435 }
436
437 #if GEN_GEN >= 12
438 /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
439 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
440 info->view->array_len > 1;
441 #elif GEN_GEN >= 7
442 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
443 #endif
444
445 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
446 /* For render target surfaces, the hardware interprets field
447 * MIPCount/LOD as LOD. The Broadwell PRM says:
448 *
449 * MIPCountLOD defines the LOD that will be rendered into.
450 * SurfaceMinLOD is ignored.
451 */
452 s.MIPCountLOD = info->view->base_level;
453 s.SurfaceMinLOD = 0;
454 } else {
455 /* For non render target surfaces, the hardware interprets field
456 * MIPCount/LOD as MIPCount. The range of levels accessible by the
457 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
458 */
459 s.SurfaceMinLOD = info->view->base_level;
460 s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
461 }
462
463 #if GEN_GEN >= 9
464 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
465 * Start LOD" to 15 to prevent the hardware from trying to use them.
466 */
467 s.TiledResourceMode = NONE;
468 s.MipTailStartLOD = 15;
469 #endif
470
471 #if GEN_GEN >= 6
472 const struct isl_extent3d image_align = get_image_alignment(info->surf);
473 s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
474 #if GEN_GEN >= 7
475 s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
476 #endif
477 #endif
478
479 if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
480 /* For gen9 1-D textures, surface pitch is ignored */
481 s.SurfacePitch = 0;
482 } else {
483 s.SurfacePitch = info->surf->row_pitch_B - 1;
484 }
485
486 #if GEN_GEN >= 8
487 s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
488 #elif GEN_GEN == 7
489 s.SurfaceArraySpacing = info->surf->array_pitch_span ==
490 ISL_ARRAY_PITCH_SPAN_COMPACT;
491 #endif
492
493 #if GEN_GEN >= 8
494 assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
495 s.TileMode = isl_to_gen_tiling[info->surf->tiling];
496 #else
497 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
498 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
499 TILEWALK_XMAJOR,
500 #endif
501
502 #if GEN_GEN >= 8
503 s.RenderCacheReadWriteMode = WriteOnlyCache;
504 #else
505 s.RenderCacheReadWriteMode = 0;
506 #endif
507
508 #if GEN_GEN >= 11
509 /* We've seen dEQP failures when enabling this bit with UINT formats,
510 * which particularly affects blorp_copy() operations. It shouldn't
511 * have any effect on UINT textures anyway, so disable it for them.
512 */
513 s.EnableUnormPathInColorPipe =
514 !isl_format_has_int_channel(info->view->format);
515 #endif
516
517 s.CubeFaceEnablePositiveZ = 1;
518 s.CubeFaceEnableNegativeZ = 1;
519 s.CubeFaceEnablePositiveY = 1;
520 s.CubeFaceEnableNegativeY = 1;
521 s.CubeFaceEnablePositiveX = 1;
522 s.CubeFaceEnableNegativeX = 1;
523
524 #if GEN_GEN >= 6
525 s.NumberofMultisamples = ffs(info->surf->samples) - 1;
526 #if GEN_GEN >= 7
527 s.MultisampledSurfaceStorageFormat =
528 isl_to_gen_multisample_layout[info->surf->msaa_layout];
529 #endif
530 #endif
531
532 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
533 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
534 assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
535
536 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
537 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
538 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
539 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
540 #else
541 assert(isl_swizzle_is_identity(info->view->swizzle));
542 #endif
543
544 s.SurfaceBaseAddress = info->address;
545
546 #if GEN_GEN >= 6
547 s.MOCS = info->mocs;
548 #endif
549
550 #if GEN_GEN > 4 || GEN_IS_G4X
551 if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
552 /* There are fairly strict rules about when the offsets can be used.
553 * These are mostly taken from the Sky Lake PRM documentation for
554 * RENDER_SURFACE_STATE.
555 */
556 assert(info->surf->tiling != ISL_TILING_LINEAR);
557 assert(info->surf->dim == ISL_SURF_DIM_2D);
558 assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
559 assert(info->surf->levels == 1);
560 assert(info->surf->logical_level0_px.array_len == 1);
561 assert(info->aux_usage == ISL_AUX_USAGE_NONE);
562
563 if (GEN_GEN >= 8) {
564 /* Broadwell added more rules. */
565 assert(info->surf->samples == 1);
566 if (isl_format_get_layout(info->view->format)->bpb == 8)
567 assert(info->x_offset_sa % 16 == 0);
568 if (isl_format_get_layout(info->view->format)->bpb == 16)
569 assert(info->x_offset_sa % 8 == 0);
570 }
571
572 #if GEN_GEN >= 7
573 s.SurfaceArray = false;
574 #endif
575 }
576
577 const unsigned x_div = 4;
578 const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
579 assert(info->x_offset_sa % x_div == 0);
580 assert(info->y_offset_sa % y_div == 0);
581 s.XOffset = info->x_offset_sa / x_div;
582 s.YOffset = info->y_offset_sa / y_div;
583 #else
584 assert(info->x_offset_sa == 0);
585 assert(info->y_offset_sa == 0);
586 #endif
587
588 #if GEN_GEN >= 7
589 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
590 /* Check valid aux usages per-gen */
591 if (GEN_GEN >= 12) {
592 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
593 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
594 info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E ||
595 info->aux_usage == ISL_AUX_USAGE_MC ||
596 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
597 info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||
598 info->aux_usage == ISL_AUX_USAGE_STC_CCS);
599 } else if (GEN_GEN >= 9) {
600 assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
601 info->aux_usage == ISL_AUX_USAGE_MCS ||
602 info->aux_usage == ISL_AUX_USAGE_CCS_D ||
603 info->aux_usage == ISL_AUX_USAGE_CCS_E);
604 } else if (GEN_GEN >= 8) {
605 assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
606 info->aux_usage == ISL_AUX_USAGE_MCS ||
607 info->aux_usage == ISL_AUX_USAGE_CCS_D);
608 } else if (GEN_GEN >= 7) {
609 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
610 info->aux_usage == ISL_AUX_USAGE_CCS_D);
611 }
612
613 /* The docs don't appear to say anything whatsoever about compression
614 * and the data port. Testing seems to indicate that the data port
615 * completely ignores the AuxiliarySurfaceMode field.
616 *
617 * On gen12 HDC supports compression.
618 */
619 if (GEN_GEN < 12)
620 assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
621
622 if (isl_surf_usage_is_depth(info->surf->usage))
623 assert(isl_aux_usage_has_hiz(info->aux_usage));
624
625 if (isl_surf_usage_is_stencil(info->surf->usage))
626 assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
627
628 if (isl_aux_usage_has_hiz(info->aux_usage)) {
629 /* For Gen8-10, there are some restrictions around sampling from HiZ.
630 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
631 * say:
632 *
633 * "If this field is set to AUX_HIZ, Number of Multisamples must
634 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
635 *
636 * On Gen12, the docs are a bit less obvious but the restriction is
637 * the same. The limitation isn't called out explicitly but the docs
638 * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode
639 * say:
640 *
641 * "If Number of multisamples > 1, programming this value means
642 * MSAA compression is enabled for that surface. Auxillary surface
643 * is MSC with tile y."
644 *
645 * Since this interpretation ignores whether the surface is
646 * depth/stencil or not and since multisampled depth buffers use
647 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
648 * compression, this means that we can't even specify MSAA depth CCS
649 * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
650 */
651 assert(info->surf->samples == 1);
652
653 /* The dimension must not be 3D */
654 assert(info->surf->dim != ISL_SURF_DIM_3D);
655
656 /* The format must be one of the following: */
657 switch (info->view->format) {
658 case ISL_FORMAT_R32_FLOAT:
659 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
660 case ISL_FORMAT_R16_UNORM:
661 break;
662 default:
663 assert(!"Incompatible HiZ Sampling format");
664 break;
665 }
666 }
667
668 #if GEN_GEN >= 12
669 s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC;
670 #endif
671 #if GEN_GEN >= 8
672 s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
673 #else
674 s.MCSEnable = true;
675 #endif
676 }
677
678 /* The auxiliary buffer info is filled when it's useable by the HW.
679 *
680 * Starting with Gen12, the only form of compression that can be used
681 * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
682 * HiZ still requires a surface but the HiZ surface can only be
683 * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
684 *
685 * On all earlier hardware, an aux surface is required for all forms
686 * of compression.
687 */
688 if ((GEN_GEN < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) ||
689 (GEN_GEN >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) {
690
691 assert(info->aux_surf != NULL);
692
693 struct isl_tile_info tile_info;
694 isl_surf_get_tile_info(info->aux_surf, &tile_info);
695 uint32_t pitch_in_tiles =
696 info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
697
698 s.AuxiliarySurfaceBaseAddress = info->aux_address;
699 s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
700
701 #if GEN_GEN >= 8
702 /* Auxiliary surfaces in ISL have compressed formats but the hardware
703 * doesn't expect our definition of the compression, it expects qpitch
704 * in units of samples on the main surface.
705 */
706 s.AuxiliarySurfaceQPitch =
707 isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
708 #endif
709 }
710 #endif
711
712 #if GEN_GEN >= 8 && GEN_GEN < 11
713 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
714 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
715 *
716 * This bit must be set for the following surface types: BC2_UNORM
717 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
718 */
719 if (GEN_GEN >= 9 || dev->info->is_cherryview) {
720 switch (info->view->format) {
721 case ISL_FORMAT_BC2_UNORM:
722 case ISL_FORMAT_BC3_UNORM:
723 case ISL_FORMAT_BC5_UNORM:
724 case ISL_FORMAT_BC5_SNORM:
725 case ISL_FORMAT_BC7_UNORM:
726 s.SamplerL2BypassModeDisable = true;
727 break;
728 default:
729 /* From the SKL PRM, Programming Note under Sampler Output Channel
730 * Mapping:
731 *
732 * If a surface has an associated HiZ Auxilliary surface, the
733 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
734 * must be set.
735 */
736 if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
737 s.SamplerL2BypassModeDisable = true;
738 break;
739 }
740 }
741 #endif
742
743 if (isl_aux_usage_has_fast_clears(info->aux_usage)) {
744 if (info->use_clear_address) {
745 #if GEN_GEN >= 10
746 s.ClearValueAddressEnable = true;
747 s.ClearValueAddress = info->clear_address;
748 #else
749 unreachable("Gen9 and earlier do not support indirect clear colors");
750 #endif
751 }
752
753 #if GEN_GEN == 11
754 /*
755 * From BXML > GT > Shared Functions > vol5c Shared Functions >
756 * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
757 *
758 * Project: Gen11
759 *
760 * "Enables Pixel backend hw to convert clear values into native format
761 * and write back to clear address, so that display and sampler can use
762 * the converted value for resolving fast cleared RTs."
763 *
764 * Summary:
765 * Clear color conversion must be enabled if the clear color is stored
766 * indirectly and fast color clears are enabled.
767 */
768 if (info->use_clear_address) {
769 s.ClearColorConversionEnable = true;
770 }
771 #endif
772
773 #if GEN_GEN >= 12
774 assert(info->use_clear_address);
775 #elif GEN_GEN >= 9
776 if (!info->use_clear_address) {
777 s.RedClearColor = info->clear_color.u32[0];
778 s.GreenClearColor = info->clear_color.u32[1];
779 s.BlueClearColor = info->clear_color.u32[2];
780 s.AlphaClearColor = info->clear_color.u32[3];
781 }
782 #elif GEN_GEN >= 7
783 /* Prior to Sky Lake, we only have one bit for the clear color which
784 * gives us 0 or 1 in whatever the surface's format happens to be.
785 */
786 if (isl_format_has_int_channel(info->view->format)) {
787 for (unsigned i = 0; i < 4; i++) {
788 assert(info->clear_color.u32[i] == 0 ||
789 info->clear_color.u32[i] == 1);
790 }
791 s.RedClearColor = info->clear_color.u32[0] != 0;
792 s.GreenClearColor = info->clear_color.u32[1] != 0;
793 s.BlueClearColor = info->clear_color.u32[2] != 0;
794 s.AlphaClearColor = info->clear_color.u32[3] != 0;
795 } else {
796 for (unsigned i = 0; i < 4; i++) {
797 assert(info->clear_color.f32[i] == 0.0f ||
798 info->clear_color.f32[i] == 1.0f);
799 }
800 s.RedClearColor = info->clear_color.f32[0] != 0.0f;
801 s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
802 s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
803 s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
804 }
805 #endif
806 }
807
808 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
809 }
810
811 void
isl_genX(buffer_fill_state_s)812 isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
813 const struct isl_buffer_fill_state_info *restrict info)
814 {
815 uint64_t buffer_size = info->size_B;
816
817 /* Uniform and Storage buffers need to have surface size not less that the
818 * aligned 32-bit size of the buffer. To calculate the array lenght on
819 * unsized arrays in StorageBuffer the last 2 bits store the padding size
820 * added to the surface, so we can calculate latter the original buffer
821 * size to know the number of elements.
822 *
823 * surface_size = isl_align(buffer_size, 4) +
824 * (isl_align(buffer_size) - buffer_size)
825 *
826 * buffer_size = (surface_size & ~3) - (surface_size & 3)
827 */
828 if (info->format == ISL_FORMAT_RAW ||
829 info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
830 assert(info->stride_B == 1);
831 uint64_t aligned_size = isl_align(buffer_size, 4);
832 buffer_size = aligned_size + (aligned_size - buffer_size);
833 }
834
835 uint32_t num_elements = buffer_size / info->stride_B;
836
837 if (GEN_GEN >= 7) {
838 /* From the IVB PRM, SURFACE_STATE::Height,
839 *
840 * For typed buffer and structured buffer surfaces, the number
841 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
842 * surfaces, the number of entries in the buffer is the number of bytes
843 * which can range from 1 to 2^30.
844 */
845 if (info->format == ISL_FORMAT_RAW) {
846 assert(num_elements <= (1ull << 30));
847 assert(num_elements > 0);
848 } else {
849 assert(num_elements <= (1ull << 27));
850 }
851 } else {
852 assert(num_elements <= (1ull << 27));
853 }
854
855 struct GENX(RENDER_SURFACE_STATE) s = { 0, };
856
857 s.SurfaceType = SURFTYPE_BUFFER;
858 s.SurfaceFormat = info->format;
859
860 #if GEN_GEN >= 6
861 s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
862 #if GEN_GEN >= 7
863 s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
864 s.SurfaceArray = false;
865 #endif
866 #endif
867
868 #if GEN_GEN >= 7
869 s.Height = ((num_elements - 1) >> 7) & 0x3fff;
870 s.Width = (num_elements - 1) & 0x7f;
871 s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
872 #else
873 s.Height = ((num_elements - 1) >> 7) & 0x1fff;
874 s.Width = (num_elements - 1) & 0x7f;
875 s.Depth = ((num_elements - 1) >> 20) & 0x7f;
876 #endif
877
878 if (GEN_GEN == 12 && dev->info->revision == 0) {
879 /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
880 * textures with very close base addresses (delta < 64B) to corrupt each
881 * other. We can sort-of work around this by making small buffer
882 * textures 1D textures instead. This doesn't fix the problem for large
883 * buffer textures but the liklihood of large, overlapping, and very
884 * close buffer textures is fairly low and the point is to hack around
885 * the bug so we can run apps and tests.
886 */
887 if (info->format != ISL_FORMAT_RAW &&
888 info->stride_B == isl_format_get_layout(info->format)->bpb / 8 &&
889 num_elements <= (1 << 14)) {
890 s.SurfaceType = SURFTYPE_1D;
891 s.Width = num_elements - 1;
892 s.Height = 0;
893 s.Depth = 0;
894 }
895 }
896
897 s.SurfacePitch = info->stride_B - 1;
898
899 #if GEN_GEN >= 6
900 s.NumberofMultisamples = MULTISAMPLECOUNT_1;
901 #endif
902
903 #if (GEN_GEN >= 8)
904 s.TileMode = LINEAR;
905 #else
906 s.TiledSurface = false;
907 #endif
908
909 #if (GEN_GEN >= 8)
910 s.RenderCacheReadWriteMode = WriteOnlyCache;
911 #else
912 s.RenderCacheReadWriteMode = 0;
913 #endif
914
915 s.SurfaceBaseAddress = info->address;
916 #if GEN_GEN >= 6
917 s.MOCS = info->mocs;
918 #endif
919
920 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
921 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
922 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
923 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
924 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
925 #endif
926
927 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
928 }
929
930 void
isl_genX(null_fill_state)931 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
932 {
933 struct GENX(RENDER_SURFACE_STATE) s = {
934 .SurfaceType = SURFTYPE_NULL,
935 /* We previously had this format set to B8G8R8A8_UNORM but ran into
936 * hangs on IVB. R32_UINT seems to work for everybody.
937 *
938 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1872
939 */
940 .SurfaceFormat = ISL_FORMAT_R32_UINT,
941 #if GEN_GEN >= 7
942 .SurfaceArray = size.depth > 1,
943 #endif
944 #if GEN_GEN >= 8
945 .TileMode = YMAJOR,
946 #else
947 .TiledSurface = true,
948 .TileWalk = TILEWALK_YMAJOR,
949 #endif
950 #if GEN_GEN == 7
951 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
952 * Functions"
953 *
954 * RENDER_SURFACE_STATE::Surface Vertical Alignment
955 *
956 * "This field must be set to VALIGN_4 for all tiled Y Render Target
957 * surfaces."
958 *
959 * Affect IVB, HSW.
960 */
961 .SurfaceVerticalAlignment = VALIGN_4,
962 #endif
963 .Width = size.width - 1,
964 .Height = size.height - 1,
965 .Depth = size.depth - 1,
966 .RenderTargetViewExtent = size.depth - 1,
967 #if GEN_GEN <= 5
968 .ColorBufferComponentWriteDisables = 0xf,
969 #endif
970 };
971 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
972 }
973