1 //===-- RegisterInfos_arm64_sve.h -------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT 10 11 enum { 12 sve_fpsr = fpu_fpsr, 13 sve_fpcr = fpu_fpcr, 14 15 sve_vg = exc_far, 16 17 sve_z0, 18 sve_z1, 19 sve_z2, 20 sve_z3, 21 sve_z4, 22 sve_z5, 23 sve_z6, 24 sve_z7, 25 sve_z8, 26 sve_z9, 27 sve_z10, 28 sve_z11, 29 sve_z12, 30 sve_z13, 31 sve_z14, 32 sve_z15, 33 sve_z16, 34 sve_z17, 35 sve_z18, 36 sve_z19, 37 sve_z20, 38 sve_z21, 39 sve_z22, 40 sve_z23, 41 sve_z24, 42 sve_z25, 43 sve_z26, 44 sve_z27, 45 sve_z28, 46 sve_z29, 47 sve_z30, 48 sve_z31, 49 50 sve_p0, 51 sve_p1, 52 sve_p2, 53 sve_p3, 54 sve_p4, 55 sve_p5, 56 sve_p6, 57 sve_p7, 58 sve_p8, 59 sve_p9, 60 sve_p10, 61 sve_p11, 62 sve_p12, 63 sve_p13, 64 sve_p14, 65 sve_p15, 66 67 sve_ffr, 68 }; 69 70 #ifndef SVE_OFFSET_VG 71 #error SVE_OFFSET_VG must be defined before including this header file 72 #endif 73 74 static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0, 75 LLDB_INVALID_REGNUM}; 76 static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1, 77 LLDB_INVALID_REGNUM}; 78 static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2, 79 LLDB_INVALID_REGNUM}; 80 static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3, 81 LLDB_INVALID_REGNUM}; 82 static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4, 83 LLDB_INVALID_REGNUM}; 84 static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5, 85 LLDB_INVALID_REGNUM}; 86 static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6, 87 LLDB_INVALID_REGNUM}; 88 static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7, 89 LLDB_INVALID_REGNUM}; 90 static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8, 91 LLDB_INVALID_REGNUM}; 92 static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9, 93 LLDB_INVALID_REGNUM}; 94 static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10, 95 LLDB_INVALID_REGNUM}; 96 static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11, 97 LLDB_INVALID_REGNUM}; 98 static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12, 99 LLDB_INVALID_REGNUM}; 100 static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13, 101 LLDB_INVALID_REGNUM}; 102 static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14, 103 LLDB_INVALID_REGNUM}; 104 static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15, 105 LLDB_INVALID_REGNUM}; 106 static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16, 107 LLDB_INVALID_REGNUM}; 108 static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17, 109 LLDB_INVALID_REGNUM}; 110 static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18, 111 LLDB_INVALID_REGNUM}; 112 static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19, 113 LLDB_INVALID_REGNUM}; 114 static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20, 115 LLDB_INVALID_REGNUM}; 116 static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21, 117 LLDB_INVALID_REGNUM}; 118 static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22, 119 LLDB_INVALID_REGNUM}; 120 static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23, 121 LLDB_INVALID_REGNUM}; 122 static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24, 123 LLDB_INVALID_REGNUM}; 124 static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25, 125 LLDB_INVALID_REGNUM}; 126 static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26, 127 LLDB_INVALID_REGNUM}; 128 static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27, 129 LLDB_INVALID_REGNUM}; 130 static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28, 131 LLDB_INVALID_REGNUM}; 132 static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29, 133 LLDB_INVALID_REGNUM}; 134 static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30, 135 LLDB_INVALID_REGNUM}; 136 static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31, 137 LLDB_INVALID_REGNUM}; 138 139 static uint32_t g_sve_d0_invalidates[] = {sve_z0, fpu_v0, fpu_s0, 140 LLDB_INVALID_REGNUM}; 141 static uint32_t g_sve_d1_invalidates[] = {sve_z1, fpu_v1, fpu_s1, 142 LLDB_INVALID_REGNUM}; 143 static uint32_t g_sve_d2_invalidates[] = {sve_z2, fpu_v2, fpu_s2, 144 LLDB_INVALID_REGNUM}; 145 static uint32_t g_sve_d3_invalidates[] = {sve_z3, fpu_v3, fpu_s3, 146 LLDB_INVALID_REGNUM}; 147 static uint32_t g_sve_d4_invalidates[] = {sve_z4, fpu_v4, fpu_s4, 148 LLDB_INVALID_REGNUM}; 149 static uint32_t g_sve_d5_invalidates[] = {sve_z5, fpu_v5, fpu_s5, 150 LLDB_INVALID_REGNUM}; 151 static uint32_t g_sve_d6_invalidates[] = {sve_z6, fpu_v6, fpu_s6, 152 LLDB_INVALID_REGNUM}; 153 static uint32_t g_sve_d7_invalidates[] = {sve_z7, fpu_v7, fpu_s7, 154 LLDB_INVALID_REGNUM}; 155 static uint32_t g_sve_d8_invalidates[] = {sve_z8, fpu_v8, fpu_s8, 156 LLDB_INVALID_REGNUM}; 157 static uint32_t g_sve_d9_invalidates[] = {sve_z9, fpu_v9, fpu_s9, 158 LLDB_INVALID_REGNUM}; 159 static uint32_t g_sve_d10_invalidates[] = {sve_z10, fpu_v10, fpu_s10, 160 LLDB_INVALID_REGNUM}; 161 static uint32_t g_sve_d11_invalidates[] = {sve_z11, fpu_v11, fpu_s11, 162 LLDB_INVALID_REGNUM}; 163 static uint32_t g_sve_d12_invalidates[] = {sve_z12, fpu_v12, fpu_s12, 164 LLDB_INVALID_REGNUM}; 165 static uint32_t g_sve_d13_invalidates[] = {sve_z13, fpu_v13, fpu_s13, 166 LLDB_INVALID_REGNUM}; 167 static uint32_t g_sve_d14_invalidates[] = {sve_z14, fpu_v14, fpu_s14, 168 LLDB_INVALID_REGNUM}; 169 static uint32_t g_sve_d15_invalidates[] = {sve_z15, fpu_v15, fpu_s15, 170 LLDB_INVALID_REGNUM}; 171 static uint32_t g_sve_d16_invalidates[] = {sve_z16, fpu_v16, fpu_s16, 172 LLDB_INVALID_REGNUM}; 173 static uint32_t g_sve_d17_invalidates[] = {sve_z17, fpu_v17, fpu_s17, 174 LLDB_INVALID_REGNUM}; 175 static uint32_t g_sve_d18_invalidates[] = {sve_z18, fpu_v18, fpu_s18, 176 LLDB_INVALID_REGNUM}; 177 static uint32_t g_sve_d19_invalidates[] = {sve_z19, fpu_v19, fpu_s19, 178 LLDB_INVALID_REGNUM}; 179 static uint32_t g_sve_d20_invalidates[] = {sve_z20, fpu_v20, fpu_s20, 180 LLDB_INVALID_REGNUM}; 181 static uint32_t g_sve_d21_invalidates[] = {sve_z21, fpu_v21, fpu_s21, 182 LLDB_INVALID_REGNUM}; 183 static uint32_t g_sve_d22_invalidates[] = {sve_z22, fpu_v22, fpu_s22, 184 LLDB_INVALID_REGNUM}; 185 static uint32_t g_sve_d23_invalidates[] = {sve_z23, fpu_v23, fpu_s23, 186 LLDB_INVALID_REGNUM}; 187 static uint32_t g_sve_d24_invalidates[] = {sve_z24, fpu_v24, fpu_s24, 188 LLDB_INVALID_REGNUM}; 189 static uint32_t g_sve_d25_invalidates[] = {sve_z25, fpu_v25, fpu_s25, 190 LLDB_INVALID_REGNUM}; 191 static uint32_t g_sve_d26_invalidates[] = {sve_z26, fpu_v26, fpu_s26, 192 LLDB_INVALID_REGNUM}; 193 static uint32_t g_sve_d27_invalidates[] = {sve_z27, fpu_v27, fpu_s27, 194 LLDB_INVALID_REGNUM}; 195 static uint32_t g_sve_d28_invalidates[] = {sve_z28, fpu_v28, fpu_s28, 196 LLDB_INVALID_REGNUM}; 197 static uint32_t g_sve_d29_invalidates[] = {sve_z29, fpu_v29, fpu_s29, 198 LLDB_INVALID_REGNUM}; 199 static uint32_t g_sve_d30_invalidates[] = {sve_z30, fpu_v30, fpu_s30, 200 LLDB_INVALID_REGNUM}; 201 static uint32_t g_sve_d31_invalidates[] = {sve_z31, fpu_v31, fpu_s31, 202 LLDB_INVALID_REGNUM}; 203 204 static uint32_t g_sve_v0_invalidates[] = {sve_z0, fpu_d0, fpu_s0, 205 LLDB_INVALID_REGNUM}; 206 static uint32_t g_sve_v1_invalidates[] = {sve_z1, fpu_d1, fpu_s1, 207 LLDB_INVALID_REGNUM}; 208 static uint32_t g_sve_v2_invalidates[] = {sve_z2, fpu_d2, fpu_s2, 209 LLDB_INVALID_REGNUM}; 210 static uint32_t g_sve_v3_invalidates[] = {sve_z3, fpu_d3, fpu_s3, 211 LLDB_INVALID_REGNUM}; 212 static uint32_t g_sve_v4_invalidates[] = {sve_z4, fpu_d4, fpu_s4, 213 LLDB_INVALID_REGNUM}; 214 static uint32_t g_sve_v5_invalidates[] = {sve_z5, fpu_d5, fpu_s5, 215 LLDB_INVALID_REGNUM}; 216 static uint32_t g_sve_v6_invalidates[] = {sve_z6, fpu_d6, fpu_s6, 217 LLDB_INVALID_REGNUM}; 218 static uint32_t g_sve_v7_invalidates[] = {sve_z7, fpu_d7, fpu_s7, 219 LLDB_INVALID_REGNUM}; 220 static uint32_t g_sve_v8_invalidates[] = {sve_z8, fpu_d8, fpu_s8, 221 LLDB_INVALID_REGNUM}; 222 static uint32_t g_sve_v9_invalidates[] = {sve_z9, fpu_d9, fpu_s9, 223 LLDB_INVALID_REGNUM}; 224 static uint32_t g_sve_v10_invalidates[] = {sve_z10, fpu_d10, fpu_s10, 225 LLDB_INVALID_REGNUM}; 226 static uint32_t g_sve_v11_invalidates[] = {sve_z11, fpu_d11, fpu_s11, 227 LLDB_INVALID_REGNUM}; 228 static uint32_t g_sve_v12_invalidates[] = {sve_z12, fpu_d12, fpu_s12, 229 LLDB_INVALID_REGNUM}; 230 static uint32_t g_sve_v13_invalidates[] = {sve_z13, fpu_d13, fpu_s13, 231 LLDB_INVALID_REGNUM}; 232 static uint32_t g_sve_v14_invalidates[] = {sve_z14, fpu_d14, fpu_s14, 233 LLDB_INVALID_REGNUM}; 234 static uint32_t g_sve_v15_invalidates[] = {sve_z15, fpu_d15, fpu_s15, 235 LLDB_INVALID_REGNUM}; 236 static uint32_t g_sve_v16_invalidates[] = {sve_z16, fpu_d16, fpu_s16, 237 LLDB_INVALID_REGNUM}; 238 static uint32_t g_sve_v17_invalidates[] = {sve_z17, fpu_d17, fpu_s17, 239 LLDB_INVALID_REGNUM}; 240 static uint32_t g_sve_v18_invalidates[] = {sve_z18, fpu_d18, fpu_s18, 241 LLDB_INVALID_REGNUM}; 242 static uint32_t g_sve_v19_invalidates[] = {sve_z19, fpu_d19, fpu_s19, 243 LLDB_INVALID_REGNUM}; 244 static uint32_t g_sve_v20_invalidates[] = {sve_z20, fpu_d20, fpu_s20, 245 LLDB_INVALID_REGNUM}; 246 static uint32_t g_sve_v21_invalidates[] = {sve_z21, fpu_d21, fpu_s21, 247 LLDB_INVALID_REGNUM}; 248 static uint32_t g_sve_v22_invalidates[] = {sve_z22, fpu_d22, fpu_s22, 249 LLDB_INVALID_REGNUM}; 250 static uint32_t g_sve_v23_invalidates[] = {sve_z23, fpu_d23, fpu_s23, 251 LLDB_INVALID_REGNUM}; 252 static uint32_t g_sve_v24_invalidates[] = {sve_z24, fpu_d24, fpu_s24, 253 LLDB_INVALID_REGNUM}; 254 static uint32_t g_sve_v25_invalidates[] = {sve_z25, fpu_d25, fpu_s25, 255 LLDB_INVALID_REGNUM}; 256 static uint32_t g_sve_v26_invalidates[] = {sve_z26, fpu_d26, fpu_s26, 257 LLDB_INVALID_REGNUM}; 258 static uint32_t g_sve_v27_invalidates[] = {sve_z27, fpu_d27, fpu_s27, 259 LLDB_INVALID_REGNUM}; 260 static uint32_t g_sve_v28_invalidates[] = {sve_z28, fpu_d28, fpu_s28, 261 LLDB_INVALID_REGNUM}; 262 static uint32_t g_sve_v29_invalidates[] = {sve_z29, fpu_d29, fpu_s29, 263 LLDB_INVALID_REGNUM}; 264 static uint32_t g_sve_v30_invalidates[] = {sve_z30, fpu_d30, fpu_s30, 265 LLDB_INVALID_REGNUM}; 266 static uint32_t g_sve_v31_invalidates[] = {sve_z31, fpu_d31, fpu_s31, 267 LLDB_INVALID_REGNUM}; 268 269 static uint32_t g_contained_z0[] = {sve_z0, LLDB_INVALID_REGNUM}; 270 static uint32_t g_contained_z1[] = {sve_z1, LLDB_INVALID_REGNUM}; 271 static uint32_t g_contained_z2[] = {sve_z2, LLDB_INVALID_REGNUM}; 272 static uint32_t g_contained_z3[] = {sve_z3, LLDB_INVALID_REGNUM}; 273 static uint32_t g_contained_z4[] = {sve_z4, LLDB_INVALID_REGNUM}; 274 static uint32_t g_contained_z5[] = {sve_z5, LLDB_INVALID_REGNUM}; 275 static uint32_t g_contained_z6[] = {sve_z6, LLDB_INVALID_REGNUM}; 276 static uint32_t g_contained_z7[] = {sve_z7, LLDB_INVALID_REGNUM}; 277 static uint32_t g_contained_z8[] = {sve_z8, LLDB_INVALID_REGNUM}; 278 static uint32_t g_contained_z9[] = {sve_z9, LLDB_INVALID_REGNUM}; 279 static uint32_t g_contained_z10[] = {sve_z10, LLDB_INVALID_REGNUM}; 280 static uint32_t g_contained_z11[] = {sve_z11, LLDB_INVALID_REGNUM}; 281 static uint32_t g_contained_z12[] = {sve_z12, LLDB_INVALID_REGNUM}; 282 static uint32_t g_contained_z13[] = {sve_z13, LLDB_INVALID_REGNUM}; 283 static uint32_t g_contained_z14[] = {sve_z14, LLDB_INVALID_REGNUM}; 284 static uint32_t g_contained_z15[] = {sve_z15, LLDB_INVALID_REGNUM}; 285 static uint32_t g_contained_z16[] = {sve_z16, LLDB_INVALID_REGNUM}; 286 static uint32_t g_contained_z17[] = {sve_z17, LLDB_INVALID_REGNUM}; 287 static uint32_t g_contained_z18[] = {sve_z18, LLDB_INVALID_REGNUM}; 288 static uint32_t g_contained_z19[] = {sve_z19, LLDB_INVALID_REGNUM}; 289 static uint32_t g_contained_z20[] = {sve_z20, LLDB_INVALID_REGNUM}; 290 static uint32_t g_contained_z21[] = {sve_z21, LLDB_INVALID_REGNUM}; 291 static uint32_t g_contained_z22[] = {sve_z22, LLDB_INVALID_REGNUM}; 292 static uint32_t g_contained_z23[] = {sve_z23, LLDB_INVALID_REGNUM}; 293 static uint32_t g_contained_z24[] = {sve_z24, LLDB_INVALID_REGNUM}; 294 static uint32_t g_contained_z25[] = {sve_z25, LLDB_INVALID_REGNUM}; 295 static uint32_t g_contained_z26[] = {sve_z26, LLDB_INVALID_REGNUM}; 296 static uint32_t g_contained_z27[] = {sve_z27, LLDB_INVALID_REGNUM}; 297 static uint32_t g_contained_z28[] = {sve_z28, LLDB_INVALID_REGNUM}; 298 static uint32_t g_contained_z29[] = {sve_z29, LLDB_INVALID_REGNUM}; 299 static uint32_t g_contained_z30[] = {sve_z30, LLDB_INVALID_REGNUM}; 300 static uint32_t g_contained_z31[] = {sve_z31, LLDB_INVALID_REGNUM}; 301 302 #define VG_OFFSET_NAME(reg) SVE_OFFSET_VG 303 304 #define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM) 305 #define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM) 306 307 // Default offset SVE Z registers and all corresponding pseudo registers 308 // ( S, D and V registers) is zero and will be configured during execution. 309 310 // Defines sve pseudo vector (V) register with 16-byte size 311 #define DEFINE_VREG_SVE(vreg, zreg) \ 312 { \ 313 #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \ 314 VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \ 315 nullptr, 0 \ 316 } 317 318 // Defines S and D pseudo registers mapping over corresponding vector register 319 #define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \ 320 { \ 321 #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat, \ 322 LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \ 323 nullptr, 0 \ 324 } 325 326 // Defines a Z vector register with 16-byte default size 327 #define DEFINE_ZREG(reg) \ 328 { \ 329 #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \ 330 SVE_REG_KIND(reg), nullptr, nullptr, nullptr, 0 \ 331 } 332 333 // Defines a P vector register with 2-byte default size 334 #define DEFINE_PREG(reg) \ 335 { \ 336 #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \ 337 SVE_REG_KIND(reg), nullptr, nullptr, nullptr, 0 \ 338 } 339 340 static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = { 341 // clang-format off 342 // DEFINE_GPR64(name, GENERIC KIND) 343 DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1), 344 DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2), 345 DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3), 346 DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4), 347 DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5), 348 DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6), 349 DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7), 350 DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8), 351 DEFINE_GPR64(x8, LLDB_INVALID_REGNUM), 352 DEFINE_GPR64(x9, LLDB_INVALID_REGNUM), 353 DEFINE_GPR64(x10, LLDB_INVALID_REGNUM), 354 DEFINE_GPR64(x11, LLDB_INVALID_REGNUM), 355 DEFINE_GPR64(x12, LLDB_INVALID_REGNUM), 356 DEFINE_GPR64(x13, LLDB_INVALID_REGNUM), 357 DEFINE_GPR64(x14, LLDB_INVALID_REGNUM), 358 DEFINE_GPR64(x15, LLDB_INVALID_REGNUM), 359 DEFINE_GPR64(x16, LLDB_INVALID_REGNUM), 360 DEFINE_GPR64(x17, LLDB_INVALID_REGNUM), 361 DEFINE_GPR64(x18, LLDB_INVALID_REGNUM), 362 DEFINE_GPR64(x19, LLDB_INVALID_REGNUM), 363 DEFINE_GPR64(x20, LLDB_INVALID_REGNUM), 364 DEFINE_GPR64(x21, LLDB_INVALID_REGNUM), 365 DEFINE_GPR64(x22, LLDB_INVALID_REGNUM), 366 DEFINE_GPR64(x23, LLDB_INVALID_REGNUM), 367 DEFINE_GPR64(x24, LLDB_INVALID_REGNUM), 368 DEFINE_GPR64(x25, LLDB_INVALID_REGNUM), 369 DEFINE_GPR64(x26, LLDB_INVALID_REGNUM), 370 DEFINE_GPR64(x27, LLDB_INVALID_REGNUM), 371 DEFINE_GPR64(x28, LLDB_INVALID_REGNUM), 372 // DEFINE_GPR64(name, GENERIC KIND) 373 DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP), 374 DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA), 375 DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP), 376 DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC), 377 378 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind) 379 DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr), 380 381 // DEFINE_GPR32(name, parent name) 382 DEFINE_GPR32(w0, x0), 383 DEFINE_GPR32(w1, x1), 384 DEFINE_GPR32(w2, x2), 385 DEFINE_GPR32(w3, x3), 386 DEFINE_GPR32(w4, x4), 387 DEFINE_GPR32(w5, x5), 388 DEFINE_GPR32(w6, x6), 389 DEFINE_GPR32(w7, x7), 390 DEFINE_GPR32(w8, x8), 391 DEFINE_GPR32(w9, x9), 392 DEFINE_GPR32(w10, x10), 393 DEFINE_GPR32(w11, x11), 394 DEFINE_GPR32(w12, x12), 395 DEFINE_GPR32(w13, x13), 396 DEFINE_GPR32(w14, x14), 397 DEFINE_GPR32(w15, x15), 398 DEFINE_GPR32(w16, x16), 399 DEFINE_GPR32(w17, x17), 400 DEFINE_GPR32(w18, x18), 401 DEFINE_GPR32(w19, x19), 402 DEFINE_GPR32(w20, x20), 403 DEFINE_GPR32(w21, x21), 404 DEFINE_GPR32(w22, x22), 405 DEFINE_GPR32(w23, x23), 406 DEFINE_GPR32(w24, x24), 407 DEFINE_GPR32(w25, x25), 408 DEFINE_GPR32(w26, x26), 409 DEFINE_GPR32(w27, x27), 410 DEFINE_GPR32(w28, x28), 411 412 // DEFINE_VREG_SVE(v register, z register) 413 DEFINE_VREG_SVE(v0, z0), 414 DEFINE_VREG_SVE(v1, z1), 415 DEFINE_VREG_SVE(v2, z2), 416 DEFINE_VREG_SVE(v3, z3), 417 DEFINE_VREG_SVE(v4, z4), 418 DEFINE_VREG_SVE(v5, z5), 419 DEFINE_VREG_SVE(v6, z6), 420 DEFINE_VREG_SVE(v7, z7), 421 DEFINE_VREG_SVE(v8, z8), 422 DEFINE_VREG_SVE(v9, z9), 423 DEFINE_VREG_SVE(v10, z10), 424 DEFINE_VREG_SVE(v11, z11), 425 DEFINE_VREG_SVE(v12, z12), 426 DEFINE_VREG_SVE(v13, z13), 427 DEFINE_VREG_SVE(v14, z14), 428 DEFINE_VREG_SVE(v15, z15), 429 DEFINE_VREG_SVE(v16, z16), 430 DEFINE_VREG_SVE(v17, z17), 431 DEFINE_VREG_SVE(v18, z18), 432 DEFINE_VREG_SVE(v19, z19), 433 DEFINE_VREG_SVE(v20, z20), 434 DEFINE_VREG_SVE(v21, z21), 435 DEFINE_VREG_SVE(v22, z22), 436 DEFINE_VREG_SVE(v23, z23), 437 DEFINE_VREG_SVE(v24, z24), 438 DEFINE_VREG_SVE(v25, z25), 439 DEFINE_VREG_SVE(v26, z26), 440 DEFINE_VREG_SVE(v27, z27), 441 DEFINE_VREG_SVE(v28, z28), 442 DEFINE_VREG_SVE(v29, z29), 443 DEFINE_VREG_SVE(v30, z30), 444 DEFINE_VREG_SVE(v31, z31), 445 446 // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register) 447 DEFINE_FPU_PSEUDO_SVE(s0, 4, z0), 448 DEFINE_FPU_PSEUDO_SVE(s1, 4, z1), 449 DEFINE_FPU_PSEUDO_SVE(s2, 4, z2), 450 DEFINE_FPU_PSEUDO_SVE(s3, 4, z3), 451 DEFINE_FPU_PSEUDO_SVE(s4, 4, z4), 452 DEFINE_FPU_PSEUDO_SVE(s5, 4, z5), 453 DEFINE_FPU_PSEUDO_SVE(s6, 4, z6), 454 DEFINE_FPU_PSEUDO_SVE(s7, 4, z7), 455 DEFINE_FPU_PSEUDO_SVE(s8, 4, z8), 456 DEFINE_FPU_PSEUDO_SVE(s9, 4, z9), 457 DEFINE_FPU_PSEUDO_SVE(s10, 4, z10), 458 DEFINE_FPU_PSEUDO_SVE(s11, 4, z11), 459 DEFINE_FPU_PSEUDO_SVE(s12, 4, z12), 460 DEFINE_FPU_PSEUDO_SVE(s13, 4, z13), 461 DEFINE_FPU_PSEUDO_SVE(s14, 4, z14), 462 DEFINE_FPU_PSEUDO_SVE(s15, 4, z15), 463 DEFINE_FPU_PSEUDO_SVE(s16, 4, z16), 464 DEFINE_FPU_PSEUDO_SVE(s17, 4, z17), 465 DEFINE_FPU_PSEUDO_SVE(s18, 4, z18), 466 DEFINE_FPU_PSEUDO_SVE(s19, 4, z19), 467 DEFINE_FPU_PSEUDO_SVE(s20, 4, z20), 468 DEFINE_FPU_PSEUDO_SVE(s21, 4, z21), 469 DEFINE_FPU_PSEUDO_SVE(s22, 4, z22), 470 DEFINE_FPU_PSEUDO_SVE(s23, 4, z23), 471 DEFINE_FPU_PSEUDO_SVE(s24, 4, z24), 472 DEFINE_FPU_PSEUDO_SVE(s25, 4, z25), 473 DEFINE_FPU_PSEUDO_SVE(s26, 4, z26), 474 DEFINE_FPU_PSEUDO_SVE(s27, 4, z27), 475 DEFINE_FPU_PSEUDO_SVE(s28, 4, z28), 476 DEFINE_FPU_PSEUDO_SVE(s29, 4, z29), 477 DEFINE_FPU_PSEUDO_SVE(s30, 4, z30), 478 DEFINE_FPU_PSEUDO_SVE(s31, 4, z31), 479 480 DEFINE_FPU_PSEUDO_SVE(d0, 8, z0), 481 DEFINE_FPU_PSEUDO_SVE(d1, 8, z1), 482 DEFINE_FPU_PSEUDO_SVE(d2, 8, z2), 483 DEFINE_FPU_PSEUDO_SVE(d3, 8, z3), 484 DEFINE_FPU_PSEUDO_SVE(d4, 8, z4), 485 DEFINE_FPU_PSEUDO_SVE(d5, 8, z5), 486 DEFINE_FPU_PSEUDO_SVE(d6, 8, z6), 487 DEFINE_FPU_PSEUDO_SVE(d7, 8, z7), 488 DEFINE_FPU_PSEUDO_SVE(d8, 8, z8), 489 DEFINE_FPU_PSEUDO_SVE(d9, 8, z9), 490 DEFINE_FPU_PSEUDO_SVE(d10, 8, z10), 491 DEFINE_FPU_PSEUDO_SVE(d11, 8, z11), 492 DEFINE_FPU_PSEUDO_SVE(d12, 8, z12), 493 DEFINE_FPU_PSEUDO_SVE(d13, 8, z13), 494 DEFINE_FPU_PSEUDO_SVE(d14, 8, z14), 495 DEFINE_FPU_PSEUDO_SVE(d15, 8, z15), 496 DEFINE_FPU_PSEUDO_SVE(d16, 8, z16), 497 DEFINE_FPU_PSEUDO_SVE(d17, 8, z17), 498 DEFINE_FPU_PSEUDO_SVE(d18, 8, z18), 499 DEFINE_FPU_PSEUDO_SVE(d19, 8, z19), 500 DEFINE_FPU_PSEUDO_SVE(d20, 8, z20), 501 DEFINE_FPU_PSEUDO_SVE(d21, 8, z21), 502 DEFINE_FPU_PSEUDO_SVE(d22, 8, z22), 503 DEFINE_FPU_PSEUDO_SVE(d23, 8, z23), 504 DEFINE_FPU_PSEUDO_SVE(d24, 8, z24), 505 DEFINE_FPU_PSEUDO_SVE(d25, 8, z25), 506 DEFINE_FPU_PSEUDO_SVE(d26, 8, z26), 507 DEFINE_FPU_PSEUDO_SVE(d27, 8, z27), 508 DEFINE_FPU_PSEUDO_SVE(d28, 8, z28), 509 DEFINE_FPU_PSEUDO_SVE(d29, 8, z29), 510 DEFINE_FPU_PSEUDO_SVE(d30, 8, z30), 511 DEFINE_FPU_PSEUDO_SVE(d31, 8, z31), 512 513 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind) 514 DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr), 515 DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr), 516 517 DEFINE_MISC_REGS(vg, 8, VG, sve_vg), 518 // DEFINE_ZREG(name) 519 DEFINE_ZREG(z0), 520 DEFINE_ZREG(z1), 521 DEFINE_ZREG(z2), 522 DEFINE_ZREG(z3), 523 DEFINE_ZREG(z4), 524 DEFINE_ZREG(z5), 525 DEFINE_ZREG(z6), 526 DEFINE_ZREG(z7), 527 DEFINE_ZREG(z8), 528 DEFINE_ZREG(z9), 529 DEFINE_ZREG(z10), 530 DEFINE_ZREG(z11), 531 DEFINE_ZREG(z12), 532 DEFINE_ZREG(z13), 533 DEFINE_ZREG(z14), 534 DEFINE_ZREG(z15), 535 DEFINE_ZREG(z16), 536 DEFINE_ZREG(z17), 537 DEFINE_ZREG(z18), 538 DEFINE_ZREG(z19), 539 DEFINE_ZREG(z20), 540 DEFINE_ZREG(z21), 541 DEFINE_ZREG(z22), 542 DEFINE_ZREG(z23), 543 DEFINE_ZREG(z24), 544 DEFINE_ZREG(z25), 545 DEFINE_ZREG(z26), 546 DEFINE_ZREG(z27), 547 DEFINE_ZREG(z28), 548 DEFINE_ZREG(z29), 549 DEFINE_ZREG(z30), 550 DEFINE_ZREG(z31), 551 552 // DEFINE_PREG(name) 553 DEFINE_PREG(p0), 554 DEFINE_PREG(p1), 555 DEFINE_PREG(p2), 556 DEFINE_PREG(p3), 557 DEFINE_PREG(p4), 558 DEFINE_PREG(p5), 559 DEFINE_PREG(p6), 560 DEFINE_PREG(p7), 561 DEFINE_PREG(p8), 562 DEFINE_PREG(p9), 563 DEFINE_PREG(p10), 564 DEFINE_PREG(p11), 565 DEFINE_PREG(p12), 566 DEFINE_PREG(p13), 567 DEFINE_PREG(p14), 568 DEFINE_PREG(p15), 569 570 // DEFINE FFR 571 DEFINE_PREG(ffr) 572 // clang-format on 573 }; 574 575 #endif // DECLARE_REGISTER_INFOS_ARM64_SVE_STRUCT 576