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1 /*
2  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Rob Clark <robclark@freedesktop.org>
25  */
26 
27 #ifndef IR3_COMPILER_H_
28 #define IR3_COMPILER_H_
29 
30 #include "util/disk_cache.h"
31 
32 #include "ir3.h"
33 
34 struct ir3_ra_reg_set;
35 struct ir3_shader;
36 
37 struct ir3_compiler {
38 	struct fd_device *dev;
39 	uint32_t gpu_id;
40 	struct ir3_ra_reg_set *set;
41 	struct ir3_ra_reg_set *mergedregs_set;
42 	uint32_t shader_count;
43 
44 	struct disk_cache *disk_cache;
45 
46 	/*
47 	 * Configuration options for things that are handled differently on
48 	 * different generations:
49 	 */
50 
51 	/* a4xx (and later) drops SP_FS_FLAT_SHAD_MODE_REG_* for flat-interpolate
52 	 * so we need to use ldlv.u32 to load the varying directly:
53 	 */
54 	bool flat_bypass;
55 
56 	/* on a3xx, we need to add one to # of array levels:
57 	 */
58 	bool levels_add_one;
59 
60 	/* on a3xx, we need to scale up integer coords for isaml based
61 	 * on LoD:
62 	 */
63 	bool unminify_coords;
64 
65 	/* on a3xx do txf_ms w/ isaml and scaled coords: */
66 	bool txf_ms_with_isaml;
67 
68 	/* on a4xx, for array textures we need to add 0.5 to the array
69 	 * index coordinate:
70 	 */
71 	bool array_index_add_half;
72 
73 	/* on a6xx, rewrite samgp to sequence of samgq0-3 in vertex shaders:
74 	 */
75 	bool samgq_workaround;
76 
77 	/* on a650, vertex shader <-> tess control io uses LDL/STL */
78 	bool tess_use_shared;
79 
80 	/* The maximum number of constants, in vec4's, across the entire graphics
81 	 * pipeline.
82 	 */
83 	uint16_t max_const_pipeline;
84 
85 	/* The maximum number of constants, in vec4's, for VS+HS+DS+GS. */
86 	uint16_t max_const_geom;
87 
88 	/* The maximum number of constants, in vec4's, for FS. */
89 	uint16_t max_const_frag;
90 
91 	/* A "safe" max constlen that can be applied to each shader in the
92 	 * pipeline which we guarantee will never exceed any combined limits.
93 	 */
94 	uint16_t max_const_safe;
95 
96 	/* The maximum number of constants, in vec4's, for compute shaders. */
97 	uint16_t max_const_compute;
98 
99 	/* Number of instructions that the shader's base address and length
100 	 * (instrlen divides instruction count by this) must be aligned to.
101 	 */
102 	uint32_t instr_align;
103 
104 	/* on a3xx, the unit of indirect const load is higher than later gens (in
105 	 * vec4 units):
106 	 */
107 	uint32_t const_upload_unit;
108 
109 	/* Whether clip+cull distances are supported */
110 	bool has_clip_cull;
111 };
112 
113 void ir3_compiler_destroy(struct ir3_compiler *compiler);
114 struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id);
115 
116 void ir3_disk_cache_init(struct ir3_compiler *compiler);
117 void ir3_disk_cache_init_shader_key(struct ir3_compiler *compiler,
118 		struct ir3_shader *shader);
119 bool ir3_disk_cache_retrieve(struct ir3_compiler *compiler,
120 		struct ir3_shader_variant *v);
121 void ir3_disk_cache_store(struct ir3_compiler *compiler,
122 		struct ir3_shader_variant *v);
123 
124 int ir3_compile_shader_nir(struct ir3_compiler *compiler,
125 		struct ir3_shader_variant *so);
126 
127 /* gpu pointer size in units of 32bit registers/slots */
128 static inline
ir3_pointer_size(struct ir3_compiler * compiler)129 unsigned ir3_pointer_size(struct ir3_compiler *compiler)
130 {
131 	return (compiler->gpu_id >= 500) ? 2 : 1;
132 }
133 
134 enum ir3_shader_debug {
135 	IR3_DBG_SHADER_VS  = BITFIELD_BIT(0),
136 	IR3_DBG_SHADER_TCS = BITFIELD_BIT(1),
137 	IR3_DBG_SHADER_TES = BITFIELD_BIT(2),
138 	IR3_DBG_SHADER_GS  = BITFIELD_BIT(3),
139 	IR3_DBG_SHADER_FS  = BITFIELD_BIT(4),
140 	IR3_DBG_SHADER_CS  = BITFIELD_BIT(5),
141 	IR3_DBG_DISASM     = BITFIELD_BIT(6),
142 	IR3_DBG_OPTMSGS    = BITFIELD_BIT(7),
143 	IR3_DBG_FORCES2EN  = BITFIELD_BIT(8),
144 	IR3_DBG_NOUBOOPT   = BITFIELD_BIT(9),
145 	IR3_DBG_NOFP16     = BITFIELD_BIT(10),
146 	IR3_DBG_NOCACHE    = BITFIELD_BIT(11),
147 
148 	/* DEBUG-only options: */
149 	IR3_DBG_SCHEDMSGS  = BITFIELD_BIT(20),
150 	IR3_DBG_RAMSGS     = BITFIELD_BIT(21),
151 };
152 
153 extern enum ir3_shader_debug ir3_shader_debug;
154 
155 static inline bool
shader_debug_enabled(gl_shader_stage type)156 shader_debug_enabled(gl_shader_stage type)
157 {
158 	if (ir3_shader_debug & IR3_DBG_DISASM)
159 		return true;
160 
161 	switch (type) {
162 	case MESA_SHADER_VERTEX:      return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
163 	case MESA_SHADER_TESS_CTRL:   return !!(ir3_shader_debug & IR3_DBG_SHADER_TCS);
164 	case MESA_SHADER_TESS_EVAL:   return !!(ir3_shader_debug & IR3_DBG_SHADER_TES);
165 	case MESA_SHADER_GEOMETRY:    return !!(ir3_shader_debug & IR3_DBG_SHADER_GS);
166 	case MESA_SHADER_FRAGMENT:    return !!(ir3_shader_debug & IR3_DBG_SHADER_FS);
167 	case MESA_SHADER_COMPUTE:     return !!(ir3_shader_debug & IR3_DBG_SHADER_CS);
168 	default:
169 		debug_assert(0);
170 		return false;
171 	}
172 }
173 
174 static inline void
ir3_debug_print(struct ir3 * ir,const char * when)175 ir3_debug_print(struct ir3 *ir, const char *when)
176 {
177 	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
178 		printf("%s:\n", when);
179 		ir3_print(ir);
180 	}
181 }
182 
183 #endif /* IR3_COMPILER_H_ */
184