1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #ifndef VC4_CONTEXT_H
26 #define VC4_CONTEXT_H
27
28 #include <stdio.h>
29
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/slab.h"
33 #include "xf86drm.h"
34
35 #define __user
36 #include "drm-uapi/vc4_drm.h"
37 #include "vc4_bufmgr.h"
38 #include "vc4_resource.h"
39 #include "vc4_cl.h"
40 #include "vc4_qir.h"
41
42 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
43 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4
44 #endif
45 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
46 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
47 #endif
48
49 #ifdef USE_VC4_SIMULATOR
50 #define using_vc4_simulator true
51 #else
52 #define using_vc4_simulator false
53 #endif
54
55 #define VC4_DIRTY_BLEND (1 << 0)
56 #define VC4_DIRTY_RASTERIZER (1 << 1)
57 #define VC4_DIRTY_ZSA (1 << 2)
58 #define VC4_DIRTY_FRAGTEX (1 << 3)
59 #define VC4_DIRTY_VERTTEX (1 << 4)
60
61 #define VC4_DIRTY_BLEND_COLOR (1 << 7)
62 #define VC4_DIRTY_STENCIL_REF (1 << 8)
63 #define VC4_DIRTY_SAMPLE_MASK (1 << 9)
64 #define VC4_DIRTY_FRAMEBUFFER (1 << 10)
65 #define VC4_DIRTY_STIPPLE (1 << 11)
66 #define VC4_DIRTY_VIEWPORT (1 << 12)
67 #define VC4_DIRTY_CONSTBUF (1 << 13)
68 #define VC4_DIRTY_VTXSTATE (1 << 14)
69 #define VC4_DIRTY_VTXBUF (1 << 15)
70
71 #define VC4_DIRTY_SCISSOR (1 << 17)
72 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
73 #define VC4_DIRTY_PRIM_MODE (1 << 19)
74 #define VC4_DIRTY_CLIP (1 << 20)
75 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
76 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
77 #define VC4_DIRTY_COMPILED_CS (1 << 23)
78 #define VC4_DIRTY_COMPILED_VS (1 << 24)
79 #define VC4_DIRTY_COMPILED_FS (1 << 25)
80 #define VC4_DIRTY_FS_INPUTS (1 << 26)
81 #define VC4_DIRTY_UBO_1_SIZE (1 << 27)
82
83 struct vc4_sampler_view {
84 struct pipe_sampler_view base;
85 uint32_t texture_p0;
86 uint32_t texture_p1;
87 bool force_first_level;
88 /**
89 * Resource containing the actual texture that will be sampled.
90 *
91 * We may need to rebase the .base.texture resource to work around the
92 * lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled.
93 */
94 struct pipe_resource *texture;
95 };
96
97 struct vc4_sampler_state {
98 struct pipe_sampler_state base;
99 uint32_t texture_p1;
100 };
101
102 struct vc4_texture_stateobj {
103 struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
104 unsigned num_textures;
105 struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
106 unsigned num_samplers;
107 };
108
109 struct vc4_shader_uniform_info {
110 enum quniform_contents *contents;
111 uint32_t *data;
112 uint32_t count;
113 uint32_t num_texture_samples;
114 };
115
116 struct vc4_uncompiled_shader {
117 /** A name for this program, so you can track it in shader-db output. */
118 uint32_t program_id;
119 /** How many variants of this program were compiled, for shader-db. */
120 uint32_t compiled_variant_count;
121 struct pipe_shader_state base;
122 };
123
124 struct vc4_fs_inputs {
125 /**
126 * Array of the meanings of the VPM inputs this shader needs.
127 *
128 * It doesn't include those that aren't part of the VPM, like
129 * point/line coordinates.
130 */
131 struct vc4_varying_slot *input_slots;
132 uint32_t num_inputs;
133 };
134
135 struct vc4_compiled_shader {
136 uint64_t program_id;
137 struct vc4_bo *bo;
138
139 struct vc4_shader_uniform_info uniforms;
140
141 /**
142 * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
143 * uniforms have to be rewritten (and therefore the shader state
144 * reemitted).
145 */
146 uint32_t uniform_dirty_bits;
147
148 /** bitmask of which inputs are color inputs, for flat shade handling. */
149 uint32_t color_inputs;
150
151 bool disable_early_z;
152
153 /* Set if the compile failed, likely due to register allocation
154 * failure. In this case, we have no shader to run and should not try
155 * to do any draws.
156 */
157 bool failed;
158
159 bool fs_threaded;
160
161 uint8_t num_inputs;
162
163 /* Byte offsets for the start of the vertex attributes 0-7, and the
164 * total size as "attribute" 8.
165 */
166 uint8_t vattr_offsets[9];
167 uint8_t vattrs_live;
168
169 const struct vc4_fs_inputs *fs_inputs;
170 };
171
172 struct vc4_program_stateobj {
173 struct vc4_uncompiled_shader *bind_vs, *bind_fs;
174 struct vc4_compiled_shader *cs, *vs, *fs;
175 };
176
177 struct vc4_constbuf_stateobj {
178 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
179 uint32_t enabled_mask;
180 uint32_t dirty_mask;
181 };
182
183 struct vc4_vertexbuf_stateobj {
184 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
185 unsigned count;
186 uint32_t enabled_mask;
187 uint32_t dirty_mask;
188 };
189
190 struct vc4_vertex_stateobj {
191 struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
192 unsigned num_elements;
193 };
194
195 /* Hash table key for vc4->jobs */
196 struct vc4_job_key {
197 struct pipe_surface *cbuf;
198 struct pipe_surface *zsbuf;
199 };
200
201 struct vc4_hwperfmon {
202 uint32_t id;
203 uint64_t last_seqno;
204 uint8_t events[DRM_VC4_MAX_PERF_COUNTERS];
205 uint64_t counters[DRM_VC4_MAX_PERF_COUNTERS];
206 };
207
208 /**
209 * A complete bin/render job.
210 *
211 * This is all of the state necessary to submit a bin/render to the kernel.
212 * We want to be able to have multiple in progress at a time, so that we don't
213 * need to flush an existing CL just to switch to rendering to a new render
214 * target (which would mean reading back from the old render target when
215 * starting to render to it again).
216 */
217 struct vc4_job {
218 struct vc4_cl bcl;
219 struct vc4_cl shader_rec;
220 struct vc4_cl uniforms;
221 struct vc4_cl bo_handles;
222 struct vc4_cl bo_pointers;
223 uint32_t shader_rec_count;
224 /**
225 * Amount of memory used by the BOs in bo_pointers.
226 *
227 * Used for checking when we should flush the job early so we don't
228 * OOM.
229 */
230 uint32_t bo_space;
231
232 /* Last BO hindex referenced from VC4_PACKET_GEM_HANDLES. */
233 uint32_t last_gem_handle_hindex;
234
235 /** @{ Surfaces to submit rendering for. */
236 struct pipe_surface *color_read;
237 struct pipe_surface *color_write;
238 struct pipe_surface *zs_read;
239 struct pipe_surface *zs_write;
240 struct pipe_surface *msaa_color_write;
241 struct pipe_surface *msaa_zs_write;
242 /** @} */
243 /** @{
244 * Bounding box of the scissor across all queued drawing.
245 *
246 * Note that the max values are exclusive.
247 */
248 uint32_t draw_min_x;
249 uint32_t draw_min_y;
250 uint32_t draw_max_x;
251 uint32_t draw_max_y;
252 /** @} */
253 /** @{
254 * Width/height of the color framebuffer being rendered to,
255 * for VC4_TILE_RENDERING_MODE_CONFIG.
256 */
257 uint32_t draw_width;
258 uint32_t draw_height;
259 /** @} */
260 /** @{ Tile information, depending on MSAA and float color buffer. */
261 uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
262 uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
263
264 uint32_t tile_width; /** @< Width of a tile. */
265 uint32_t tile_height; /** @< Height of a tile. */
266 /** Whether the current rendering is in a 4X MSAA tile buffer. */
267 bool msaa;
268 /** @} */
269
270 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
271 * first rendering.
272 */
273 uint32_t cleared;
274 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
275 * (either clears or draws).
276 */
277 uint32_t resolve;
278 uint32_t clear_color[2];
279 uint32_t clear_depth; /**< 24-bit unorm depth */
280 uint8_t clear_stencil;
281
282 /**
283 * Set if some drawing (triangles, blits, or just a glClear()) has
284 * been done to the FBO, meaning that we need to
285 * DRM_IOCTL_VC4_SUBMIT_CL.
286 */
287 bool needs_flush;
288
289 /**
290 * Number of draw calls (not counting full buffer clears) queued in
291 * the current job.
292 */
293 uint32_t draw_calls_queued;
294
295 /** Any flags to be passed in drm_vc4_submit_cl.flags. */
296 uint32_t flags;
297
298 /* Performance monitor attached to this job. */
299 struct vc4_hwperfmon *perfmon;
300
301 struct vc4_job_key key;
302 };
303
304 struct vc4_context {
305 struct pipe_context base;
306
307 int fd;
308 struct vc4_screen *screen;
309
310 /** The 3D rendering job for the currently bound FBO. */
311 struct vc4_job *job;
312
313 /* Map from struct vc4_job_key to the job for that FBO.
314 */
315 struct hash_table *jobs;
316
317 /**
318 * Map from vc4_resource to a job writing to that resource.
319 *
320 * Primarily for flushing jobs rendering to textures that are now
321 * being read from.
322 */
323 struct hash_table *write_jobs;
324
325 struct slab_child_pool transfer_pool;
326 struct blitter_context *blitter;
327
328 /** bitfield of VC4_DIRTY_* */
329 uint32_t dirty;
330
331 struct primconvert_context *primconvert;
332
333 struct hash_table *fs_cache, *vs_cache;
334 struct set *fs_inputs_set;
335 uint32_t next_uncompiled_program_id;
336 uint64_t next_compiled_program_id;
337
338 struct ra_regs *regs;
339 unsigned int reg_class_any[2];
340 unsigned int reg_class_a_or_b[2];
341 unsigned int reg_class_a_or_b_or_acc[2];
342 unsigned int reg_class_r0_r3;
343 unsigned int reg_class_r4_or_a[2];
344 unsigned int reg_class_a[2];
345
346 uint8_t prim_mode;
347
348 /** Maximum index buffer valid for the current shader_rec. */
349 uint32_t max_index;
350 /** Last index bias baked into the current shader_rec. */
351 uint32_t last_index_bias;
352
353 /** Seqno of the last CL flush's job. */
354 uint64_t last_emit_seqno;
355
356 struct u_upload_mgr *uploader;
357
358 struct pipe_shader_state *yuv_linear_blit_vs;
359 struct pipe_shader_state *yuv_linear_blit_fs_8bit;
360 struct pipe_shader_state *yuv_linear_blit_fs_16bit;
361
362 /** @{ Current pipeline state objects */
363 struct pipe_scissor_state scissor;
364 struct pipe_blend_state *blend;
365 struct vc4_rasterizer_state *rasterizer;
366 struct vc4_depth_stencil_alpha_state *zsa;
367
368 struct vc4_texture_stateobj verttex, fragtex;
369
370 struct vc4_program_stateobj prog;
371
372 struct vc4_vertex_stateobj *vtx;
373
374 struct {
375 struct pipe_blend_color f;
376 uint8_t ub[4];
377 } blend_color;
378 struct pipe_stencil_ref stencil_ref;
379 unsigned sample_mask;
380 struct pipe_framebuffer_state framebuffer;
381 struct pipe_poly_stipple stipple;
382 struct pipe_clip_state clip;
383 struct pipe_viewport_state viewport;
384 struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
385 struct vc4_vertexbuf_stateobj vertexbuf;
386 struct pipe_debug_callback debug;
387
388 struct vc4_hwperfmon *perfmon;
389 /** @} */
390
391 /** Handle of syncobj containing the last submitted job fence. */
392 uint32_t job_syncobj;
393
394 int in_fence_fd;
395 /** Handle of the syncobj that holds in_fence_fd for submission. */
396 uint32_t in_syncobj;
397 };
398
399 struct vc4_rasterizer_state {
400 struct pipe_rasterizer_state base;
401
402 /* VC4_CONFIGURATION_BITS */
403 uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
404
405 struct PACKED {
406 uint8_t depth_offset[V3D21_DEPTH_OFFSET_length];
407 uint8_t point_size[V3D21_POINT_SIZE_length];
408 uint8_t line_width[V3D21_LINE_WIDTH_length];
409 } packed;
410
411 /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
412 uint32_t tile_raster_order_flags;
413 };
414
415 struct vc4_depth_stencil_alpha_state {
416 struct pipe_depth_stencil_alpha_state base;
417
418 /* VC4_CONFIGURATION_BITS */
419 uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
420
421 /** Uniforms for stencil state.
422 *
423 * Index 0 is either the front config, or the front-and-back config.
424 * Index 1 is the back config if doing separate back stencil.
425 * Index 2 is the writemask config if it's not a common mask value.
426 */
427 uint32_t stencil_uniforms[3];
428 };
429
430 #define perf_debug(...) do { \
431 if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \
432 fprintf(stderr, __VA_ARGS__); \
433 if (unlikely(vc4->debug.debug_message)) \
434 pipe_debug_message(&vc4->debug, PERF_INFO, __VA_ARGS__); \
435 } while (0)
436
437 static inline struct vc4_context *
vc4_context(struct pipe_context * pcontext)438 vc4_context(struct pipe_context *pcontext)
439 {
440 return (struct vc4_context *)pcontext;
441 }
442
443 static inline struct vc4_sampler_view *
vc4_sampler_view(struct pipe_sampler_view * psview)444 vc4_sampler_view(struct pipe_sampler_view *psview)
445 {
446 return (struct vc4_sampler_view *)psview;
447 }
448
449 static inline struct vc4_sampler_state *
vc4_sampler_state(struct pipe_sampler_state * psampler)450 vc4_sampler_state(struct pipe_sampler_state *psampler)
451 {
452 return (struct vc4_sampler_state *)psampler;
453 }
454
455 int vc4_get_driver_query_group_info(struct pipe_screen *pscreen,
456 unsigned index,
457 struct pipe_driver_query_group_info *info);
458 int vc4_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
459 struct pipe_driver_query_info *info);
460
461 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
462 void *priv, unsigned flags);
463 void vc4_draw_init(struct pipe_context *pctx);
464 void vc4_state_init(struct pipe_context *pctx);
465 void vc4_program_init(struct pipe_context *pctx);
466 void vc4_program_fini(struct pipe_context *pctx);
467 void vc4_query_init(struct pipe_context *pctx);
468 void vc4_simulator_init(struct vc4_screen *screen);
469 void vc4_simulator_destroy(struct vc4_screen *screen);
470 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
471 void vc4_simulator_open_from_handle(int fd, int handle, uint32_t size);
472
473 static inline int
vc4_ioctl(int fd,unsigned long request,void * arg)474 vc4_ioctl(int fd, unsigned long request, void *arg)
475 {
476 if (using_vc4_simulator)
477 return vc4_simulator_ioctl(fd, request, arg);
478 else
479 return drmIoctl(fd, request, arg);
480 }
481
482 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
483 void vc4_write_uniforms(struct vc4_context *vc4,
484 struct vc4_compiled_shader *shader,
485 struct vc4_constbuf_stateobj *cb,
486 struct vc4_texture_stateobj *texstate);
487
488 void vc4_flush(struct pipe_context *pctx);
489 int vc4_job_init(struct vc4_context *vc4);
490 int vc4_fence_context_init(struct vc4_context *vc4);
491 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
492 struct pipe_surface *cbuf,
493 struct pipe_surface *zsbuf);
494 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
495
496 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
497 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
498 struct pipe_resource *prsc);
499 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
500 struct pipe_resource *prsc);
501 void vc4_emit_state(struct pipe_context *pctx);
502 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
503 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
504 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
505
506 bool vc4_rt_format_supported(enum pipe_format f);
507 bool vc4_rt_format_is_565(enum pipe_format f);
508 bool vc4_tex_format_supported(enum pipe_format f);
509 uint8_t vc4_get_tex_format(enum pipe_format f);
510 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
511 void vc4_init_query_functions(struct vc4_context *vc4);
512 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
513 void vc4_blitter_save(struct vc4_context *vc4);
514 #endif /* VC4_CONTEXT_H */
515