| /external/llvm-project/llvm/test/MC/AArch64/SVE/ |
| D | trn1-diagnostics.s | 4 trn1 z10.h, z22.h, z31.x label
10 trn1 z10.h, z3.h, z15.b label
16 trn1 z1.h, z2.h label
22 trn1 z1.s, z2.s, z32.s label
28 trn1 p1.s, p2.s, p16.s label
34 trn1 z1.s, z2.s, p3.s label
40 trn1 p1.s, p2.s, z3.s label
50 trn1 z31.d, z31.d, z31.d label
56 trn1 z31.d, z31.d, z31.d label
|
| D | trn1.s | 10 trn1 z31.b, z31.b, z31.b label
16 trn1 z31.h, z31.h, z31.h label
22 trn1 z31.s, z31.s, z31.s label
28 trn1 z31.d, z31.d, z31.d label
34 trn1 p15.b, p15.b, p15.b label
40 trn1 p15.s, p15.s, p15.s label
46 trn1 p15.h, p15.h, p15.h label
52 trn1 p15.d, p15.d, p15.d label
|
| D | matrix-multiply-fp64.s | 271 trn1 z0.q, z1.q, z2.q label
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2159 __ trn1(v19.V16B(), v24.V16B(), v12.V16B()); in GenerateTestSequenceNEON() local
2160 __ trn1(v2.V2D(), v7.V2D(), v10.V2D()); in GenerateTestSequenceNEON() local
2161 __ trn1(v22.V2S(), v0.V2S(), v21.V2S()); in GenerateTestSequenceNEON() local
2162 __ trn1(v12.V4H(), v15.V4H(), v20.V4H()); in GenerateTestSequenceNEON() local
2163 __ trn1(v30.V4S(), v17.V4S(), v9.V4S()); in GenerateTestSequenceNEON() local
2164 __ trn1(v12.V8B(), v19.V8B(), v29.V8B()); in GenerateTestSequenceNEON() local
2165 __ trn1(v23.V8H(), v8.V8H(), v9.V8H()); in GenerateTestSequenceNEON() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 5386 void Assembler::trn1(const PRegisterWithLaneSize& pd, in trn1() function in vixl::aarch64::Assembler
5487 void Assembler::trn1(const ZRegister& zd, in trn1() function in vixl::aarch64::Assembler
|
| D | assembler-aarch64.cc | 4842 void Assembler::trn1(const VRegister& vd, in trn1() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 4169 LogicVRegister Simulator::trn1(VectorFormat vform, in trn1() function in vixl::aarch64::Simulator
|