1 /*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <platform_def.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/interrupt_props.h>
15 #include <drivers/arm/gicv2.h>
16 #include <drivers/arm/gic_common.h>
17 #include <lib/mmio.h>
18 #include <lib/xlat_tables/xlat_tables_v2.h>
19 #include <plat/common/platform.h>
20
21 #include "rcar_def.h"
22 #include "rcar_private.h"
23 #include "rcar_version.h"
24
25 #if (IMAGE_BL2)
26 extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
27 extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
28 #endif
29
30 const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
31 __attribute__ ((__section__("ro"))) = VERSION_OF_RENESAS;
32
33 #define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
34 RCAR_SHARED_MEM_SIZE, \
35 MT_MEMORY | MT_RW | MT_SECURE)
36
37 #define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
38 FLASH0_SIZE, \
39 MT_MEMORY | MT_RO | MT_SECURE)
40
41 #define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
42 DRAM1_NS_SIZE, \
43 MT_MEMORY | MT_RW | MT_NS)
44
45 #define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
46 DEVICE_RCAR_SIZE, \
47 MT_DEVICE | MT_RW | MT_SECURE)
48
49 #define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
50 DEVICE_RCAR_SIZE2, \
51 MT_DEVICE | MT_RW | MT_SECURE)
52
53 #define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
54 DEVICE_SRAM_SIZE, \
55 MT_MEMORY | MT_RO | MT_SECURE)
56
57 #define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
58 DEVICE_SRAM_STACK_SIZE, \
59 MT_MEMORY | MT_RW | MT_SECURE)
60
61 #define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
62 RCAR_BL31_CRASH_SIZE, \
63 MT_MEMORY | MT_RW | MT_SECURE)
64
65 #define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
66 RCAR_BL31_LOG_SIZE, \
67 MT_DEVICE | MT_RW | MT_SECURE)
68 #if IMAGE_BL2
69 #define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
70 DRAM1_SIZE, \
71 MT_MEMORY | MT_RW | MT_SECURE)
72
73 #define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
74 DEVICE_RCAR_SIZE, \
75 MT_DEVICE | MT_RW | MT_SECURE)
76
77 #define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \
78 RCAR_SYSRAM_SIZE, \
79 MT_MEMORY | MT_RW | MT_SECURE)
80
81 #define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \
82 REG1_SIZE, \
83 MT_DEVICE | MT_RW | MT_SECURE)
84
85 #define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \
86 ROM0_SIZE, \
87 MT_MEMORY | MT_RO | MT_SECURE)
88
89 #define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \
90 REG2_SIZE, \
91 MT_DEVICE | MT_RW | MT_SECURE)
92
93 #define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \
94 DRAM_40BIT_SIZE, \
95 MT_MEMORY | MT_RW | MT_SECURE)
96 #endif
97
98 #ifdef BL32_BASE
99 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \
100 BL32_LIMIT - BL32_BASE, \
101 MT_MEMORY | MT_RW | MT_SECURE)
102 #endif
103
104 #if IMAGE_BL2
105 static const mmap_region_t rcar_mmap[] = {
106 MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
107 MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
108 MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
109 MAP_RAM0, /* 0xE6300000 - 0xE6303FFF System RAM area */
110 MAP_REG1, /* 0xE6400000 - 0xEAFFFFFF SoC register area */
111 MAP_ROM, /* 0xEB100000 - 0xEB127FFF boot ROM area */
112 MAP_REG2, /* 0xEC000000 - 0xFFFFFFFF SoC register area */
113 MAP_DRAM1, /* 0x0400000000 - 0x07FFFFFFFF DRAM area(4GB over) */
114 {0}
115 };
116 #endif
117
118 #if IMAGE_BL31
119 static const mmap_region_t rcar_mmap[] = {
120 MAP_SHARED_RAM,
121 MAP_ATFW_CRASH,
122 MAP_ATFW_LOG,
123 MAP_DEVICE_RCAR,
124 MAP_DEVICE_RCAR2,
125 MAP_SRAM,
126 MAP_SRAM_STACK,
127 {0}
128 };
129 #endif
130
131 #if IMAGE_BL32
132 static const mmap_region_t rcar_mmap[] = {
133 MAP_DEVICE0,
134 MAP_DEVICE1,
135 {0}
136 };
137 #endif
138
139 CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS
140 <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
141
142 /*
143 * Macro generating the code for the function setting up the pagetables as per
144 * the platform memory map & initialize the mmu, for the given exception level
145 */
146 #if USE_COHERENT_MEM
rcar_configure_mmu_el3(unsigned long total_base,unsigned long total_size,unsigned long ro_start,unsigned long ro_limit,unsigned long coh_start,unsigned long coh_limit)147 void rcar_configure_mmu_el3(unsigned long total_base,
148 unsigned long total_size,
149 unsigned long ro_start,
150 unsigned long ro_limit,
151 unsigned long coh_start,
152 unsigned long coh_limit)
153 {
154 mmap_add_region(total_base, total_base, total_size,
155 MT_MEMORY | MT_RW | MT_SECURE);
156 mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
157 MT_MEMORY | MT_RO | MT_SECURE);
158 mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
159 MT_DEVICE | MT_RW | MT_SECURE);
160 mmap_add(rcar_mmap);
161
162 init_xlat_tables();
163 enable_mmu_el3(0);
164 }
165 #else
rcar_configure_mmu_el3(unsigned long total_base,unsigned long total_size,unsigned long ro_start,unsigned long ro_limit)166 void rcar_configure_mmu_el3(unsigned long total_base,
167 unsigned long total_size,
168 unsigned long ro_start,
169 unsigned long ro_limit)
170 {
171 mmap_add_region(total_base, total_base, total_size,
172 MT_MEMORY | MT_RW | MT_SECURE);
173 mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
174 MT_MEMORY | MT_RO | MT_SECURE);
175 mmap_add(rcar_mmap);
176
177 init_xlat_tables();
178 enable_mmu_el3(0);
179 }
180 #endif
181
plat_get_ns_image_entrypoint(void)182 uintptr_t plat_get_ns_image_entrypoint(void)
183 {
184 #if (IMAGE_BL2)
185 uint32_t cert, len;
186 uintptr_t dst;
187 int32_t ret;
188
189 ret = rcar_get_certificate(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert);
190 if (ret) {
191 ERROR("%s : cert file load error", __func__);
192 return NS_IMAGE_OFFSET;
193 }
194
195 rcar_read_certificate((uint64_t) cert, &len, &dst);
196
197 return dst;
198 #else
199 return NS_IMAGE_OFFSET;
200 #endif
201 }
202
plat_get_syscnt_freq2(void)203 unsigned int plat_get_syscnt_freq2(void)
204 {
205 unsigned int freq;
206
207 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
208 if (freq == 0)
209 panic();
210
211 return freq;
212 }
213
plat_rcar_gic_init(void)214 void plat_rcar_gic_init(void)
215 {
216 gicv2_distif_init();
217 gicv2_pcpu_distif_init();
218 gicv2_cpuif_enable();
219 }
220
221 static const interrupt_prop_t interrupt_props[] = {
222 #if IMAGE_BL2
223 INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
224 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
225 #else
226 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
227 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
228 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
229 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
230 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
231 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
232 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
233 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
234 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
235 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
236 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
238 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
240 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
242 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
243 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
244 INTR_PROP_DESC(ARM_IRQ_SEC_RPC, GIC_HIGHEST_SEC_PRIORITY,
245 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
246 INTR_PROP_DESC(ARM_IRQ_SEC_TIMER, GIC_HIGHEST_SEC_PRIORITY,
247 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
248 INTR_PROP_DESC(ARM_IRQ_SEC_TIMER_UP, GIC_HIGHEST_SEC_PRIORITY,
249 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
250 INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
251 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
252 INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT, GIC_HIGHEST_SEC_PRIORITY,
253 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
254 INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_SecPKA, GIC_HIGHEST_SEC_PRIORITY,
255 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
256 INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_PubPKA, GIC_HIGHEST_SEC_PRIORITY,
257 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
258 #endif
259 };
260
261 static const gicv2_driver_data_t plat_gicv2_driver_data = {
262 .interrupt_props = interrupt_props,
263 .interrupt_props_num = (uint32_t) ARRAY_SIZE(interrupt_props),
264 .gicd_base = RCAR_GICD_BASE,
265 .gicc_base = RCAR_GICC_BASE,
266 };
267
plat_rcar_gic_driver_init(void)268 void plat_rcar_gic_driver_init(void)
269 {
270 gicv2_driver_init(&plat_gicv2_driver_data);
271 }
272