1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "util/u_memory.h"
24 #include "util/format/u_format.h"
25 #include "util/format/u_format_s3tc.h"
26 #include "util/u_screen.h"
27 #include "util/u_video.h"
28 #include "util/u_math.h"
29 #include "util/os_time.h"
30 #include "util/xmlconfig.h"
31 #include "pipe/p_defines.h"
32 #include "pipe/p_screen.h"
33
34 #include "tgsi/tgsi_exec.h"
35
36 #include "virgl_screen.h"
37 #include "virgl_resource.h"
38 #include "virgl_public.h"
39 #include "virgl_context.h"
40 #include "virtio-gpu/virgl_protocol.h"
41
42 int virgl_debug = 0;
43 static const struct debug_named_value debug_options[] = {
44 { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
45 { "tgsi", VIRGL_DEBUG_TGSI, NULL },
46 { "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA, "Disable tweak to emulate BGRA as RGBA on GLES hosts"},
47 { "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,"Disable tweak to swizzle emulated BGRA on GLES hosts" },
48 { "sync", VIRGL_DEBUG_SYNC, "Sync after every flush" },
49 { "xfer", VIRGL_DEBUG_XFER, "Do not optimize for transfers" },
50 DEBUG_NAMED_VALUE_END
51 };
52 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
53
54 static const char *
virgl_get_vendor(struct pipe_screen * screen)55 virgl_get_vendor(struct pipe_screen *screen)
56 {
57 return "Mesa/X.org";
58 }
59
60
61 static const char *
virgl_get_name(struct pipe_screen * screen)62 virgl_get_name(struct pipe_screen *screen)
63 {
64 return "virgl";
65 }
66
67 static int
virgl_get_param(struct pipe_screen * screen,enum pipe_cap param)68 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
69 {
70 struct virgl_screen *vscreen = virgl_screen(screen);
71 switch (param) {
72 case PIPE_CAP_NPOT_TEXTURES:
73 return 1;
74 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
75 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
76 case PIPE_CAP_VERTEX_SHADER_SATURATE:
77 return 1;
78 case PIPE_CAP_ANISOTROPIC_FILTER:
79 return 1;
80 case PIPE_CAP_POINT_SPRITE:
81 return 1;
82 case PIPE_CAP_MAX_RENDER_TARGETS:
83 return vscreen->caps.caps.v1.max_render_targets;
84 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
85 return vscreen->caps.caps.v1.max_dual_source_render_targets;
86 case PIPE_CAP_OCCLUSION_QUERY:
87 return vscreen->caps.caps.v1.bset.occlusion_query;
88 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
89 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
90 return vscreen->caps.caps.v1.bset.mirror_clamp;
91 case PIPE_CAP_TEXTURE_SWIZZLE:
92 return 1;
93 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
94 if (vscreen->caps.caps.v2.max_texture_2d_size)
95 return vscreen->caps.caps.v2.max_texture_2d_size;
96 return 16384;
97 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
98 if (vscreen->caps.caps.v2.max_texture_3d_size)
99 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
100 return 9; /* 256 x 256 x 256 */
101 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
102 if (vscreen->caps.caps.v2.max_texture_cube_size)
103 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
104 return 13; /* 4K x 4K */
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
106 return 1;
107 case PIPE_CAP_INDEP_BLEND_ENABLE:
108 return vscreen->caps.caps.v1.bset.indep_blend_enable;
109 case PIPE_CAP_INDEP_BLEND_FUNC:
110 return vscreen->caps.caps.v1.bset.indep_blend_func;
111 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
112 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
113 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
114 return 1;
115 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
116 return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
117 case PIPE_CAP_DEPTH_CLIP_DISABLE:
118 if (vscreen->caps.caps.v1.bset.depth_clip_disable)
119 return 1;
120 if (vscreen->caps.caps.v2.host_feature_check_version >= 3)
121 return 2;
122 return 0;
123 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
124 return vscreen->caps.caps.v1.max_streamout_buffers;
125 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
127 return 16*4;
128 case PIPE_CAP_PRIMITIVE_RESTART:
129 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
130 return vscreen->caps.caps.v1.bset.primitive_restart;
131 case PIPE_CAP_SHADER_STENCIL_EXPORT:
132 return vscreen->caps.caps.v1.bset.shader_stencil_export;
133 case PIPE_CAP_TGSI_INSTANCEID:
134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
135 return 1;
136 case PIPE_CAP_SEAMLESS_CUBE_MAP:
137 return vscreen->caps.caps.v1.bset.seamless_cube_map;
138 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
139 return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
140 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
141 return vscreen->caps.caps.v1.max_texture_array_layers;
142 case PIPE_CAP_MIN_TEXEL_OFFSET:
143 return vscreen->caps.caps.v2.min_texel_offset;
144 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
145 return vscreen->caps.caps.v2.min_texture_gather_offset;
146 case PIPE_CAP_MAX_TEXEL_OFFSET:
147 return vscreen->caps.caps.v2.max_texel_offset;
148 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
149 return vscreen->caps.caps.v2.max_texture_gather_offset;
150 case PIPE_CAP_CONDITIONAL_RENDER:
151 return vscreen->caps.caps.v1.bset.conditional_render;
152 case PIPE_CAP_TEXTURE_BARRIER:
153 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
154 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
155 return 1;
156 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
157 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
158 return vscreen->caps.caps.v1.bset.color_clamping;
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
161 (vscreen->caps.caps.v2.host_feature_check_version < 1);
162 case PIPE_CAP_GLSL_FEATURE_LEVEL:
163 return vscreen->caps.caps.v1.glsl_level;
164 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
165 return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
166 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
167 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
168 return 0;
169 case PIPE_CAP_COMPUTE:
170 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
171 case PIPE_CAP_USER_VERTEX_BUFFERS:
172 return 0;
173 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
174 return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
175 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
176 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
177 return vscreen->caps.caps.v1.bset.streamout_pause_resume;
178 case PIPE_CAP_START_INSTANCE:
179 return vscreen->caps.caps.v1.bset.start_instance;
180 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
181 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
182 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
183 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
184 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
185 return 0;
186 case PIPE_CAP_QUERY_TIMESTAMP:
187 return 1;
188 case PIPE_CAP_QUERY_TIME_ELAPSED:
189 return 1;
190 case PIPE_CAP_TGSI_TEXCOORD:
191 return 0;
192 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
193 return VIRGL_MAP_BUFFER_ALIGNMENT;
194 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
195 return vscreen->caps.caps.v1.max_tbo_size > 0;
196 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
197 return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
198 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
199 return 0;
200 case PIPE_CAP_CUBE_MAP_ARRAY:
201 return vscreen->caps.caps.v1.bset.cube_map_array;
202 case PIPE_CAP_TEXTURE_MULTISAMPLE:
203 return vscreen->caps.caps.v1.bset.texture_multisample;
204 case PIPE_CAP_MAX_VIEWPORTS:
205 return vscreen->caps.caps.v1.max_viewports;
206 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
207 return vscreen->caps.caps.v1.max_tbo_size;
208 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
209 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
210 case PIPE_CAP_ENDIANNESS:
211 return 0;
212 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
213 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
214 return 1;
215 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
216 return 0;
217 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
218 return vscreen->caps.caps.v2.max_geom_output_vertices;
219 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
220 return vscreen->caps.caps.v2.max_geom_total_output_components;
221 case PIPE_CAP_TEXTURE_QUERY_LOD:
222 return vscreen->caps.caps.v1.bset.texture_query_lod;
223 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
224 return vscreen->caps.caps.v1.max_texture_gather_components;
225 case PIPE_CAP_DRAW_INDIRECT:
226 return vscreen->caps.caps.v1.bset.has_indirect_draw;
227 case PIPE_CAP_SAMPLE_SHADING:
228 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
229 return vscreen->caps.caps.v1.bset.has_sample_shading;
230 case PIPE_CAP_CULL_DISTANCE:
231 return vscreen->caps.caps.v1.bset.has_cull;
232 case PIPE_CAP_MAX_VERTEX_STREAMS:
233 return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
234 (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
235 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
236 return vscreen->caps.caps.v1.bset.conditional_render_inverted;
237 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
238 return vscreen->caps.caps.v1.bset.derivative_control;
239 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
240 return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
241 case PIPE_CAP_QUERY_SO_OVERFLOW:
242 return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
243 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
244 return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
245 case PIPE_CAP_DOUBLES:
246 return vscreen->caps.caps.v1.bset.has_fp64 ||
247 (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
248 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
249 return vscreen->caps.caps.v2.max_shader_patch_varyings;
250 case PIPE_CAP_SAMPLER_VIEW_TARGET:
251 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
252 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
253 return vscreen->caps.caps.v2.max_vertex_attrib_stride;
254 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
255 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
256 case PIPE_CAP_TGSI_TXQS:
257 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
258 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
259 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
260 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
261 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
262 case PIPE_CAP_FBFETCH:
263 return (vscreen->caps.caps.v2.capability_bits &
264 VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
265 case PIPE_CAP_BLEND_EQUATION_ADVANCED:
266 return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION;
267 case PIPE_CAP_TGSI_CLOCK:
268 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
269 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
270 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
271 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
272 return vscreen->caps.caps.v2.max_combined_shader_buffers;
273 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
274 return vscreen->caps.caps.v2.max_combined_atomic_counters;
275 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
276 return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
277 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
278 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
279 return 1; /* TODO: need to introduce a hw-cap for this */
280 case PIPE_CAP_QUERY_BUFFER_OBJECT:
281 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
282 case PIPE_CAP_MAX_VARYINGS:
283 if (vscreen->caps.caps.v1.glsl_level < 150)
284 return vscreen->caps.caps.v2.max_vertex_attribs;
285 return 32;
286 case PIPE_CAP_FAKE_SW_MSAA:
287 /* If the host supports only one sample (e.g., if it is using softpipe),
288 * fake multisampling to able to advertise higher GL versions. */
289 return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
290 case PIPE_CAP_MULTI_DRAW_INDIRECT:
291 return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
292 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
293 return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
294 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
295 return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ARB_BUFFER_STORAGE) &&
296 (vscreen->caps.caps.v2.host_feature_check_version >= 4) &&
297 vscreen->vws->supports_coherent;
298 case PIPE_CAP_PCI_GROUP:
299 case PIPE_CAP_PCI_BUS:
300 case PIPE_CAP_PCI_DEVICE:
301 case PIPE_CAP_PCI_FUNCTION:
302 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
303 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
304 return 0;
305 case PIPE_CAP_CLEAR_TEXTURE:
306 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLEAR_TEXTURE;
307 case PIPE_CAP_CLIP_HALFZ:
308 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
309 case PIPE_CAP_MAX_GS_INVOCATIONS:
310 return 32;
311 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
312 return 1 << 27;
313 case PIPE_CAP_VENDOR_ID:
314 return 0x1af4;
315 case PIPE_CAP_DEVICE_ID:
316 return 0x1010;
317 case PIPE_CAP_ACCELERATED:
318 return 1;
319 case PIPE_CAP_UMA:
320 case PIPE_CAP_VIDEO_MEMORY:
321 return 0;
322 case PIPE_CAP_NATIVE_FENCE_FD:
323 return vscreen->vws->supports_fences;
324 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
325 return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
326 (vscreen->caps.caps.v2.host_feature_check_version < 1);
327 case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
328 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
329 default:
330 return u_pipe_screen_get_param_defaults(screen, param);
331 }
332 }
333
334 static int
virgl_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)335 virgl_get_shader_param(struct pipe_screen *screen,
336 enum pipe_shader_type shader,
337 enum pipe_shader_cap param)
338 {
339 struct virgl_screen *vscreen = virgl_screen(screen);
340
341 if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
342 !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
343 return 0;
344
345 if (shader == PIPE_SHADER_COMPUTE &&
346 !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
347 return 0;
348
349 switch(shader)
350 {
351 case PIPE_SHADER_FRAGMENT:
352 case PIPE_SHADER_VERTEX:
353 case PIPE_SHADER_GEOMETRY:
354 case PIPE_SHADER_TESS_CTRL:
355 case PIPE_SHADER_TESS_EVAL:
356 case PIPE_SHADER_COMPUTE:
357 switch (param) {
358 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
359 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
360 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
361 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
362 return INT_MAX;
363 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
364 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
365 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
366 return 1;
367 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
368 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
369 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
370 case PIPE_SHADER_CAP_MAX_INPUTS:
371 if (vscreen->caps.caps.v1.glsl_level < 150)
372 return vscreen->caps.caps.v2.max_vertex_attribs;
373 return (shader == PIPE_SHADER_VERTEX ||
374 shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
375 case PIPE_SHADER_CAP_MAX_OUTPUTS:
376 if (shader == PIPE_SHADER_FRAGMENT)
377 return vscreen->caps.caps.v1.max_render_targets;
378 return vscreen->caps.caps.v2.max_vertex_outputs;
379 // case PIPE_SHADER_CAP_MAX_CONSTS:
380 // return 4096;
381 case PIPE_SHADER_CAP_MAX_TEMPS:
382 return 256;
383 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
384 return vscreen->caps.caps.v1.max_uniform_blocks;
385 // case PIPE_SHADER_CAP_MAX_ADDRS:
386 // return 1;
387 case PIPE_SHADER_CAP_SUBROUTINES:
388 return 1;
389 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
390 return 16;
391 case PIPE_SHADER_CAP_INTEGERS:
392 return vscreen->caps.caps.v1.glsl_level >= 130;
393 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
394 return 32;
395 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
396 return 4096 * sizeof(float[4]);
397 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
398 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
399 return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
400 else
401 return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
402 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
403 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
404 return vscreen->caps.caps.v2.max_shader_image_frag_compute;
405 else
406 return vscreen->caps.caps.v2.max_shader_image_other_stages;
407 case PIPE_SHADER_CAP_SUPPORTED_IRS:
408 return (1 << PIPE_SHADER_IR_TGSI);
409 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
410 return vscreen->caps.caps.v2.max_atomic_counters[shader];
411 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
412 return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
413 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
414 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
415 case PIPE_SHADER_CAP_INT64_ATOMICS:
416 case PIPE_SHADER_CAP_FP16:
417 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
418 case PIPE_SHADER_CAP_INT16:
419 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
420 return 0;
421 default:
422 return 0;
423 }
424 default:
425 return 0;
426 }
427 }
428
429 static float
virgl_get_paramf(struct pipe_screen * screen,enum pipe_capf param)430 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
431 {
432 struct virgl_screen *vscreen = virgl_screen(screen);
433 switch (param) {
434 case PIPE_CAPF_MAX_LINE_WIDTH:
435 return vscreen->caps.caps.v2.max_aliased_line_width;
436 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
437 return vscreen->caps.caps.v2.max_smooth_line_width;
438 case PIPE_CAPF_MAX_POINT_WIDTH:
439 return vscreen->caps.caps.v2.max_aliased_point_size;
440 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
441 return vscreen->caps.caps.v2.max_smooth_point_size;
442 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
443 return 16.0;
444 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
445 return vscreen->caps.caps.v2.max_texture_lod_bias;
446 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
447 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
448 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
449 return 0.0f;
450 }
451 /* should only get here on unhandled cases */
452 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
453 return 0.0;
454 }
455
456 static int
virgl_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)457 virgl_get_compute_param(struct pipe_screen *screen,
458 enum pipe_shader_ir ir_type,
459 enum pipe_compute_cap param,
460 void *ret)
461 {
462 struct virgl_screen *vscreen = virgl_screen(screen);
463 if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
464 return 0;
465 switch (param) {
466 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
467 if (ret) {
468 uint64_t *grid_size = ret;
469 grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
470 grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
471 grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
472 }
473 return 3 * sizeof(uint64_t) ;
474 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
475 if (ret) {
476 uint64_t *block_size = ret;
477 block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
478 block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
479 block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
480 }
481 return 3 * sizeof(uint64_t);
482 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
483 if (ret) {
484 uint64_t *max_threads_per_block = ret;
485 *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
486 }
487 return sizeof(uint64_t);
488 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
489 if (ret) {
490 uint64_t *max_local_size = ret;
491 /* Value reported by the closed source driver. */
492 *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
493 }
494 return sizeof(uint64_t);
495 default:
496 break;
497 }
498 return 0;
499 }
500
501 static bool
has_format_bit(struct virgl_supported_format_mask * mask,enum virgl_formats fmt)502 has_format_bit(struct virgl_supported_format_mask *mask,
503 enum virgl_formats fmt)
504 {
505 assert(fmt < VIRGL_FORMAT_MAX);
506 unsigned val = (unsigned)fmt;
507 unsigned idx = val / 32;
508 unsigned bit = val % 32;
509 assert(idx < ARRAY_SIZE(mask->bitmask));
510 return (mask->bitmask[idx] & (1u << bit)) != 0;
511 }
512
513 bool
virgl_has_readback_format(struct pipe_screen * screen,enum virgl_formats fmt)514 virgl_has_readback_format(struct pipe_screen *screen,
515 enum virgl_formats fmt)
516 {
517 struct virgl_screen *vscreen = virgl_screen(screen);
518 return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
519 fmt);
520 }
521
522 static bool
virgl_is_vertex_format_supported(struct pipe_screen * screen,enum pipe_format format)523 virgl_is_vertex_format_supported(struct pipe_screen *screen,
524 enum pipe_format format)
525 {
526 struct virgl_screen *vscreen = virgl_screen(screen);
527 const struct util_format_description *format_desc;
528 int i;
529
530 format_desc = util_format_description(format);
531 if (!format_desc)
532 return false;
533
534 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
535 int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
536 int big = vformat / 32;
537 int small = vformat % 32;
538 if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
539 return false;
540 return true;
541 }
542
543 /* Find the first non-VOID channel. */
544 for (i = 0; i < 4; i++) {
545 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
546 break;
547 }
548 }
549
550 if (i == 4)
551 return false;
552
553 if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
554 return false;
555
556 if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
557 return false;
558 return true;
559 }
560
561 static bool
virgl_format_check_bitmask(enum pipe_format format,uint32_t bitmask[16],bool may_emulate_bgra)562 virgl_format_check_bitmask(enum pipe_format format,
563 uint32_t bitmask[16],
564 bool may_emulate_bgra)
565 {
566 enum virgl_formats vformat = pipe_to_virgl_format(format);
567 int big = vformat / 32;
568 int small = vformat % 32;
569 if ((bitmask[big] & (1 << small)))
570 return true;
571
572 /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
573 * emulate it by using a swizzled RGBx */
574 if (may_emulate_bgra) {
575 if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
576 format = PIPE_FORMAT_R8G8B8A8_SRGB;
577 else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
578 format = PIPE_FORMAT_R8G8B8X8_SRGB;
579 else {
580 return false;
581 }
582
583 vformat = pipe_to_virgl_format(format);
584 big = vformat / 32;
585 small = vformat % 32;
586 if (bitmask[big] & (1 << small))
587 return true;
588 }
589 return false;
590 }
591
592 /**
593 * Query format support for creating a texture, drawing surface, etc.
594 * \param format the format to test
595 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
596 */
597 static bool
virgl_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bind)598 virgl_is_format_supported( struct pipe_screen *screen,
599 enum pipe_format format,
600 enum pipe_texture_target target,
601 unsigned sample_count,
602 unsigned storage_sample_count,
603 unsigned bind)
604 {
605 struct virgl_screen *vscreen = virgl_screen(screen);
606 const struct util_format_description *format_desc;
607 int i;
608
609 union virgl_caps *caps = &vscreen->caps.caps;
610 boolean may_emulate_bgra = (caps->v2.capability_bits &
611 VIRGL_CAP_APP_TWEAK_SUPPORT) &&
612 vscreen->tweak_gles_emulate_bgra;
613
614 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
615 return false;
616
617 if (!util_is_power_of_two_or_zero(sample_count))
618 return false;
619
620 assert(target == PIPE_BUFFER ||
621 target == PIPE_TEXTURE_1D ||
622 target == PIPE_TEXTURE_1D_ARRAY ||
623 target == PIPE_TEXTURE_2D ||
624 target == PIPE_TEXTURE_2D_ARRAY ||
625 target == PIPE_TEXTURE_RECT ||
626 target == PIPE_TEXTURE_3D ||
627 target == PIPE_TEXTURE_CUBE ||
628 target == PIPE_TEXTURE_CUBE_ARRAY);
629
630 format_desc = util_format_description(format);
631 if (!format_desc)
632 return false;
633
634 if (util_format_is_intensity(format))
635 return false;
636
637 if (sample_count > 1) {
638 if (!caps->v1.bset.texture_multisample)
639 return false;
640
641 if (bind & PIPE_BIND_SHADER_IMAGE) {
642 if (sample_count > caps->v2.max_image_samples)
643 return false;
644 }
645
646 if (sample_count > caps->v1.max_samples)
647 return false;
648 }
649
650 if (bind & PIPE_BIND_VERTEX_BUFFER) {
651 return virgl_is_vertex_format_supported(screen, format);
652 }
653
654 if (util_format_is_compressed(format) && target == PIPE_BUFFER)
655 return false;
656
657 /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
658 if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
659 format == PIPE_FORMAT_R32G32B32_SINT ||
660 format == PIPE_FORMAT_R32G32B32_UINT) &&
661 target != PIPE_BUFFER)
662 return false;
663
664 if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
665 format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
666 format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
667 target == PIPE_TEXTURE_3D)
668 return false;
669
670
671 if (bind & PIPE_BIND_RENDER_TARGET) {
672 /* For ARB_framebuffer_no_attachments. */
673 if (format == PIPE_FORMAT_NONE)
674 return TRUE;
675
676 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
677 return false;
678
679 /*
680 * Although possible, it is unnatural to render into compressed or YUV
681 * surfaces. So disable these here to avoid going into weird paths
682 * inside gallium frontends.
683 */
684 if (format_desc->block.width != 1 ||
685 format_desc->block.height != 1)
686 return false;
687
688 if (!virgl_format_check_bitmask(format,
689 caps->v1.render.bitmask,
690 may_emulate_bgra))
691 return false;
692 }
693
694 if (bind & PIPE_BIND_DEPTH_STENCIL) {
695 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
696 return false;
697 }
698
699 if (bind & PIPE_BIND_SCANOUT) {
700 if (!virgl_format_check_bitmask(format, caps->v2.scanout.bitmask, false))
701 return false;
702 }
703
704 /*
705 * All other operations (sampling, transfer, etc).
706 */
707
708 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
709 goto out_lookup;
710 }
711 if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
712 goto out_lookup;
713 }
714 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
715 goto out_lookup;
716 }
717 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
718 goto out_lookup;
719 }
720
721 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
722 goto out_lookup;
723 } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
724 goto out_lookup;
725 }
726
727 /* Find the first non-VOID channel. */
728 for (i = 0; i < 4; i++) {
729 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
730 break;
731 }
732 }
733
734 if (i == 4)
735 return false;
736
737 /* no L4A4 */
738 if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
739 return false;
740
741 out_lookup:
742 return virgl_format_check_bitmask(format,
743 caps->v1.sampler.bitmask,
744 may_emulate_bgra);
745 }
746
virgl_flush_frontbuffer(struct pipe_screen * screen,struct pipe_resource * res,unsigned level,unsigned layer,void * winsys_drawable_handle,struct pipe_box * sub_box)747 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
748 struct pipe_resource *res,
749 unsigned level, unsigned layer,
750 void *winsys_drawable_handle, struct pipe_box *sub_box)
751 {
752 struct virgl_screen *vscreen = virgl_screen(screen);
753 struct virgl_winsys *vws = vscreen->vws;
754 struct virgl_resource *vres = virgl_resource(res);
755
756 if (vws->flush_frontbuffer)
757 vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
758 sub_box);
759 }
760
virgl_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)761 static void virgl_fence_reference(struct pipe_screen *screen,
762 struct pipe_fence_handle **ptr,
763 struct pipe_fence_handle *fence)
764 {
765 struct virgl_screen *vscreen = virgl_screen(screen);
766 struct virgl_winsys *vws = vscreen->vws;
767
768 vws->fence_reference(vws, ptr, fence);
769 }
770
virgl_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)771 static bool virgl_fence_finish(struct pipe_screen *screen,
772 struct pipe_context *ctx,
773 struct pipe_fence_handle *fence,
774 uint64_t timeout)
775 {
776 struct virgl_screen *vscreen = virgl_screen(screen);
777 struct virgl_winsys *vws = vscreen->vws;
778
779 return vws->fence_wait(vws, fence, timeout);
780 }
781
virgl_fence_get_fd(struct pipe_screen * screen,struct pipe_fence_handle * fence)782 static int virgl_fence_get_fd(struct pipe_screen *screen,
783 struct pipe_fence_handle *fence)
784 {
785 struct virgl_screen *vscreen = virgl_screen(screen);
786 struct virgl_winsys *vws = vscreen->vws;
787
788 return vws->fence_get_fd(vws, fence);
789 }
790
791 static uint64_t
virgl_get_timestamp(struct pipe_screen * _screen)792 virgl_get_timestamp(struct pipe_screen *_screen)
793 {
794 return os_time_get_nano();
795 }
796
797 static void
virgl_destroy_screen(struct pipe_screen * screen)798 virgl_destroy_screen(struct pipe_screen *screen)
799 {
800 struct virgl_screen *vscreen = virgl_screen(screen);
801 struct virgl_winsys *vws = vscreen->vws;
802
803 slab_destroy_parent(&vscreen->transfer_pool);
804
805 if (vws)
806 vws->destroy(vws);
807 FREE(vscreen);
808 }
809
810 static void
fixup_formats(union virgl_caps * caps,struct virgl_supported_format_mask * mask)811 fixup_formats(union virgl_caps *caps, struct virgl_supported_format_mask *mask)
812 {
813 const size_t size = ARRAY_SIZE(mask->bitmask);
814 for (int i = 0; i < size; ++i) {
815 if (mask->bitmask[i] != 0)
816 return; /* we got some formats, we definately have a new protocol */
817 }
818
819 /* old protocol used; fall back to considering all sampleable formats valid
820 * readback-formats
821 */
822 for (int i = 0; i < size; ++i)
823 mask->bitmask[i] = caps->v1.sampler.bitmask[i];
824 }
825
826 struct pipe_screen *
virgl_create_screen(struct virgl_winsys * vws,const struct pipe_screen_config * config)827 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
828 {
829 struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
830
831 const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
832 const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
833 const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
834
835 if (!screen)
836 return NULL;
837
838 virgl_debug = debug_get_option_virgl_debug();
839
840 if (config && config->options) {
841 screen->tweak_gles_emulate_bgra =
842 driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
843 screen->tweak_gles_apply_bgra_dest_swizzle =
844 driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
845 screen->tweak_gles_tf3_value =
846 driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
847 }
848 screen->tweak_gles_emulate_bgra &= !(virgl_debug & VIRGL_DEBUG_NO_EMULATE_BGRA);
849 screen->tweak_gles_apply_bgra_dest_swizzle &= !(virgl_debug & VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE);
850
851 screen->vws = vws;
852 screen->base.get_name = virgl_get_name;
853 screen->base.get_vendor = virgl_get_vendor;
854 screen->base.get_param = virgl_get_param;
855 screen->base.get_shader_param = virgl_get_shader_param;
856 screen->base.get_compute_param = virgl_get_compute_param;
857 screen->base.get_paramf = virgl_get_paramf;
858 screen->base.is_format_supported = virgl_is_format_supported;
859 screen->base.destroy = virgl_destroy_screen;
860 screen->base.context_create = virgl_context_create;
861 screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
862 screen->base.get_timestamp = virgl_get_timestamp;
863 screen->base.fence_reference = virgl_fence_reference;
864 //screen->base.fence_signalled = virgl_fence_signalled;
865 screen->base.fence_finish = virgl_fence_finish;
866 screen->base.fence_get_fd = virgl_fence_get_fd;
867
868 virgl_init_screen_resource_functions(&screen->base);
869
870 vws->get_caps(vws, &screen->caps);
871 fixup_formats(&screen->caps.caps,
872 &screen->caps.caps.v2.supported_readback_formats);
873 fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout);
874
875 union virgl_caps *caps = &screen->caps.caps;
876 bool may_emulate_bgra = (caps->v2.capability_bits & VIRGL_CAP_APP_TWEAK_SUPPORT);
877 screen->tweak_gles_emulate_bgra &= !virgl_format_check_bitmask(
878 PIPE_FORMAT_B8G8R8A8_SRGB, caps->v1.render.bitmask, may_emulate_bgra);
879 screen->refcnt = 1;
880
881 slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
882
883 return &screen->base;
884 }
885