1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef H_ETNA_INTERNAL
25 #define H_ETNA_INTERNAL
26
27 #include <assert.h>
28 #include <stdbool.h>
29 #include <stdint.h>
30
31 #include "hw/state.xml.h"
32 #include "hw/state_3d.xml.h"
33
34 #include "drm/etnaviv_drmif.h"
35
36 #define ETNA_NUM_INPUTS (16)
37 #define ETNA_NUM_VARYINGS 16
38 #define ETNA_NUM_LOD (14)
39 #define ETNA_NUM_LAYERS (6)
40 #define ETNA_MAX_UNIFORMS (256)
41 #define ETNA_MAX_CONST_BUF 16
42 #define ETNA_MAX_PIXELPIPES 2
43
44 /* All RS operations must have width%16 = 0 */
45 #define ETNA_RS_WIDTH_MASK (16 - 1)
46 /* RS tiled operations must have height%4 = 0 */
47 #define ETNA_RS_HEIGHT_MASK (3)
48 /* PE render targets must be aligned to 64 bytes */
49 #define ETNA_PE_ALIGNMENT (64)
50
51 /* These demarcate the margin (fixp16) between the computed sizes and the
52 value sent to the chip. These have been set to the numbers used by the
53 Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
54 am not sure whether older hardware was relying on these or they were just a
55 guess. But if so, these need to be moved to the _specs structure.
56 */
57 #define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
58 #define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
59 #define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
60 #define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
61
62 /* GPU chip 3D specs */
63 struct etna_specs {
64 /* HALTI (gross architecture) level. -1 for pre-HALTI. */
65 int halti : 8;
66 /* supports SUPERTILE (64x64) tiling? */
67 unsigned can_supertile : 1;
68 /* needs z=(z+w)/2, for older GCxxx */
69 unsigned vs_need_z_div : 1;
70 /* supports trigonometric instructions */
71 unsigned has_sin_cos_sqrt : 1;
72 /* has SIGN/FLOOR/CEIL instructions */
73 unsigned has_sign_floor_ceil : 1;
74 /* can use VS_RANGE, PS_RANGE registers*/
75 unsigned has_shader_range_registers : 1;
76 /* has the new sin/cos/log functions */
77 unsigned has_new_transcendentals : 1;
78 /* has the new dp2/dpX_norm instructions, among others */
79 unsigned has_halti2_instructions : 1;
80 /* has V4_COMPRESSION */
81 unsigned v4_compression : 1;
82 /* supports single-buffer rendering with multiple pixel pipes */
83 unsigned single_buffer : 1;
84 /* has unified uniforms memory */
85 unsigned has_unified_uniforms : 1;
86 /* can load shader instructions from memory */
87 unsigned has_icache : 1;
88 /* ASTC texture support (and has associated states) */
89 unsigned tex_astc : 1;
90 /* has BLT engine instead of RS */
91 unsigned use_blt : 1;
92 /* can use any kind of wrapping mode on npot textures */
93 unsigned npot_tex_any_wrap : 1;
94 /* supports seamless cube map */
95 unsigned seamless_cube_map : 1;
96 /* number of bits per TS tile */
97 unsigned bits_per_tile;
98 /* clear value for TS (dependent on bits_per_tile) */
99 uint32_t ts_clear_value;
100 /* base of vertex texture units */
101 unsigned vertex_sampler_offset;
102 /* number of fragment sampler units */
103 unsigned fragment_sampler_count;
104 /* number of vertex sampler units */
105 unsigned vertex_sampler_count;
106 /* size of vertex shader output buffer */
107 unsigned vertex_output_buffer_size;
108 /* maximum number of vertex element configurations */
109 unsigned vertex_max_elements;
110 /* size of a cached vertex (?) */
111 unsigned vertex_cache_size;
112 /* number of shader cores */
113 unsigned shader_core_count;
114 /* number of vertex streams */
115 unsigned stream_count;
116 /* vertex shader memory address*/
117 uint32_t vs_offset;
118 /* pixel shader memory address*/
119 uint32_t ps_offset;
120 /* vertex shader uniforms address*/
121 uint32_t vs_uniforms_offset;
122 /* pixel shader uniforms address*/
123 uint32_t ps_uniforms_offset;
124 /* vertex/fragment shader max instructions */
125 uint32_t max_instructions;
126 /* maximum number of varyings */
127 unsigned max_varyings;
128 /* maximum number of registers */
129 unsigned max_registers;
130 /* maximum vertex uniforms */
131 unsigned max_vs_uniforms;
132 /* maximum pixel uniforms */
133 unsigned max_ps_uniforms;
134 /* maximum texture size */
135 unsigned max_texture_size;
136 /* maximum texture size */
137 unsigned max_rendertarget_size;
138 /* available pixel pipes */
139 unsigned pixel_pipes;
140 /* number of constants */
141 unsigned num_constants;
142 };
143
144 /* Compiled Gallium state. All the different compiled state atoms are woven
145 * together and uploaded only when it is necessary to synchronize the state,
146 * for example before rendering. */
147
148 /* Compiled pipe_blend_color */
149 struct compiled_blend_color {
150 float color[4];
151 uint32_t PE_ALPHA_BLEND_COLOR;
152 uint32_t PE_ALPHA_COLOR_EXT0;
153 uint32_t PE_ALPHA_COLOR_EXT1;
154 };
155
156 /* Compiled pipe_stencil_ref */
157 struct compiled_stencil_ref {
158 uint32_t PE_STENCIL_CONFIG[2];
159 uint32_t PE_STENCIL_CONFIG_EXT[2];
160 };
161
162 /* Compiled pipe_viewport_state */
163 struct compiled_viewport_state {
164 uint32_t PA_VIEWPORT_SCALE_X;
165 uint32_t PA_VIEWPORT_SCALE_Y;
166 uint32_t PA_VIEWPORT_SCALE_Z;
167 uint32_t PA_VIEWPORT_OFFSET_X;
168 uint32_t PA_VIEWPORT_OFFSET_Y;
169 uint32_t PA_VIEWPORT_OFFSET_Z;
170 uint32_t SE_SCISSOR_LEFT;
171 uint32_t SE_SCISSOR_TOP;
172 uint32_t SE_SCISSOR_RIGHT;
173 uint32_t SE_SCISSOR_BOTTOM;
174 uint32_t PE_DEPTH_NEAR;
175 uint32_t PE_DEPTH_FAR;
176 };
177
178 /* Compiled pipe_framebuffer_state */
179 struct compiled_framebuffer_state {
180 uint32_t GL_MULTI_SAMPLE_CONFIG;
181 uint32_t PE_COLOR_FORMAT;
182 uint32_t PE_DEPTH_CONFIG;
183 struct etna_reloc PE_DEPTH_ADDR;
184 struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
185 uint32_t PE_DEPTH_STRIDE;
186 uint32_t PE_HDEPTH_CONTROL;
187 uint32_t PE_DEPTH_NORMALIZE;
188 struct etna_reloc PE_COLOR_ADDR;
189 struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
190 uint32_t PE_COLOR_STRIDE;
191 uint32_t PE_MEM_CONFIG;
192 uint32_t RA_MULTISAMPLE_UNK00E04;
193 uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
194 uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
195 uint32_t TS_MEM_CONFIG;
196 uint32_t TS_DEPTH_CLEAR_VALUE;
197 struct etna_reloc TS_DEPTH_STATUS_BASE;
198 struct etna_reloc TS_DEPTH_SURFACE_BASE;
199 uint32_t TS_COLOR_CLEAR_VALUE;
200 uint32_t TS_COLOR_CLEAR_VALUE_EXT;
201 struct etna_reloc TS_COLOR_STATUS_BASE;
202 struct etna_reloc TS_COLOR_SURFACE_BASE;
203 uint32_t PE_LOGIC_OP;
204 uint32_t PS_CONTROL;
205 uint32_t PS_CONTROL_EXT;
206 bool msaa_mode; /* adds input (and possible temp) to PS */
207 };
208
209 /* Compiled context->create_vertex_elements_state */
210 struct compiled_vertex_elements_state {
211 unsigned num_elements;
212 uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
213 uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN];
214 uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
215 uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN];
216 unsigned num_buffers;
217 uint32_t NFE_VERTEX_STREAMS_VERTEX_DIVISOR[VIVS_NFE_VERTEX_STREAMS__LEN];
218 };
219
220 /* Compiled context->set_vertex_buffer result */
221 struct compiled_set_vertex_buffer {
222 uint32_t FE_VERTEX_STREAM_CONTROL;
223 struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
224 };
225
226 /* Compiled linked VS+PS shader state */
227 struct compiled_shader_state {
228 uint32_t RA_CONTROL;
229 uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
230 uint32_t PA_CONFIG;
231 uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
232 uint32_t VS_END_PC;
233 uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
234 uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
235 uint32_t VS_INPUT_COUNT;
236 uint32_t VS_TEMP_REGISTER_CONTROL;
237 uint32_t VS_OUTPUT[4];
238 uint32_t VS_INPUT[4];
239 uint32_t VS_LOAD_BALANCING;
240 uint32_t VS_START_PC;
241 uint32_t PS_END_PC;
242 uint32_t PS_OUTPUT_REG;
243 uint32_t PS_INPUT_COUNT;
244 uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
245 uint32_t PS_TEMP_REGISTER_CONTROL;
246 uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
247 uint32_t PS_START_PC;
248 uint32_t GL_VARYING_TOTAL_COMPONENTS;
249 uint32_t GL_VARYING_NUM_COMPONENTS[2];
250 uint32_t GL_VARYING_COMPONENT_USE[2];
251 uint32_t GL_HALTI5_SH_SPECIALS;
252 uint32_t FE_HALTI5_ID_CONFIG;
253 unsigned vs_inst_mem_size;
254 unsigned ps_inst_mem_size;
255 uint32_t *VS_INST_MEM;
256 uint32_t *PS_INST_MEM;
257 struct etna_reloc PS_INST_ADDR;
258 struct etna_reloc VS_INST_ADDR;
259 unsigned writes_z:1;
260 unsigned uses_discard:1;
261 };
262
263 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
264 * field_size must be a power of two, and <= 32. */
265 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
266 uint32_t name[(num) * (field_size) / 32]
267
268 static inline void
etna_bitarray_set(uint32_t * array,size_t array_size,size_t field_size,size_t index,uint32_t value)269 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
270 size_t index, uint32_t value)
271 {
272 size_t shift = (index * field_size) % 32;
273 size_t offset = (index * field_size) / 32;
274
275 assert(index < array_size * 32 / field_size);
276 assert(value < 1 << field_size);
277
278 array[offset] |= value << shift;
279 }
280
281 #define etna_bitarray_set(array, field_size, index, value) \
282 etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
283
284 #endif
285