1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc2(size_t elements,const float * input,float * output,float * sum,float max)18 void xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc2(
19 size_t elements,
20 const float* input,
21 float* output,
22 float* sum,
23 float max) XNN_DISABLE_TSAN
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
28 // The smallest x for which expf(x) is normalized.
29 const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep6f);
30 const float32x4_t vlog2e = vmovq_n_f32(0x1.715476p+0f);
31 // Last 7 bits are zeroes
32 const float32x4_t vminus_ln2_hi = vmovq_n_f32(-0x1.62E400p-1f);
33 const float32x4_t vminus_ln2_lo = vmovq_n_f32(-0x1.7F7D1Cp-20f);
34
35 const float32x4_t vc1 = vmovq_n_f32(0x1.FFFFF6p-1f);
36 const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
37 const float32x4_t vc3 = vmovq_n_f32(0x1.555A80p-3f);
38 const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
39 const float32x4_t vc5 = vmovq_n_f32(0x1.0F9F9Cp-7f);
40
41 const float32x4_t vi_max = vdupq_n_f32(max);
42
43 float32x4_t vacc0 = vmovq_n_f32(0.0f);
44 float32x4_t vacc1 = vmovq_n_f32(0.0f);
45 for (; elements >= 20 * sizeof(float); elements -= 20 * sizeof(float)) {
46 // Load 20 (5x4) inputs at a time.
47 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
48 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
49 const float32x4_t vi89AB = vld1q_f32(input); input += 4;
50 const float32x4_t viCDEF = vld1q_f32(input); input += 4;
51 const float32x4_t viGHIJ = vld1q_f32(input); input += 4;
52
53 // Subtract maximum input x := i - i_max. This implies x <= 0.
54 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
55 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
56 const float32x4_t vx89AB = vsubq_f32(vi89AB, vi_max);
57 const float32x4_t vxCDEF = vsubq_f32(viCDEF, vi_max);
58 const float32x4_t vxGHIJ = vsubq_f32(viGHIJ, vi_max);
59
60 // Compute reduced argument n := round(x / log(2)).
61 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
62 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
63 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
64 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
65 // of the algorithm.
66 float32x4_t vn0123 = vmlaq_f32(vmagic_bias, vx0123, vlog2e);
67 float32x4_t vn4567 = vmlaq_f32(vmagic_bias, vx4567, vlog2e);
68 float32x4_t vn89AB = vmlaq_f32(vmagic_bias, vx89AB, vlog2e);
69 float32x4_t vnCDEF = vmlaq_f32(vmagic_bias, vxCDEF, vlog2e);
70 float32x4_t vnGHIJ = vmlaq_f32(vmagic_bias, vxGHIJ, vlog2e);
71
72 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
73 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
74 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
75 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
76 const float32x4_t vs89AB = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn89AB), 23));
77 const float32x4_t vsCDEF = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnCDEF), 23));
78 const float32x4_t vsGHIJ = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnGHIJ), 23));
79
80 // Subtract the large number back to get final n := round(x / log(2)).
81 vn0123 = vsubq_f32(vn0123, vmagic_bias);
82 vn4567 = vsubq_f32(vn4567, vmagic_bias);
83 vn89AB = vsubq_f32(vn89AB, vmagic_bias);
84 vnCDEF = vsubq_f32(vnCDEF, vmagic_bias);
85 vnGHIJ = vsubq_f32(vnGHIJ, vmagic_bias);
86
87 // Compute reduced argument t := z - n * log(2).
88 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
89 float32x4_t vt0123 = vmlaq_f32(vx0123, vn0123, vminus_ln2_hi);
90 float32x4_t vt4567 = vmlaq_f32(vx4567, vn4567, vminus_ln2_hi);
91 float32x4_t vt89AB = vmlaq_f32(vx89AB, vn89AB, vminus_ln2_hi);
92 float32x4_t vtCDEF = vmlaq_f32(vxCDEF, vnCDEF, vminus_ln2_hi);
93 float32x4_t vtGHIJ = vmlaq_f32(vxGHIJ, vnGHIJ, vminus_ln2_hi);
94
95 vt0123 = vmlaq_f32(vt0123, vn0123, vminus_ln2_lo);
96 vt4567 = vmlaq_f32(vt4567, vn4567, vminus_ln2_lo);
97 vt89AB = vmlaq_f32(vt89AB, vn89AB, vminus_ln2_lo);
98 vtCDEF = vmlaq_f32(vtCDEF, vnCDEF, vminus_ln2_lo);
99 vtGHIJ = vmlaq_f32(vtGHIJ, vnGHIJ, vminus_ln2_lo);
100
101 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
102 float32x4_t vp0123 = vmlaq_f32(vc4, vc5, vt0123);
103 float32x4_t vp4567 = vmlaq_f32(vc4, vc5, vt4567);
104 float32x4_t vp89AB = vmlaq_f32(vc4, vc5, vt89AB);
105 float32x4_t vpCDEF = vmlaq_f32(vc4, vc5, vtCDEF);
106 float32x4_t vpGHIJ = vmlaq_f32(vc4, vc5, vtGHIJ);
107
108 vp0123 = vmlaq_f32(vc3, vp0123, vt0123);
109 vp4567 = vmlaq_f32(vc3, vp4567, vt4567);
110 vp89AB = vmlaq_f32(vc3, vp89AB, vt89AB);
111 vpCDEF = vmlaq_f32(vc3, vpCDEF, vtCDEF);
112 vpGHIJ = vmlaq_f32(vc3, vpGHIJ, vtGHIJ);
113
114 vp0123 = vmlaq_f32(vc2, vp0123, vt0123);
115 vp4567 = vmlaq_f32(vc2, vp4567, vt4567);
116 vp89AB = vmlaq_f32(vc2, vp89AB, vt89AB);
117 vpCDEF = vmlaq_f32(vc2, vpCDEF, vtCDEF);
118 vpGHIJ = vmlaq_f32(vc2, vpGHIJ, vtGHIJ);
119
120 vp0123 = vmlaq_f32(vc1, vp0123, vt0123);
121 vp4567 = vmlaq_f32(vc1, vp4567, vt4567);
122 vp89AB = vmlaq_f32(vc1, vp89AB, vt89AB);
123 vpCDEF = vmlaq_f32(vc1, vpCDEF, vtCDEF);
124 vpGHIJ = vmlaq_f32(vc1, vpGHIJ, vtGHIJ);
125
126 // Reconstruct the final f value:
127 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
128 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
129 // = s + (t * s) * p
130 vt0123 = vmulq_f32(vt0123, vs0123);
131 vt4567 = vmulq_f32(vt4567, vs4567);
132 vt89AB = vmulq_f32(vt89AB, vs89AB);
133 vtCDEF = vmulq_f32(vtCDEF, vsCDEF);
134 vtGHIJ = vmulq_f32(vtGHIJ, vsGHIJ);
135
136 float32x4_t vf0123 = vmlaq_f32(vs0123, vp0123, vt0123);
137 float32x4_t vf4567 = vmlaq_f32(vs4567, vp4567, vt4567);
138 float32x4_t vf89AB = vmlaq_f32(vs89AB, vp89AB, vt89AB);
139 float32x4_t vfCDEF = vmlaq_f32(vsCDEF, vpCDEF, vtCDEF);
140 float32x4_t vfGHIJ = vmlaq_f32(vsGHIJ, vpGHIJ, vtGHIJ);
141
142 // For inputs below denormal cutoff, replace output with +0.0f.
143 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
144 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
145 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
146 vf89AB = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf89AB), vcltq_f32(vx89AB, vdenorm_cutoff)));
147 vfCDEF = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfCDEF), vcltq_f32(vxCDEF, vdenorm_cutoff)));
148 vfGHIJ = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfGHIJ), vcltq_f32(vxGHIJ, vdenorm_cutoff)));
149
150 // Store 20 (5x4) outputs at a time.
151 vst1q_f32(output, vf0123); output += 4;
152 vst1q_f32(output, vf4567); output += 4;
153 vst1q_f32(output, vf89AB); output += 4;
154 vst1q_f32(output, vfCDEF); output += 4;
155 vst1q_f32(output, vfGHIJ); output += 4;
156
157 // Accumulate computed exponents.
158 vacc0 = vaddq_f32(vacc0, vf0123);
159 vacc0 = vaddq_f32(vacc0, vf4567);
160 vacc0 = vaddq_f32(vacc0, vf89AB);
161 vacc0 = vaddq_f32(vacc0, vfCDEF);
162 vacc0 = vaddq_f32(vacc0, vfGHIJ);
163 }
164 // Add up all accumulators to vacc0
165 vacc0 = vaddq_f32(vacc0, vacc1);
166
167 float32x4_t vacc = vacc0;
168 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
169 // Load 4 inputs at a time.
170 const float32x4_t vi = vld1q_f32(input); input += 4;
171
172 // Subtract maximum input x := i - i_max. This implies x <= 0.
173 const float32x4_t vx = vsubq_f32(vi, vi_max);
174
175 // Compute reduced argument n := round(x / log(2)).
176 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
177 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
178 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
179 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
180 // of the algorithm.
181 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
182
183 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
184 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
185 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
186
187 // Subtract the large number back to get final n := round(x / log(2)).
188 vn = vsubq_f32(vn, vmagic_bias);
189
190 // Compute reduced argument t := z - n * log(2).
191 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
192 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
193 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
194
195 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
196 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
197 vp = vmlaq_f32(vc3, vp, vt);
198 vp = vmlaq_f32(vc2, vp, vt);
199 vp = vmlaq_f32(vc1, vp, vt);
200
201 // Reconstruct the final f value:
202 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
203 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
204 // = s + (t * s) * p
205 vt = vmulq_f32(vt, vs);
206 float32x4_t vf = vmlaq_f32(vs, vp, vt);
207
208 // For inputs below denormal cutoff, replace output with +0.0f.
209 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
210 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
211
212 // Store 4 outputs at a time.
213 vst1q_f32(output, vf); output += 4;
214
215 // Accumulate computed exponents.
216 vacc = vaddq_f32(vacc, vf);
217 }
218 #if XNN_ARCH_ARM64
219 float vacc_lo = vaddvq_f32(vacc);
220 #else
221 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
222 #endif
223 if (elements != 0) {
224 assert(elements >= 1 * sizeof(float));
225 assert(elements <= 3 * sizeof(float));
226 // Load 4 inputs at a time.
227 const float32x4_t vi = vld1q_f32(input); input += 4;
228
229 // Subtract maximum input x := i - i_max. This implies x <= 0.
230 const float32x4_t vx = vsubq_f32(vi, vi_max);
231
232 // Compute reduced argument n := round(x / log(2)).
233 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
234 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
235 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
236 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
237 // of the algorithm.
238 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
239
240 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
241 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
242 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
243
244 // Subtract the large number back to get final n := round(x / log(2)).
245 vn = vsubq_f32(vn, vmagic_bias);
246
247 // Compute reduced argument t := z - n * log(2).
248 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
249 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
250 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
251
252 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
253 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
254 vp = vmlaq_f32(vc3, vp, vt);
255 vp = vmlaq_f32(vc2, vp, vt);
256 vp = vmlaq_f32(vc1, vp, vt);
257
258 // Reconstruct the final f value:
259 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
260 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
261 // = s + (t * s) * p
262 vt = vmulq_f32(vt, vs);
263 float32x4_t vf = vmlaq_f32(vs, vp, vt);
264
265 // For inputs below denormal cutoff, replace output with +0.0f.
266 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
267 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
268
269 float32x2_t vf_lo = vget_low_f32(vf);
270 if (elements & (2 * sizeof(float))) {
271 // Store 2 outputs at a time.
272 vst1_f32(output, vf_lo); output += 2;
273
274 // Accumulate 2 computed exponents.
275 #if XNN_ARCH_ARM64
276 vacc_lo += vaddv_f32(vf_lo);
277 #else
278 vacc_lo = vadd_f32(vacc_lo, vf_lo);
279 #endif
280
281 vf_lo = vget_high_f32(vf);
282 }
283 if (elements & (1 * sizeof(float))) {
284 // Store 1 output at a time.
285 vst1_lane_f32(output, vf_lo, 0);
286
287 // Accumulate 1 computed exponent.
288 #if XNN_ARCH_ARM64
289 vacc_lo += vget_lane_f32(vf_lo, 0);
290 #else
291 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
292 #endif
293 }
294 }
295 // Reduce 4 elements in the SIMD register
296 #if XNN_ARCH_ARM64
297 *sum = vacc_lo;
298 #else
299 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
300 #endif
301 }
302