1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8_acc2(size_t elements,const float * input,float * output,float * sum,float max)18 void xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8_acc2(
19 size_t elements,
20 const float* input,
21 float* output,
22 float* sum,
23 float max) XNN_DISABLE_TSAN
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
28 // The smallest x for which expf(x) is normalized.
29 const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep6f);
30 const float32x4_t vlog2e = vmovq_n_f32(0x1.715476p+0f);
31 // Last 7 bits are zeroes
32 const float32x4_t vminus_ln2_hi = vmovq_n_f32(-0x1.62E400p-1f);
33 const float32x4_t vminus_ln2_lo = vmovq_n_f32(-0x1.7F7D1Cp-20f);
34
35 const float32x4_t vc1 = vmovq_n_f32(0x1.FFFFF6p-1f);
36 const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
37 const float32x4_t vc3 = vmovq_n_f32(0x1.555A80p-3f);
38 const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
39 const float32x4_t vc5 = vmovq_n_f32(0x1.0F9F9Cp-7f);
40
41 const float32x4_t vi_max = vdupq_n_f32(max);
42
43 float32x4_t vacc0 = vmovq_n_f32(0.0f);
44 float32x4_t vacc1 = vmovq_n_f32(0.0f);
45 for (; elements >= 8 * sizeof(float); elements -= 8 * sizeof(float)) {
46 // Load 8 (2x4) inputs at a time.
47 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
48 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
49
50 // Subtract maximum input x := i - i_max. This implies x <= 0.
51 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
52 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
53
54 // Compute reduced argument n := round(x / log(2)).
55 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
56 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
57 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
58 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
59 // of the algorithm.
60 float32x4_t vn0123 = vmlaq_f32(vmagic_bias, vx0123, vlog2e);
61 float32x4_t vn4567 = vmlaq_f32(vmagic_bias, vx4567, vlog2e);
62
63 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
64 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
65 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
66 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
67
68 // Subtract the large number back to get final n := round(x / log(2)).
69 vn0123 = vsubq_f32(vn0123, vmagic_bias);
70 vn4567 = vsubq_f32(vn4567, vmagic_bias);
71
72 // Compute reduced argument t := z - n * log(2).
73 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
74 float32x4_t vt0123 = vmlaq_f32(vx0123, vn0123, vminus_ln2_hi);
75 float32x4_t vt4567 = vmlaq_f32(vx4567, vn4567, vminus_ln2_hi);
76
77 vt0123 = vmlaq_f32(vt0123, vn0123, vminus_ln2_lo);
78 vt4567 = vmlaq_f32(vt4567, vn4567, vminus_ln2_lo);
79
80 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
81 float32x4_t vp0123 = vmlaq_f32(vc4, vc5, vt0123);
82 float32x4_t vp4567 = vmlaq_f32(vc4, vc5, vt4567);
83
84 vp0123 = vmlaq_f32(vc3, vp0123, vt0123);
85 vp4567 = vmlaq_f32(vc3, vp4567, vt4567);
86
87 vp0123 = vmlaq_f32(vc2, vp0123, vt0123);
88 vp4567 = vmlaq_f32(vc2, vp4567, vt4567);
89
90 vp0123 = vmlaq_f32(vc1, vp0123, vt0123);
91 vp4567 = vmlaq_f32(vc1, vp4567, vt4567);
92
93 // Reconstruct the final f value:
94 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
95 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
96 // = s + (t * s) * p
97 vt0123 = vmulq_f32(vt0123, vs0123);
98 vt4567 = vmulq_f32(vt4567, vs4567);
99
100 float32x4_t vf0123 = vmlaq_f32(vs0123, vp0123, vt0123);
101 float32x4_t vf4567 = vmlaq_f32(vs4567, vp4567, vt4567);
102
103 // For inputs below denormal cutoff, replace output with +0.0f.
104 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
105 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
106 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
107
108 // Store 8 (2x4) outputs at a time.
109 vst1q_f32(output, vf0123); output += 4;
110 vst1q_f32(output, vf4567); output += 4;
111
112 // Accumulate computed exponents.
113 vacc0 = vaddq_f32(vacc0, vf0123);
114 vacc0 = vaddq_f32(vacc0, vf4567);
115 }
116 // Add up all accumulators to vacc0
117 vacc0 = vaddq_f32(vacc0, vacc1);
118
119 float32x4_t vacc = vacc0;
120 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
121 // Load 4 inputs at a time.
122 const float32x4_t vi = vld1q_f32(input); input += 4;
123
124 // Subtract maximum input x := i - i_max. This implies x <= 0.
125 const float32x4_t vx = vsubq_f32(vi, vi_max);
126
127 // Compute reduced argument n := round(x / log(2)).
128 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
129 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
130 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
131 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
132 // of the algorithm.
133 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
134
135 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
136 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
137 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
138
139 // Subtract the large number back to get final n := round(x / log(2)).
140 vn = vsubq_f32(vn, vmagic_bias);
141
142 // Compute reduced argument t := z - n * log(2).
143 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
144 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
145 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
146
147 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
148 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
149 vp = vmlaq_f32(vc3, vp, vt);
150 vp = vmlaq_f32(vc2, vp, vt);
151 vp = vmlaq_f32(vc1, vp, vt);
152
153 // Reconstruct the final f value:
154 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
155 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
156 // = s + (t * s) * p
157 vt = vmulq_f32(vt, vs);
158 float32x4_t vf = vmlaq_f32(vs, vp, vt);
159
160 // For inputs below denormal cutoff, replace output with +0.0f.
161 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
162 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
163
164 // Store 4 outputs at a time.
165 vst1q_f32(output, vf); output += 4;
166
167 // Accumulate computed exponents.
168 vacc = vaddq_f32(vacc, vf);
169 }
170 #if XNN_ARCH_ARM64
171 float vacc_lo = vaddvq_f32(vacc);
172 #else
173 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
174 #endif
175 if (elements != 0) {
176 assert(elements >= 1 * sizeof(float));
177 assert(elements <= 3 * sizeof(float));
178 // Load 4 inputs at a time.
179 const float32x4_t vi = vld1q_f32(input); input += 4;
180
181 // Subtract maximum input x := i - i_max. This implies x <= 0.
182 const float32x4_t vx = vsubq_f32(vi, vi_max);
183
184 // Compute reduced argument n := round(x / log(2)).
185 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
186 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
187 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
188 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
189 // of the algorithm.
190 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
191
192 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
193 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
194 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
195
196 // Subtract the large number back to get final n := round(x / log(2)).
197 vn = vsubq_f32(vn, vmagic_bias);
198
199 // Compute reduced argument t := z - n * log(2).
200 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
201 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
202 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
203
204 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
205 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
206 vp = vmlaq_f32(vc3, vp, vt);
207 vp = vmlaq_f32(vc2, vp, vt);
208 vp = vmlaq_f32(vc1, vp, vt);
209
210 // Reconstruct the final f value:
211 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
212 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
213 // = s + (t * s) * p
214 vt = vmulq_f32(vt, vs);
215 float32x4_t vf = vmlaq_f32(vs, vp, vt);
216
217 // For inputs below denormal cutoff, replace output with +0.0f.
218 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
219 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
220
221 float32x2_t vf_lo = vget_low_f32(vf);
222 if (elements & (2 * sizeof(float))) {
223 // Store 2 outputs at a time.
224 vst1_f32(output, vf_lo); output += 2;
225
226 // Accumulate 2 computed exponents.
227 #if XNN_ARCH_ARM64
228 vacc_lo += vaddv_f32(vf_lo);
229 #else
230 vacc_lo = vadd_f32(vacc_lo, vf_lo);
231 #endif
232
233 vf_lo = vget_high_f32(vf);
234 }
235 if (elements & (1 * sizeof(float))) {
236 // Store 1 output at a time.
237 vst1_lane_f32(output, vf_lo, 0);
238
239 // Accumulate 1 computed exponent.
240 #if XNN_ARCH_ARM64
241 vacc_lo += vget_lane_f32(vf_lo, 0);
242 #else
243 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
244 #endif
245 }
246 }
247 // Reduce 4 elements in the SIMD register
248 #if XNN_ARCH_ARM64
249 *sum = vacc_lo;
250 #else
251 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
252 #endif
253 }
254