1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x4(size_t elements,const float * input,float * output,float * sum,float max)18 void xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x4(
19 size_t elements,
20 const float* input,
21 float* output,
22 float* sum,
23 float max) XNN_DISABLE_TSAN
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
28 // The smallest x for which expf(x) is normalized.
29 const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep6f);
30 const float32x4_t vlog2e = vmovq_n_f32(0x1.715476p+0f);
31 const float32x4_t vminus_ln2_hi = vmovq_n_f32(-0x1.62E43p-1f);
32 const float32x4_t vminus_ln2_lo = vmovq_n_f32(0x1.05C61p-29f);
33
34 const float32x4_t vc1 = vmovq_n_f32(0x1.FFFFF6p-1f);
35 const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
36 const float32x4_t vc3 = vmovq_n_f32(0x1.555A80p-3f);
37 const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
38 const float32x4_t vc5 = vmovq_n_f32(0x1.0F9F9Cp-7f);
39
40 const float32x4_t vi_max = vdupq_n_f32(max);
41
42 float32x4_t vacc = vmovq_n_f32(0.0f);
43 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
44 // Load 4 inputs at a time.
45 const float32x4_t vi = vld1q_f32(input); input += 4;
46
47 // Subtract maximum input x := i - i_max. This implies x <= 0.
48 const float32x4_t vx = vsubq_f32(vi, vi_max);
49
50 // Compute reduced argument n := round(x / log(2)).
51 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
52 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
53 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
54 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
55 // of the algorithm.
56 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
57
58 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
59 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
60 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
61
62 // Subtract the large number back to get final n := round(x / log(2)).
63 vn = vsubq_f32(vn, vmagic_bias);
64
65 // Compute reduced argument t := z - n * log(2).
66 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
67 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2_hi);
68 vt = vfmaq_f32(vt, vn, vminus_ln2_lo);
69
70 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
71 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
72 vp = vfmaq_f32(vc3, vp, vt);
73 vp = vfmaq_f32(vc2, vp, vt);
74 vp = vfmaq_f32(vc1, vp, vt);
75
76 // Reconstruct the final f value:
77 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
78 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
79 // = s + (t * s) * p
80 vt = vmulq_f32(vt, vs);
81 float32x4_t vf = vfmaq_f32(vs, vp, vt);
82
83 // For inputs below denormal cutoff, replace output with +0.0f.
84 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
85 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
86
87 // Store 4 outputs at a time.
88 vst1q_f32(output, vf); output += 4;
89
90 // Accumulate computed exponents.
91 vacc = vaddq_f32(vacc, vf);
92 }
93 #if XNN_ARCH_ARM64
94 float vacc_lo = vaddvq_f32(vacc);
95 #else
96 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
97 #endif
98 if (elements != 0) {
99 assert(elements >= 1 * sizeof(float));
100 assert(elements <= 3 * sizeof(float));
101 // Load 4 inputs at a time.
102 const float32x4_t vi = vld1q_f32(input); input += 4;
103
104 // Subtract maximum input x := i - i_max. This implies x <= 0.
105 const float32x4_t vx = vsubq_f32(vi, vi_max);
106
107 // Compute reduced argument n := round(x / log(2)).
108 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
109 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
110 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
111 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
112 // of the algorithm.
113 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
114
115 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
116 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
117 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
118
119 // Subtract the large number back to get final n := round(x / log(2)).
120 vn = vsubq_f32(vn, vmagic_bias);
121
122 // Compute reduced argument t := z - n * log(2).
123 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
124 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2_hi);
125 vt = vfmaq_f32(vt, vn, vminus_ln2_lo);
126
127 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
128 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
129 vp = vfmaq_f32(vc3, vp, vt);
130 vp = vfmaq_f32(vc2, vp, vt);
131 vp = vfmaq_f32(vc1, vp, vt);
132
133 // Reconstruct the final f value:
134 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
135 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
136 // = s + (t * s) * p
137 vt = vmulq_f32(vt, vs);
138 float32x4_t vf = vfmaq_f32(vs, vp, vt);
139
140 // For inputs below denormal cutoff, replace output with +0.0f.
141 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
142 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
143
144 float32x2_t vf_lo = vget_low_f32(vf);
145 if (elements & (2 * sizeof(float))) {
146 // Store 2 outputs at a time.
147 vst1_f32(output, vf_lo); output += 2;
148
149 // Accumulate 2 computed exponents.
150 #if XNN_ARCH_ARM64
151 vacc_lo += vaddv_f32(vf_lo);
152 #else
153 vacc_lo = vadd_f32(vacc_lo, vf_lo);
154 #endif
155
156 vf_lo = vget_high_f32(vf);
157 }
158 if (elements & (1 * sizeof(float))) {
159 // Store 1 output at a time.
160 vst1_lane_f32(output, vf_lo, 0);
161
162 // Accumulate 1 computed exponent.
163 #if XNN_ARCH_ARM64
164 vacc_lo += vget_lane_f32(vf_lo, 0);
165 #else
166 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
167 #endif
168 }
169 }
170 // Reduce 4 elements in the SIMD register
171 #if XNN_ARCH_ARM64
172 *sum = vacc_lo;
173 #else
174 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
175 #endif
176 }
177