1 // Copyright (c) Facebook, Inc. and its affiliates.
2 // All rights reserved.
3 //
4 // Copyright 2019 Google LLC
5 //
6 // This source code is licensed under the BSD-style license found in the
7 // LICENSE file in the root directory of this source tree.
8
9 #include <assert.h>
10 #include <stdint.h>
11 #include <stddef.h>
12
13 #include <arm_neon.h>
14
15 #include <fp16/bitcasts.h>
16
17 #include <xnnpack/requantization-stubs.h>
18
19
xnn_qs8_requantize_q31__neon(size_t n,const int32_t * input,float scale,int8_t zero_point,int8_t qmin,int8_t qmax,int8_t * output)20 void xnn_qs8_requantize_q31__neon(
21 size_t n,
22 const int32_t* input,
23 float scale,
24 int8_t zero_point,
25 int8_t qmin,
26 int8_t qmax,
27 int8_t* output)
28 {
29 assert(n % 16 == 0);
30 assert(scale < 1.0f);
31 assert(scale >= 0x1.0p-32f);
32
33 // Compute requantization parameters.
34 const uint32_t scale_bits = fp32_to_bits(scale);
35
36 // Multiplier is in [0x40000000, 0x7FFFFF80] range.
37 const int32_t multiplier = (int32_t)(((scale_bits & UINT32_C(0x007FFFFF)) | UINT32_C(0x00800000)) << 7);
38 assert(multiplier >= INT32_C(0x40000000));
39 assert(multiplier <= INT32_C(0x7FFFFF80));
40
41 // Shift is in [0, 31] range.
42 const int32_t shift = 127 + 31 - 32 - (fp32_to_bits(scale) >> 23);
43 assert(shift >= 0);
44 assert(shift < 32);
45
46 const int32x4_t vmultiplier = vdupq_n_s32(multiplier);
47 const int16x8_t vzero_point = vdupq_n_s16((int16_t) zero_point);
48 const int32x4_t vshift = vdupq_n_s32(-shift);
49 const int32x4_t vshift_eq_0_mask = vreinterpretq_s32_u32(vceqq_s32(vshift, vmovq_n_s32(0)));
50 const int8x16_t vqmin = vdupq_n_s8(qmin);
51 const int8x16_t vqmax = vdupq_n_s8(qmax);
52 for (; n != 0; n -= 16) {
53 const int32x4_t x = vld1q_s32(input);
54 const int32x4_t y = vld1q_s32(input + 4);
55 const int32x4_t z = vld1q_s32(input + 8);
56 const int32x4_t w = vld1q_s32(input + 12);
57 input += 16;
58
59 // Directly use VQRDMULH/SQRDMULH instruction for Q31 multiplication with rounding.
60 // Although these instruction saturate out-of-range outputs, we never hit this case in requantization.
61 const int32x4_t x_product = vqrdmulhq_s32(x, vmultiplier);
62 const int32x4_t y_product = vqrdmulhq_s32(y, vmultiplier);
63 const int32x4_t z_product = vqrdmulhq_s32(z, vmultiplier);
64 const int32x4_t w_product = vqrdmulhq_s32(w, vmultiplier);
65
66 // Shift the 32-bit product right with rounding.
67 // Rounding is performed towards closest integer, with midpoints rounded up (same as away from zero).
68 //
69 // We leverage the "right shift with rounding" instruction (VRSHL.S32 on ARM NEON, SRSHL in ARM64 Advanced SIMD) to
70 // do the shift. However, as this instruction rounds midpoints up, rather than away from zero, we adjust the input
71 // by subtracting 1 from negative values, but only if shift is non-zero.
72 const int32x4_t x_adjusted_product = vsraq_n_s32(x_product, vbicq_s32(x, vshift_eq_0_mask), 31);
73 const int32x4_t y_adjusted_product = vsraq_n_s32(y_product, vbicq_s32(y, vshift_eq_0_mask), 31);
74 const int32x4_t z_adjusted_product = vsraq_n_s32(z_product, vbicq_s32(z, vshift_eq_0_mask), 31);
75 const int32x4_t w_adjusted_product = vsraq_n_s32(w_product, vbicq_s32(w, vshift_eq_0_mask), 31);
76
77 const int32x4_t x_scaled = vrshlq_s32(x_adjusted_product, vshift);
78 const int32x4_t y_scaled = vrshlq_s32(y_adjusted_product, vshift);
79 const int32x4_t z_scaled = vrshlq_s32(z_adjusted_product, vshift);
80 const int32x4_t w_scaled = vrshlq_s32(w_adjusted_product, vshift);
81
82 #ifdef __aarch64__
83 const int16x8_t xy_packed = vqaddq_s16(vqmovn_high_s32(vqmovn_s32(x_scaled), y_scaled), vzero_point);
84 const int16x8_t zw_packed = vqaddq_s16(vqmovn_high_s32(vqmovn_s32(z_scaled), w_scaled), vzero_point);
85 const int8x16_t xyzw_packed = vqmovn_high_s16(vqmovn_s16(xy_packed), zw_packed);
86 #else
87 const int16x8_t xy_packed = vqaddq_s16(vcombine_s16(vqmovn_s32(x_scaled), vqmovn_s32(y_scaled)), vzero_point);
88 const int16x8_t zw_packed = vqaddq_s16(vcombine_s16(vqmovn_s32(z_scaled), vqmovn_s32(w_scaled)), vzero_point);
89 const int8x16_t xyzw_packed = vcombine_s8(vqmovn_s16(xy_packed), vqmovn_s16(zw_packed));
90 #endif
91
92 const int8x16_t xyzw_clamped = vmaxq_s8(vminq_s8(xyzw_packed, vqmax), vqmin);
93
94 // AArch32 version:
95 // 4x VQRDMULH.S32 Qd, Qm, Qn
96 // 4x VAND Qd, Qm, Dn
97 // 4x VSRA.S32 Qd, Qm, #31
98 // 4x VRSHL.S32 Qd, Qm, Qn
99 // 4x VQMOVN.S32 Dd, Qm
100 // 2x VADD.S16 Qd, Qm, Qn
101 // 2x VQMOVN.S16 Dd, Qm
102 // 1x VMAX.S8 Qd, Qm, Qn
103 // 1x VMIN.S8 Qd, Qm, Qn
104 // ---------------------
105 // 26 instructions total
106 //
107 // AArch64 version:
108 // 4x SQRDMULH Vd.4S, Vn.4S, Vm.4S
109 // 4x AND Vd.16B, Vn.16B, Vm.16B
110 // 4x SSRA Vd.4S, Vn.4S, #31
111 // 4x SRSHL Vd.4S, Vn.4S, Vm.4S
112 // 2x SQXTN Vd.4H, Vn.4S
113 // 2x SQXTN2 Vd.8H, Vn.4S
114 // 2x ADD Vd.8H, Vn.8H, Vm.8H
115 // 1x SQXTN Vd.8B, Vn.8H
116 // 1x SQXTN2 Vd.16B, Vn.8H
117 // 1x SMIN Vd.16B, Vn.16B, Vm.16B
118 // 1x SMAX Vd.16B, Vn.16B, Vm.16B
119 // ---------------------
120 // 26 instructions total
121
122 vst1q_s8(output, xyzw_clamped);
123 output += 16;
124 }
125 }
126