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Searched defs:zdn (Results 1 – 5 of 5) sorted by relevance

/external/vixl/src/aarch64/
Dassembler-sve-aarch64.cc86 void Assembler::SVELogicalImmediate(const ZRegister& zdn, in SVELogicalImmediate()
169 const ZRegister& zdn, in SVEBitwiseShiftImmediatePred()
1422 void Assembler::fmad(const ZRegister& zdn, in fmad()
1467 void Assembler::fmsb(const ZRegister& zdn, in fmsb()
1482 void Assembler::fnmad(const ZRegister& zdn, in fnmad()
1527 void Assembler::fnmsb(const ZRegister& zdn, in fnmsb()
2014 void Assembler::decp(const ZRegister& zdn, const PRegister& pg) { in decp()
2039 void Assembler::incp(const ZRegister& zdn, const PRegister& pg) { in incp()
2079 void Assembler::sqdecp(const ZRegister& zdn, const PRegister& pg) { in sqdecp()
2118 void Assembler::sqincp(const ZRegister& zdn, const PRegister& pg) { in sqincp()
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Dsimulator-aarch64.cc7443 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEBitwiseShiftByImm_Predicated() local
7492 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEBitwiseShiftByVector_Predicated() local
7541 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEBitwiseShiftByWideElements_Predicated() local
7861 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEFPArithmetic_Predicated() local
7921 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEFPArithmeticWithImm_Predicated() local
8096 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEFPComplexAddition() local
8615 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEIncDecByPredicateCount() local
8778 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEIntAddSubtractVectors_Predicated() local
8802 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEBitwiseLogical_Predicated() local
8829 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEIntMulVectors_Predicated() local
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Dmacro-assembler-aarch64.h4034 void Decp(const ZRegister& zdn, const PRegister& pg) { Decp(zdn, pg, zdn); } in Decp()
4378 void Fmad(const ZRegister& zdn, in Fmad()
4510 void Fmsb(const ZRegister& zdn, in Fmsb()
4758 void Incp(const ZRegister& zdn, const PRegister& pg) { Incp(zdn, pg, zdn); } in Incp()
4770 void Insr(const ZRegister& zdn, const Register& rm) { in Insr()
4775 void Insr(const ZRegister& zdn, const VRegister& vm) { in Insr()
5744 void Sqdecp(const ZRegister& zdn, const PRegister& pg) { in Sqdecp()
5833 void Sqincp(const ZRegister& zdn, const PRegister& pg) { in Sqincp()
6168 void Uqdecp(const ZRegister& zdn, const PRegister& pg) { in Uqdecp()
6232 void Uqincp(const ZRegister& zdn, const PRegister& pg) { in Uqincp()
Dmacro-assembler-sve-aarch64.cc879 void MacroAssembler::Insr(const ZRegister& zdn, IntegerOperand imm) { in Insr()
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc110 const ZRegister& zdn, in InsrHelper()