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Searched defs:zm (Results 1 – 7 of 7) sorted by relevance

/external/vixl/src/aarch64/
Dassembler-sve-aarch64.cc132 const ZRegister& zm) { in and_()
141 const ZRegister& zm) { in bic()
150 const ZRegister& zm) { in eor()
159 const ZRegister& zm) { in orr()
199 const ZRegister& zm) { in asr()
239 const ZRegister& zm) { in asrr()
274 const ZRegister& zm) { in lsl()
296 const ZRegister& zm) { in lslr()
331 const ZRegister& zm) { in lsr()
353 const ZRegister& zm) { in lsrr()
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Dmacro-assembler-sve-aarch64.cc505 const ZRegister& zm, in NoncommutativeArithmeticHelper()
527 const ZRegister& zm, in FPCommutativeArithmeticHelper()
568 const ZRegister& zm) { in Asr()
583 const ZRegister& zm) { in Lsl()
598 const ZRegister& zm) { in Lsr()
613 const ZRegister& zm) { in Fdiv()
628 const ZRegister& zm) { in Fsub()
643 const ZRegister& zm, in Fadd()
658 const ZRegister& zm, in Fabd()
673 const ZRegister& zm, in Fmul()
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Dmacro-assembler-aarch64.h3480 void Add(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Add()
3515 void And(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in And()
3551 void Asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Asr()
3572 void Bic(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Bic()
3681 const ZRegister& zm) { in Clasta()
3689 const ZRegister& zm) { in Clasta()
3701 const ZRegister& zm) { in Clastb()
3709 const ZRegister& zm) { in Clastb()
3731 const ZRegister& zm) { in Cmpeq()
3752 const ZRegister& zm) { in Cmpge()
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Dsimulator-aarch64.cc7342 SimVRegister& zm = ReadVRegister(instr->GetRm()); in VisitSVEAddressGeneration() local
7415 SimVRegister& zm = ReadVRegister(instr->GetRm()); in VisitSVEBitwiseLogicalUnpredicated() local
7493 SimVRegister& zm = ReadVRegister(instr->GetRn()); in VisitSVEBitwiseShiftByVector_Predicated() local
7542 SimVRegister& zm = ReadVRegister(instr->GetRn()); in VisitSVEBitwiseShiftByWideElements_Predicated() local
7846 SimVRegister& zm = ReadVRegister(instr->GetRn()); in VisitSVEFPAccumulatingReduction() local
7862 SimVRegister& zm = ReadVRegister(instr->GetRn()); in VisitSVEFPArithmetic_Predicated() local
7969 SimVRegister& zm = ReadVRegister(instr->GetRn()); in VisitSVEFPTrigMulAddCoefficient() local
7985 SimVRegister& zm = ReadVRegister(instr->GetRm()); in VisitSVEFPArithmeticUnpredicated() local
8015 SimVRegister& zm = ReadVRegister(instr->GetRm()); in VisitSVEFPCompareVectors() local
8097 SimVRegister& zm = ReadVRegister(instr->GetRn()); in VisitSVEFPComplexAddition() local
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Dlogic-aarch64.cc6881 const LogicVRegister& zm) { in SVEBitwiseLogicalUnpredicatedHelper()
/external/mesa3d/src/gallium/drivers/zink/
Dzink_program.c117 zink_destroy_shader_module(struct zink_screen *screen, struct zink_shader_module *zm) in zink_destroy_shader_module()
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc448 ZRegister zm = z3.WithLaneSize(lane_size_in_bits); in MlaMlsHelper() local
5111 ZRegister zm = z27.WithLaneSize(lane_size_in_bits); in IntArithHelper() local
11685 int index) { in SdotUdotHelper()
11704 ZRegister zm = z3.WithLaneSize(lane_size_in_bits / 4); in SdotUdotHelper() local
12168 ZRegister zm = z31.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12354 ZRegister zm = z28.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12865 ZRegister zm = z28.WithLaneSize(kDRegSize); in BitwiseShiftWideElementsHelper() local
16714 ZRegister zm = z3.WithLaneSize(lane_size_in_bits); in FPMulAccHelper() local
17926 double zm[] = {-0.0, inf_n, inf_n, -2.0, inf_n, nan, nan, inf_p}; in TEST_SVE() local