| /external/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 100 void Assembler::and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in and_()
115 void Assembler::eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in eor()
122 void Assembler::orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in orr()
131 const ZRegister& zn, in and_()
140 const ZRegister& zn, in bic()
149 const ZRegister& zn, in eor()
158 const ZRegister& zn, in orr()
181 const ZRegister& zn, in asr()
198 const ZRegister& zn, in asr()
220 const ZRegister& zn, in asrd()
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| D | macro-assembler-sve-aarch64.cc | 34 const ZRegister& zn, in AddSubHelper()
71 const ZRegister& zn, in TrySingleAddSub()
95 const ZRegister& zn, in IntWideImmHelper()
130 const ZRegister& zn, in Mul()
139 const ZRegister& zn, in Smin()
149 const ZRegister& zn, in Smax()
159 const ZRegister& zn, in Umax()
169 const ZRegister& zn, in Umin()
504 const ZRegister& zn, in NoncommutativeArithmeticHelper()
526 const ZRegister& zn, in FPCommutativeArithmeticHelper()
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| D | macro-assembler-aarch64.h | 3475 void Abs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Abs()
3480 void Add(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Add()
3485 void Add(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) { in Add()
3505 void And(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in And()
3515 void And(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in And()
3529 void Andv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) { in Andv()
3536 const ZRegister& zn, in Asr()
3546 void Asr(const ZRegister& zd, const ZRegister& zn, int shift) { in Asr()
3551 void Asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Asr()
3558 const ZRegister& zn, in Asrd()
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| D | simulator-aarch64.cc | 7341 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEAddressGeneration() local
7414 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEBitwiseLogicalUnpredicated() local
7572 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEBitwiseShiftUnpredicated() local
7984 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEFPArithmeticUnpredicated() local
8014 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEFPCompareVectors() local
8053 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEFPCompareWithZero() local
8122 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEFPComplexMulAdd() local
8142 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEFPComplexMulAddIndex() local
8180 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEFPFastReduction() local
8245 SimVRegister& zn = ReadVRegister(instr->GetRn()); in VisitSVEFPMulIndex() local
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| D | logic-aarch64.cc | 6880 const LogicVRegister& zn, in SVEBitwiseLogicalUnpredicatedHelper()
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| /external/llvm-project/flang/test/Semantics/ |
| D | modfile20.f90 | 12 complex*16, parameter :: zn = (-1.0_k8, 2.0_k8) variable
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| /external/bzip2/ |
| D | decompress.c | 130 Int32 zn; in BZ2_decompress() local
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| /external/icu/android_icu4j/src/main/tests/android/icu/dev/test/calendar/ |
| D | CompatibilityTest.java | 783 TransitionItem(String zn, int y, int m, int d, int h) { in TestAddAcrossOffsetTransitions()
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| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/calendar/ |
| D | CompatibilityTest.java | 780 TransitionItem(String zn, int y, int m, int d, int h) { in TestAddAcrossOffsetTransitions()
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| /external/deqp/modules/internal/ |
| D | ditFrameworkTests.cpp | 706 const float zn = 0.0f; in runCase() local
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| /external/deqp/framework/referencerenderer/ |
| D | rrRenderState.hpp | 338 float zn; member
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| D | rrRenderer.cpp | 829 const float zn = state.viewport.zn; in transformVertexClipCoordsToWindowCoords() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 447 ZRegister zn = z2.WithLaneSize(lane_size_in_bits); in MlaMlsHelper() local
5110 ZRegister zn = z31.WithLaneSize(lane_size_in_bits); in IntArithHelper() local
9913 ZRegister zn = z0.WithLaneSize(esize_in_bits); in GatherLoadScalarPlusVectorHelper() local
10029 ZRegister zn = z0.WithLaneSize(esize_in_bits); in GatherLoadScalarPlusScalarOrImmHelper() local
10850 ZRegister zn = z1.WithLaneSize(lane_size_in_bits); in IntWideImmHelper() local
11685 int index) { in SdotUdotHelper()
11703 ZRegister zn = z2.WithLaneSize(lane_size_in_bits / 4); in SdotUdotHelper() local
12167 ZRegister zn = z30.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12353 ZRegister zn = z27.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12750 ZRegister zn = z28.WithLaneSize(lane_size_in_bits); in BitwiseShiftImmHelper() local
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| /external/icu/icu4c/source/tools/tzcode/ |
| D | tz2icu.cpp | 1830 int32_t zn = 0; in main() local
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| /external/llvm-project/llvm/unittests/ADT/ |
| D | APFloatTest.cpp | 589 APFloat zn(-0.0); in TEST() local
604 APFloat zn(-0.0); in TEST() local
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| /external/swiftshader/src/Pipeline/ |
| D | SamplerCore.cpp | 1320 Int4 zn = CmpLT(z, Float4(0.0f)); // z < 0 in cubeFace() local
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| /external/swiftshader/src/Shader/ |
| D | SamplerCore.cpp | 1582 Int4 zn = CmpLT(z, Float4(0.0f)); // z < 0 in cubeFace() local
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