1 /*
2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdbool.h>
8 #include <string.h>
9
10 #include <common/debug.h>
11 #include <drivers/generic_delay_timer.h>
12 #include <lib/mmio.h>
13 #include <lib/xlat_tables/xlat_tables.h>
14 #include <plat_ipi.h>
15 #include <plat_private.h>
16 #include <plat/common/platform.h>
17
18 #include "pm_api_sys.h"
19
20 /*
21 * Table of regions to map using the MMU.
22 * This doesn't include TZRAM as the 'mem_layout' argument passed to
23 * configure_mmu_elx() will give the available subset of that,
24 */
25 const mmap_region_t plat_arm_mmap[] = {
26 { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
27 { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
28 { CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
29 {0}
30 };
31
zynqmp_get_silicon_ver(void)32 static unsigned int zynqmp_get_silicon_ver(void)
33 {
34 static unsigned int ver;
35
36 if (!ver) {
37 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
38 ZYNQMP_CSU_VERSION_OFFSET);
39 ver &= ZYNQMP_SILICON_VER_MASK;
40 ver >>= ZYNQMP_SILICON_VER_SHIFT;
41 }
42
43 return ver;
44 }
45
zynqmp_get_uart_clk(void)46 unsigned int zynqmp_get_uart_clk(void)
47 {
48 unsigned int ver = zynqmp_get_silicon_ver();
49
50 if (ver == ZYNQMP_CSU_VERSION_QEMU)
51 return 133000000;
52 else
53 return 100000000;
54 }
55
56 #if LOG_LEVEL >= LOG_LEVEL_NOTICE
57 static const struct {
58 unsigned int id;
59 unsigned int ver;
60 char *name;
61 bool evexists;
62 } zynqmp_devices[] = {
63 {
64 .id = 0x10,
65 .name = "3EG",
66 },
67 {
68 .id = 0x10,
69 .ver = 0x2c,
70 .name = "3CG",
71 },
72 {
73 .id = 0x11,
74 .name = "2EG",
75 },
76 {
77 .id = 0x11,
78 .ver = 0x2c,
79 .name = "2CG",
80 },
81 {
82 .id = 0x20,
83 .name = "5EV",
84 .evexists = true,
85 },
86 {
87 .id = 0x20,
88 .ver = 0x100,
89 .name = "5EG",
90 .evexists = true,
91 },
92 {
93 .id = 0x20,
94 .ver = 0x12c,
95 .name = "5CG",
96 },
97 {
98 .id = 0x21,
99 .name = "4EV",
100 .evexists = true,
101 },
102 {
103 .id = 0x21,
104 .ver = 0x100,
105 .name = "4EG",
106 .evexists = true,
107 },
108 {
109 .id = 0x21,
110 .ver = 0x12c,
111 .name = "4CG",
112 },
113 {
114 .id = 0x30,
115 .name = "7EV",
116 .evexists = true,
117 },
118 {
119 .id = 0x30,
120 .ver = 0x100,
121 .name = "7EG",
122 .evexists = true,
123 },
124 {
125 .id = 0x30,
126 .ver = 0x12c,
127 .name = "7CG",
128 },
129 {
130 .id = 0x38,
131 .name = "9EG",
132 },
133 {
134 .id = 0x38,
135 .ver = 0x2c,
136 .name = "9CG",
137 },
138 {
139 .id = 0x39,
140 .name = "6EG",
141 },
142 {
143 .id = 0x39,
144 .ver = 0x2c,
145 .name = "6CG",
146 },
147 {
148 .id = 0x40,
149 .name = "11EG",
150 },
151 { /* For testing purpose only */
152 .id = 0x50,
153 .ver = 0x2c,
154 .name = "15CG",
155 },
156 {
157 .id = 0x50,
158 .name = "15EG",
159 },
160 {
161 .id = 0x58,
162 .name = "19EG",
163 },
164 {
165 .id = 0x59,
166 .name = "17EG",
167 },
168 {
169 .id = 0x60,
170 .name = "28DR",
171 },
172 {
173 .id = 0x61,
174 .name = "21DR",
175 },
176 {
177 .id = 0x62,
178 .name = "29DR",
179 },
180 {
181 .id = 0x63,
182 .name = "23DR",
183 },
184 {
185 .id = 0x64,
186 .name = "27DR",
187 },
188 {
189 .id = 0x65,
190 .name = "25DR",
191 },
192 {
193 .id = 0x66,
194 .name = "39DR",
195 },
196 {
197 .id = 0x7b,
198 .name = "48DR",
199 },
200 {
201 .id = 0x7e,
202 .name = "49DR",
203 },
204 };
205
206 #define ZYNQMP_PL_STATUS_BIT 9
207 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
208 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
209
zynqmp_get_silicon_idcode_name(void)210 static char *zynqmp_get_silicon_idcode_name(void)
211 {
212 uint32_t id, ver, chipid[2];
213 size_t i, j, len;
214 const char *name = "EG/EV";
215
216 #ifdef IMAGE_BL32
217 /*
218 * For BL32, get the chip id info directly by reading corresponding
219 * registers instead of making pm call. This has limitation
220 * that these registers should be configured to have access
221 * from APU which is default case.
222 */
223 chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
224 chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
225 #else
226 if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
227 return "UNKN";
228 #endif
229
230 id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
231 ZYNQMP_CSU_IDCODE_SVD_MASK);
232 id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
233 ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;
234
235 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
236 if (zynqmp_devices[i].id == id &&
237 zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))
238 break;
239 }
240
241 if (i >= ARRAY_SIZE(zynqmp_devices))
242 return "UNKN";
243
244 if (!zynqmp_devices[i].evexists)
245 return zynqmp_devices[i].name;
246
247 if (ver & ZYNQMP_PL_STATUS_MASK)
248 return zynqmp_devices[i].name;
249
250 len = strlen(zynqmp_devices[i].name) - 2;
251 for (j = 0; j < strlen(name); j++) {
252 zynqmp_devices[i].name[len] = name[j];
253 len++;
254 }
255 zynqmp_devices[i].name[len] = '\0';
256
257 return zynqmp_devices[i].name;
258 }
259
zynqmp_get_rtl_ver(void)260 static unsigned int zynqmp_get_rtl_ver(void)
261 {
262 uint32_t ver;
263
264 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
265 ver &= ZYNQMP_RTL_VER_MASK;
266 ver >>= ZYNQMP_RTL_VER_SHIFT;
267
268 return ver;
269 }
270
zynqmp_print_silicon_idcode(void)271 static char *zynqmp_print_silicon_idcode(void)
272 {
273 uint32_t id, maskid, tmp;
274
275 id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
276
277 tmp = id;
278 tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK |
279 ZYNQMP_CSU_IDCODE_FAMILY_MASK;
280 maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT |
281 ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT;
282 if (tmp != maskid) {
283 ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid);
284 return "UNKN";
285 }
286 VERBOSE("Xilinx IDCODE 0x%x\n", id);
287 return zynqmp_get_silicon_idcode_name();
288 }
289
zynqmp_get_ps_ver(void)290 static unsigned int zynqmp_get_ps_ver(void)
291 {
292 uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
293
294 ver &= ZYNQMP_PS_VER_MASK;
295 ver >>= ZYNQMP_PS_VER_SHIFT;
296
297 return ver + 1;
298 }
299
zynqmp_print_platform_name(void)300 static void zynqmp_print_platform_name(void)
301 {
302 unsigned int ver = zynqmp_get_silicon_ver();
303 unsigned int rtl = zynqmp_get_rtl_ver();
304 char *label = "Unknown";
305
306 switch (ver) {
307 case ZYNQMP_CSU_VERSION_QEMU:
308 label = "QEMU";
309 break;
310 case ZYNQMP_CSU_VERSION_SILICON:
311 label = "silicon";
312 break;
313 default:
314 /* Do nothing in default case */
315 break;
316 }
317
318 NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x\n",
319 zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(),
320 (rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE);
321 }
322 #else
zynqmp_print_platform_name(void)323 static inline void zynqmp_print_platform_name(void) { }
324 #endif
325
zynqmp_get_bootmode(void)326 unsigned int zynqmp_get_bootmode(void)
327 {
328 uint32_t r;
329 unsigned int ret;
330
331 ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
332
333 if (ret != PM_RET_SUCCESS)
334 r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
335
336 return r & CRL_APB_BOOT_MODE_MASK;
337 }
338
zynqmp_config_setup(void)339 void zynqmp_config_setup(void)
340 {
341 /* Configure IPI data for ZynqMP */
342 zynqmp_ipi_config_table_init();
343
344 zynqmp_print_platform_name();
345 generic_delay_timer_init();
346 }
347
plat_get_syscnt_freq2(void)348 unsigned int plat_get_syscnt_freq2(void)
349 {
350 unsigned int ver = zynqmp_get_silicon_ver();
351
352 if (ver == ZYNQMP_CSU_VERSION_QEMU)
353 return 65000000;
354 else
355 return mmio_read_32(IOU_SCNTRS_BASEFREQ);
356 }
357