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/external/capstone/suite/MC/ARM/
Dneon-add-encoding.s.cs2 0xa0,0x08,0x41,0xf2 = vadd.i8 d16, d17, d16
3 0xa0,0x08,0x51,0xf2 = vadd.i16 d16, d17, d16
4 0xa0,0x08,0x71,0xf2 = vadd.i64 d16, d17, d16
5 0xa0,0x08,0x61,0xf2 = vadd.i32 d16, d17, d16
6 0xa1,0x0d,0x40,0xf2 = vadd.f32 d16, d16, d17
7 0xe2,0x0d,0x40,0xf2 = vadd.f32 q8, q8, q9
8 0xa0,0x00,0xc1,0xf2 = vaddl.s8 q8, d17, d16
9 0xa0,0x00,0xd1,0xf2 = vaddl.s16 q8, d17, d16
10 0xa0,0x00,0xe1,0xf2 = vaddl.s32 q8, d17, d16
11 0xa0,0x00,0xc1,0xf3 = vaddl.u8 q8, d17, d16
[all …]
Dneon-bitwise-encoding.s.cs2 0xb0,0x01,0x41,0xf2 = vand d16, d17, d16
3 0xf2,0x01,0x40,0xf2 = vand q8, q8, q9
4 0xb0,0x01,0x41,0xf3 = veor d16, d17, d16
5 0xf2,0x01,0x40,0xf3 = veor q8, q8, q9
6 0xb0,0x01,0x61,0xf2 = vorr d16, d17, d16
7 0xf2,0x01,0x60,0xf2 = vorr q8, q8, q9
8 0x11,0x07,0xc0,0xf2 = vorr.i32 d16, #0x1000000
9 0x51,0x07,0xc0,0xf2 = vorr.i32 q8, #0x1000000
10 0x50,0x01,0xc0,0xf2 = vorr.i32 q8, #0
11 0xb0,0x01,0x51,0xf2 = vbic d16, d17, d16
[all …]
Dneon-mul-encoding.s.cs2 0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17
3 0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17
4 0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17
5 0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17
6 0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9
7 0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9
8 0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9
9 0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9
10 0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17
11 0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9
[all …]
Dneon-shift-encoding.s.cs2 0xa1,0x04,0x40,0xf3 = vshl.u8 d16, d17, d16
3 0xa1,0x04,0x50,0xf3 = vshl.u16 d16, d17, d16
4 0xa1,0x04,0x60,0xf3 = vshl.u32 d16, d17, d16
5 0xa1,0x04,0x70,0xf3 = vshl.u64 d16, d17, d16
6 0x30,0x05,0xcf,0xf2 = vshl.i8 d16, d16, #7
7 0x30,0x05,0xdf,0xf2 = vshl.i16 d16, d16, #15
8 0x30,0x05,0xff,0xf2 = vshl.i32 d16, d16, #31
9 0xb0,0x05,0xff,0xf2 = vshl.i64 d16, d16, #63
10 0xe2,0x04,0x40,0xf3 = vshl.u8 q8, q9, q8
11 0xe2,0x04,0x50,0xf3 = vshl.u16 q8, q9, q8
[all …]
Dneon-sub-encoding.s.cs2 0xa0,0x08,0x41,0xf3 = vsub.i8 d16, d17, d16
3 0xa0,0x08,0x51,0xf3 = vsub.i16 d16, d17, d16
4 0xa0,0x08,0x61,0xf3 = vsub.i32 d16, d17, d16
5 0xa0,0x08,0x71,0xf3 = vsub.i64 d16, d17, d16
6 0xa1,0x0d,0x60,0xf2 = vsub.f32 d16, d16, d17
7 0xe2,0x08,0x40,0xf3 = vsub.i8 q8, q8, q9
8 0xe2,0x08,0x50,0xf3 = vsub.i16 q8, q8, q9
9 0xe2,0x08,0x60,0xf3 = vsub.i32 q8, q8, q9
10 0xe2,0x08,0x70,0xf3 = vsub.i64 q8, q8, q9
11 0xe2,0x0d,0x60,0xf2 = vsub.f32 q8, q8, q9
[all …]
Dneon-cmp-encoding.s.cs2 0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17
3 0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17
4 0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17
5 0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17
6 0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9
7 0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9
8 0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9
9 0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9
10 0xb1,0x03,0x40,0xf2 = vcge.s8 d16, d16, d17
11 0xb1,0x03,0x50,0xf2 = vcge.s16 d16, d16, d17
[all …]
Dneon-minmax-encoding.s.cs2 0x03,0x16,0x02,0xf2 = vmax.s8 d1, d2, d3
3 0x06,0x46,0x15,0xf2 = vmax.s16 d4, d5, d6
4 0x09,0x76,0x28,0xf2 = vmax.s32 d7, d8, d9
5 0x0c,0xa6,0x0b,0xf3 = vmax.u8 d10, d11, d12
6 0x0f,0xd6,0x1e,0xf3 = vmax.u16 d13, d14, d15
7 0xa2,0x06,0x61,0xf3 = vmax.u32 d16, d17, d18
8 0xa5,0x3f,0x44,0xf2 = vmax.f32 d19, d20, d21
9 0x03,0x26,0x02,0xf2 = vmax.s8 d2, d2, d3
10 0x06,0x56,0x15,0xf2 = vmax.s16 d5, d5, d6
11 0x09,0x86,0x28,0xf2 = vmax.s32 d8, d8, d9
[all …]
Dneon-mov-encoding.s.cs2 0x18,0x0e,0xc0,0xf2 = vmov.i8 d16, #0x8
3 0x10,0x08,0xc1,0xf2 = vmov.i16 d16, #0x10
4 0x10,0x0a,0xc1,0xf2 = vmov.i16 d16, #0x1000
5 0x10,0x00,0xc2,0xf2 = vmov.i32 d16, #0x20
6 0x10,0x02,0xc2,0xf2 = vmov.i32 d16, #0x2000
7 0x10,0x04,0xc2,0xf2 = vmov.i32 d16, #0x200000
8 0x10,0x06,0xc2,0xf2 = vmov.i32 d16, #0x20000000
9 0x10,0x0c,0xc2,0xf2 = vmov.i32 d16, #0x20ff
10 0x10,0x0d,0xc2,0xf2 = vmov.i32 d16, #0x20ffff
11 0x33,0x0e,0xc1,0xf3 = vmov.i64 d16, #0xff0000ff0000ffff
[all …]
Dneon-shuffle-encoding.s.cs2 0xa0,0x03,0xf1,0xf2 = vext.8 d16, d17, d16, #3
3 0xa0,0x05,0xf1,0xf2 = vext.8 d16, d17, d16, #5
4 0xe0,0x03,0xf2,0xf2 = vext.8 q8, q9, q8, #3
5 0xe0,0x07,0xf2,0xf2 = vext.8 q8, q9, q8, #7
6 0xa0,0x06,0xf1,0xf2 = vext.16 d16, d17, d16, #3
7 0xe0,0x0c,0xf2,0xf2 = vext.32 q8, q9, q8, #3
8 0xe0,0x08,0xf2,0xf2 = vext.64 q8, q9, q8, #1
9 0xa0,0x13,0xf1,0xf2 = vext.8 d17, d17, d16, #3
10 0x0b,0x75,0xb7,0xf2 = vext.8 d7, d7, d11, #5
11 0x60,0x63,0xb6,0xf2 = vext.8 q3, q3, q8, #3
[all …]
/external/vixl/test/aarch32/traces/
Dassembler-cond-rd-pc-operand-imm8-add-t32.h38 0x0f, 0xf2, 0x13, 0x07 // add al r7 pc 19
41 0x0f, 0xf2, 0x4e, 0x06 // add al r6 pc 78
44 0x17, 0xa7 // add al r7 pc 92
47 0x0f, 0xf2, 0xc3, 0x07 // add al r7 pc 195
50 0x0f, 0xf2, 0x11, 0x04 // add al r4 pc 17
53 0x0f, 0xf2, 0x96, 0x06 // add al r6 pc 150
56 0x0f, 0xf2, 0xa6, 0x04 // add al r4 pc 166
59 0x0f, 0xf2, 0x3f, 0x01 // add al r1 pc 63
62 0x0f, 0xf2, 0x0f, 0x03 // add al r3 pc 15
65 0x0f, 0xf2, 0x31, 0x06 // add al r6 pc 49
[all …]
Dassembler-cond-dt-drt-drd-drn-drm-float-f32-only-vmax-a32.h38 0x2e, 0x1f, 0x02, 0xf2 // vmax F32 d1 d2 d30
41 0x0d, 0xcf, 0x05, 0xf2 // vmax F32 d12 d5 d13
44 0x82, 0x3f, 0x00, 0xf2 // vmax F32 d3 d16 d2
47 0x87, 0x5f, 0x4a, 0xf2 // vmax F32 d21 d26 d7
50 0x20, 0xef, 0x41, 0xf2 // vmax F32 d30 d1 d16
53 0x06, 0x1f, 0x48, 0xf2 // vmax F32 d17 d8 d6
56 0x07, 0xaf, 0x41, 0xf2 // vmax F32 d26 d1 d7
59 0x2c, 0x1f, 0x46, 0xf2 // vmax F32 d17 d6 d28
62 0x2b, 0xef, 0x46, 0xf2 // vmax F32 d30 d6 d27
65 0x0b, 0x6f, 0x0d, 0xf2 // vmax F32 d6 d13 d11
[all …]
Dassembler-cond-dt-drt-drd-drn-drm-float-f32-only-vmin-a32.h38 0x2e, 0x1f, 0x22, 0xf2 // vmin F32 d1 d2 d30
41 0x0d, 0xcf, 0x25, 0xf2 // vmin F32 d12 d5 d13
44 0x82, 0x3f, 0x20, 0xf2 // vmin F32 d3 d16 d2
47 0x87, 0x5f, 0x6a, 0xf2 // vmin F32 d21 d26 d7
50 0x20, 0xef, 0x61, 0xf2 // vmin F32 d30 d1 d16
53 0x06, 0x1f, 0x68, 0xf2 // vmin F32 d17 d8 d6
56 0x07, 0xaf, 0x61, 0xf2 // vmin F32 d26 d1 d7
59 0x2c, 0x1f, 0x66, 0xf2 // vmin F32 d17 d6 d28
62 0x2b, 0xef, 0x66, 0xf2 // vmin F32 d30 d6 d27
65 0x0b, 0x6f, 0x2d, 0xf2 // vmin F32 d6 d13 d11
[all …]
Dassembler-cond-dt-drt-drd-drn-drm-float-f32-only-vceq-a32.h38 0x2e, 0x1e, 0x02, 0xf2 // vceq F32 d1 d2 d30
41 0x0d, 0xce, 0x05, 0xf2 // vceq F32 d12 d5 d13
44 0x82, 0x3e, 0x00, 0xf2 // vceq F32 d3 d16 d2
47 0x87, 0x5e, 0x4a, 0xf2 // vceq F32 d21 d26 d7
50 0x20, 0xee, 0x41, 0xf2 // vceq F32 d30 d1 d16
53 0x06, 0x1e, 0x48, 0xf2 // vceq F32 d17 d8 d6
56 0x07, 0xae, 0x41, 0xf2 // vceq F32 d26 d1 d7
59 0x2c, 0x1e, 0x46, 0xf2 // vceq F32 d17 d6 d28
62 0x2b, 0xee, 0x46, 0xf2 // vceq F32 d30 d6 d27
65 0x0b, 0x6e, 0x0d, 0xf2 // vceq F32 d6 d13 d11
[all …]
Dassembler-cond-rd-pc-operand-imm12-addw-t32.h38 0x0f, 0xf6, 0xa6, 0x3b // addw al r11 pc 2982
41 0x0f, 0xf2, 0x7d, 0x37 // addw al r7 pc 893
44 0x0f, 0xf6, 0xff, 0x5c // addw al r12 pc 3583
47 0x0f, 0xf2, 0x44, 0x58 // addw al r8 pc 1348
50 0x0f, 0xf2, 0x64, 0x7d // addw al r13 pc 1892
53 0x0f, 0xf6, 0x04, 0x09 // addw al r9 pc 2052
56 0x0f, 0xf6, 0x29, 0x12 // addw al r2 pc 2345
59 0x0f, 0xf2, 0xf1, 0x36 // addw al r6 pc 1009
62 0x0f, 0xf6, 0x81, 0x2c // addw al r12 pc 2689
65 0x0f, 0xf6, 0xb7, 0x35 // addw al r5 pc 2999
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/X86/
Davx512bf16vl-intel.txt4 0x62,0xf2,0x67,0x28,0x72,0xd4
7 0x62,0xf2,0x67,0x2f,0x72,0xd4
10 0x62,0xf2,0x67,0xaf,0x72,0xd4
13 0x62,0xf2,0x67,0x08,0x72,0xd4
16 0x62,0xf2,0x67,0x0f,0x72,0xd4
19 0x62,0xf2,0x67,0x8f,0x72,0xd4
22 0x62,0xf2,0x67,0x28,0x72,0x94,0xf4,0x00,0x00,0x00,0x10
25 0x62,0xf2,0x67,0x2f,0x72,0x94,0x87,0x23,0x01,0x00,0x00
28 0x62,0xf2,0x67,0x38,0x72,0x10
31 0x62,0xf2,0x67,0x28,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff
[all …]
Davx512bf16vl-att.txt4 0x62,0xf2,0x67,0x28,0x72,0xd4
7 0x62,0xf2,0x67,0x2f,0x72,0xd4
10 0x62,0xf2,0x67,0xaf,0x72,0xd4
13 0x62,0xf2,0x67,0x08,0x72,0xd4
16 0x62,0xf2,0x67,0x0f,0x72,0xd4
19 0x62,0xf2,0x67,0x8f,0x72,0xd4
22 0x62,0xf2,0x67,0x28,0x72,0x94,0xf4,0x00,0x00,0x00,0x10
25 0x62,0xf2,0x67,0x2f,0x72,0x94,0x87,0x23,0x01,0x00,0x00
28 0x62,0xf2,0x67,0x38,0x72,0x10
31 0x62,0xf2,0x67,0x28,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff
[all …]
/external/llvm/test/MC/ARM/
Dneon-add-encoding.s4 @ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2]
6 @ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf2]
8 @ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf2]
10 @ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf2]
12 @ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf2]
14 @ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xf2]
17 @ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf2]
19 @ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf2]
21 @ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf2]
23 @ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf3]
[all …]
Dneon-mul-encoding.s26 @ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2]
27 @ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2]
28 @ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2]
29 @ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3]
30 @ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2]
31 @ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2]
32 @ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2]
33 @ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3]
34 @ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3]
35 @ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3]
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dneon-add-encoding.s4 @ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2]
6 @ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf2]
8 @ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf2]
10 @ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf2]
12 @ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf2]
14 @ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xf2]
17 @ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf2]
19 @ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf2]
21 @ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf2]
23 @ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf3]
[all …]
Dneon-mul-encoding.s26 @ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2]
27 @ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2]
28 @ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2]
29 @ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3]
30 @ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2]
31 @ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2]
32 @ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2]
33 @ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3]
34 @ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3]
35 @ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3]
[all …]
Dneon-bitwise-encoding.s7 @ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2]
8 @ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf2]
13 @ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf3]
14 @ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf3]
19 @ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xf2]
20 @ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2]
22 vorr.i32 d16, #0x1000000
23 vorr.i32 q8, #0x1000000
24 vorr.i32 q8, #0x0
26 @ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dneon.txt3 0x20 0x03 0xf1 0xf3
5 0x20 0x03 0xf5 0xf3
7 0x20 0x03 0xf9 0xf3
9 0x20 0x07 0xf9 0xf3
11 0x60 0x03 0xf1 0xf3
13 0x60 0x03 0xf5 0xf3
15 0x60 0x03 0xf9 0xf3
17 0x60 0x07 0xf9 0xf3
20 0x20 0x07 0xf0 0xf3
22 0x20 0x07 0xf4 0xf3
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneon.txt3 0x20 0x03 0xf1 0xf3
5 0x20 0x03 0xf5 0xf3
7 0x20 0x03 0xf9 0xf3
9 0x20 0x07 0xf9 0xf3
11 0x60 0x03 0xf1 0xf3
13 0x60 0x03 0xf5 0xf3
15 0x60 0x03 0xf9 0xf3
17 0x60 0x07 0xf9 0xf3
20 0x20 0x07 0xf0 0xf3
22 0x20 0x07 0xf4 0xf3
[all …]
/external/llvm-project/llvm/test/MC/X86/
Dx86-32-avx512vp2intersect-att.s4 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
8 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
12 // CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
16 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
20 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
24 // CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
28 // CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
32 // CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36]
36 // CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36]
40 // CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
[all …]
Dx86-64-avx512vp2intersect-att.s5 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
9 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
13 // CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
17 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
21 // CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
25 // CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
29 // CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7]
33 // CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36]
37 // CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36]
41 // CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7]
[all …]

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