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/external/arm-trusted-firmware/plat/imx/common/include/
Dimx_clock.h27 #define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0)
28 #define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1)
29 #define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0))
31 #define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4)
32 #define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5)
33 #define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4))
35 #define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8)
36 #define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9)
37 #define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8))
39 #define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12)
[all …]
Dimx_io_mux.h26 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B BIT(0)
97 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0)
98 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1)
99 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0))
100 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3)
101 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0))
102 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1))
103 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3)
107 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0)
108 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1)
[all …]
/external/arm-trusted-firmware/drivers/renesas/rcar/pfc/V3M/
Dpfc_init_v3m.c15 /* Pin functon bit */
16 #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
17 #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)
18 #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)
19 #define GPSR0_DU_DOTCLKOUT BIT(18)
20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
[all …]
/external/arm-trusted-firmware/drivers/imx/uart/
Dimx_uart.h12 #define IMX_UART_RXD_CHARRDY BIT(15)
13 #define IMX_UART_RXD_ERR BIT(14)
14 #define IMX_UART_RXD_OVERRUN BIT(13)
15 #define IMX_UART_RXD_FRMERR BIT(12)
16 #define IMX_UART_RXD_BRK BIT(11)
17 #define IMX_UART_RXD_PRERR BIT(10)
22 #define IMX_UART_CR1_ADEN BIT(15)
23 #define IMX_UART_CR1_ADBR BIT(14)
24 #define IMX_UART_CR1_TRDYEN BIT(13)
25 #define IMX_UART_CR1_IDEN BIT(12)
[all …]
/external/arm-trusted-firmware/include/drivers/st/
Dstm32_uart_regs.h26 #define USART_CR1_UE BIT(0)
27 #define USART_CR1_UESM BIT(1)
28 #define USART_CR1_RE BIT(2)
29 #define USART_CR1_TE BIT(3)
30 #define USART_CR1_IDLEIE BIT(4)
31 #define USART_CR1_RXNEIE BIT(5)
32 #define USART_CR1_TCIE BIT(6)
33 #define USART_CR1_TXEIE BIT(7)
34 #define USART_CR1_PEIE BIT(8)
35 #define USART_CR1_PS BIT(9)
[all …]
Dstm32_i2c.h14 /* Bit definition for I2C_CR1 register */
15 #define I2C_CR1_PE BIT(0)
16 #define I2C_CR1_TXIE BIT(1)
17 #define I2C_CR1_RXIE BIT(2)
18 #define I2C_CR1_ADDRIE BIT(3)
19 #define I2C_CR1_NACKIE BIT(4)
20 #define I2C_CR1_STOPIE BIT(5)
21 #define I2C_CR1_TCIE BIT(6)
22 #define I2C_CR1_ERRIE BIT(7)
24 #define I2C_CR1_ANFOFF BIT(12)
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/external/rust/crates/ahash/smhasher/
DahashOutput.txt2 --- Testing ahash64 "ahash 64bit" GOOD
68 Testing 24-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.702667%
69 Testing 32-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.670667%
70 Testing 40-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.608667%
71 Testing 48-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.670667%
72 Testing 56-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.670000%
73 Testing 64-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.663333%
74 Testing 72-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.780667%
75 Testing 80-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.716000%
76 Testing 96-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.621333%
[all …]
DfallbackOutput.txt2 --- Testing ahash64 "ahash 64bit" GOOD
68 Testing 24-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.700000%
69 Testing 32-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.628000%
70 Testing 40-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.628667%
71 Testing 48-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.662000%
72 Testing 56-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.699333%
73 Testing 64-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.665333%
74 Testing 72-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.630667%
75 Testing 80-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.692000%
76 Testing 96-bit keys -> 64-bit hashes, 300000 reps worst bias is 0.774000%
[all …]
/external/selinux/mcstrans/share/examples/nato/setrans.d/
Deyes-only.conf11 # Aruba - bit 201
14 # Antigua and Barbuda - bit 214
17 # United Arab Emirates - bit 208
20 # Afghanistan - bit 202
23 # Algeria - bit 263
26 # Azerbaijan - bit 217
29 # Albania - bit 205
32 # Armenia - bit 210
35 # Andorra - bit 206
38 # Angola - bit 203
[all …]
Drel.conf17 # Aruba - bit 201
20 # Antigua and Barbuda - bit 214
23 # United Arab Emirates - bit 208
26 # Afghanistan - bit 202
29 # Algeria - bit 263
32 # Azerbaijan - bit 217
35 # Albania - bit 205
38 # Armenia - bit 210
41 # Andorra - bit 206
44 # Angola - bit 203
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/
Dgpc_reg.h39 #define MASK_DSM_TRIGGER_A53 BIT(31)
40 #define IRQ_SRC_A53_WUP BIT(30)
42 #define IRQ_SRC_C1 BIT(29)
43 #define IRQ_SRC_C0 BIT(28)
44 #define IRQ_SRC_C3 BIT(23)
45 #define IRQ_SRC_C2 BIT(22)
46 #define CPU_CLOCK_ON_LPM BIT(14)
47 #define A53_CLK_ON_LPM BIT(14)
48 #define MASTER0_LPM_HSK BIT(6)
49 #define MASTER1_LPM_HSK BIT(7)
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/include/
Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
[all …]
/external/clang/lib/Headers/
Dmmintrin.h50 /// \brief Constructs a 64-bit integer vector, setting the lower 32 bits to the
51 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
58 /// A 32-bit integer value.
59 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
67 /// \brief Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
75 /// A 64-bit integer vector.
76 /// \returns A 32-bit signed integer value containing the lower 32 bits of the
84 /// \brief Casts a 64-bit signed integer value into a 64-bit integer vector.
91 /// A 64-bit signed integer.
92 /// \returns A 64-bit integer vector containing the same bitwise pattern as the
[all …]
/external/llvm-project/clang/lib/Headers/
Dmmintrin.h36 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
37 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
44 /// A 32-bit integer value.
45 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
53 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
61 /// A 64-bit integer vector.
62 /// \returns A 32-bit signed integer value containing the lower 32 bits of the
70 /// Casts a 64-bit signed integer value into a 64-bit integer vector.
77 /// A 64-bit signed integer.
78 /// \returns A 64-bit integer vector containing the same bitwise pattern as the
[all …]
/external/llvm/test/MC/Mips/msa/
Dinvalid.s8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
15 addvi.d $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
16 andi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
17 andi.b $w1, $w2, 256 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mn/include/
Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
[all …]
/external/llvm-project/llvm/test/MC/Mips/msa/
Dinvalid.s8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
15 addvi.d $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
16 andi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
17 andi.b $w1, $w2, 256 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
[all …]
/external/arm-trusted-firmware/drivers/imx/usdhc/
Dimx_usdhc.h34 #define XFERTYPE_DPSEL BIT(21)
35 #define XFERTYPE_CICEN BIT(20)
36 #define XFERTYPE_CCCEN BIT(19)
37 #define XFERTYPE_RSPTYP_136 BIT(16)
38 #define XFERTYPE_RSPTYP_48 BIT(17)
39 #define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
42 #define PSTATE_DAT0 BIT(24)
43 #define PSTATE_DLA BIT(2)
44 #define PSTATE_CDIHB BIT(1)
45 #define PSTATE_CIHB BIT(0)
[all …]
/external/arm-trusted-firmware/drivers/renesas/rcar/pfc/E3/
Dpfc_init_e3.c14 #define GPSR0_SDA4 BIT(17)
15 #define GPSR0_SCL4 BIT(16)
16 #define GPSR0_D15 BIT(15)
17 #define GPSR0_D14 BIT(14)
18 #define GPSR0_D13 BIT(13)
19 #define GPSR0_D12 BIT(12)
20 #define GPSR0_D11 BIT(11)
21 #define GPSR0_D10 BIT(10)
22 #define GPSR0_D9 BIT(9)
23 #define GPSR0_D8 BIT(8)
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Daix-crspill.ll2 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
5 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
23 ; 64BIT-LABEL: .killOne:
25 ; 64BIT: mflr 0
26 ; 64BIT-NEXT: std 0, 16(1)
27 ; 64BIT-NEXT: mfcr 12
28 ; 64BIT-NEXT: stw 12, 8(1)
29 ; 64BIT: stdu 1, -112(1)
31 ; 64BIT: # Clobber CR
32 ; 64BIT: bl .do_something
[all …]
Daix-cc-abi.ll2 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
9 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
23 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
24 ; 32BIT: $r3 = LI 97
25 ; 32BIT: $r4 = LI 97
26 ; 32BIT: $r5 = LI 97
27 ; 32BIT: $r6 = LI 97
28 ; 32BIT: BL_NOP <mcsymbol .test_chars>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit ki…
29 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
31 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
[all …]
Daix-cc-byval-mem.ll4 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
13 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
55 ; 32BIT: fixedStack:
56 ; 32BIT-NEXT: - { id: 0, type: default, offset: 56, size: 4, alignment: 8, stack-id: default,
57 ; 32BIT: bb.0.entry:
58 ; 32BIT-NEXT: %[[VAL:[0-9]+]]:gprc = LBZ 0, %fixed-stack.0
59 ; 32BIT-NEXT: $r3 = COPY %[[VAL]]
60 ; 32BIT-NEXT: BLR
62 ; 64BIT: fixedStack:
63 ; 64BIT-NEXT: - { id: 0, type: default, offset: 112, size: 8, alignment: 16, stack-id: default,
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8192/include/
Dmcucfg.h23 #define MP2_CPU0_STANDBYWFE BIT(4)
24 #define MP2_CPU1_STANDBYWFE BIT(5)
30 #define sw_spark_en BIT(0)
31 #define sw_no_wait_for_q_channel BIT(1)
32 #define sw_fsm_override BIT(2)
33 #define sw_logic_pre1_pdb BIT(3)
34 #define sw_logic_pre2_pdb BIT(4)
35 #define sw_logic_pdb BIT(5)
36 #define sw_iso BIT(6)
38 #define sw_sram_isointb BIT(13)
[all …]
/external/wpa_supplicant_8/src/common/
Dieee802_11_defs.h32 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
34 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
93 #define WLAN_CAPABILITY_ESS BIT(0)
94 #define WLAN_CAPABILITY_IBSS BIT(1)
95 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
96 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
97 #define WLAN_CAPABILITY_PRIVACY BIT(4)
98 #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
99 #define WLAN_CAPABILITY_PBCC BIT(6)
100 #define WLAN_CAPABILITY_CHANNEL_AGILITY BIT(7)
[all …]
/external/llvm-project/clang/include/clang/Basic/
DMSP430Target.def179 // With 16-bit hardware multiplier
180 MSP430_MCU_FEAT("msp430f147", "16bit")
181 MSP430_MCU_FEAT("msp430f148", "16bit")
182 MSP430_MCU_FEAT("msp430f149", "16bit")
183 MSP430_MCU_FEAT("msp430f1471", "16bit")
184 MSP430_MCU_FEAT("msp430f1481", "16bit")
185 MSP430_MCU_FEAT("msp430f1491", "16bit")
186 MSP430_MCU_FEAT("msp430f167", "16bit")
187 MSP430_MCU_FEAT("msp430f168", "16bit")
188 MSP430_MCU_FEAT("msp430f169", "16bit")
[all …]

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