1/* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <platform_def.h> 10#include <cortex_a75.h> 11#include <neoverse_n1.h> 12#include <cpu_macros.S> 13 14 .globl plat_arm_calc_core_pos 15 .globl plat_reset_handler 16 17 /* ----------------------------------------------------- 18 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 19 * 20 * Helper function to calculate the core position. 21 * (ChipId * PLAT_ARM_CLUSTER_COUNT * 22 * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) + 23 * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) + 24 * (CPUId * CSS_SGI_MAX_PE_PER_CPU) + 25 * ThreadId 26 * 27 * which can be simplified as: 28 * 29 * ((((ChipId * PLAT_ARM_CLUSTER_COUNT) + ClusterId) * 30 * CSS_SGI_MAX_CPUS_PER_CLUSTER) + CPUId) * CSS_SGI_MAX_PE_PER_CPU + 31 * ThreadId 32 * ------------------------------------------------------ 33 */ 34 35func plat_arm_calc_core_pos 36 mov x4, x0 37 38 /* 39 * The MT bit in MPIDR is always set for SGI platforms 40 * and the affinity level 0 corresponds to thread affinity level. 41 */ 42 43 /* Extract individual affinity fields from MPIDR */ 44 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 45 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 46 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 47 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS 48 49 /* Compute linear position */ 50 mov x4, #PLAT_ARM_CLUSTER_COUNT 51 madd x2, x3, x4, x2 52 mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER 53 madd x1, x2, x4, x1 54 mov x4, #CSS_SGI_MAX_PE_PER_CPU 55 madd x0, x1, x4, x0 56 ret 57endfunc plat_arm_calc_core_pos 58 59 /* ----------------------------------------------------- 60 * void plat_reset_handler(void); 61 * 62 * Determine the CPU MIDR and disable power down bit for 63 * that CPU. 64 * ----------------------------------------------------- 65 */ 66func plat_reset_handler 67 jump_if_cpu_midr CORTEX_A75_MIDR, A75 68 jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 69 ret 70 71 /* ----------------------------------------------------- 72 * Disable CPU power down bit in power control register 73 * ----------------------------------------------------- 74 */ 75A75: 76 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 77 bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 78 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 79 isb 80 ret 81 82N1: 83 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 84 bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 85 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 86 isb 87 ret 88endfunc plat_reset_handler 89