1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71 #include "impeg2d_deinterlace.h"
72
73 #define NUM_FRAMES_LIMIT_ENABLED 0
74
75 #ifdef LOGO_EN
76 #include "impeg2_ittiam_logo.h"
77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
78 #else
79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
80 #endif
81
82 #if NUM_FRAMES_LIMIT_ENABLED
83 #define NUM_FRAMES_LIMIT 10000
84 #else
85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
86 #endif
87
88 #define CODEC_NAME "MPEG2VDEC"
89 #define CODEC_RELEASE_TYPE "eval"
90 #define CODEC_RELEASE_VER "01.00"
91 #define CODEC_VENDOR "ITTIAM"
92
93 #ifdef ANDROID
94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
95 strcpy(version_string,"@(#)Id:"); \
96 strcat(version_string,codec_name); \
97 strcat(version_string,"_"); \
98 strcat(version_string,codec_release_type); \
99 strcat(version_string," Ver:"); \
100 strcat(version_string,codec_release_ver); \
101 strcat(version_string," Released by "); \
102 strcat(version_string,codec_vendor);
103 #else
104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
105 strcpy(version_string,"@(#)Id:"); \
106 strcat(version_string,codec_name); \
107 strcat(version_string,"_"); \
108 strcat(version_string,codec_release_type); \
109 strcat(version_string," Ver:"); \
110 strcat(version_string,codec_release_ver); \
111 strcat(version_string," Released by "); \
112 strcat(version_string,codec_vendor); \
113 strcat(version_string," Build: "); \
114 strcat(version_string,__DATE__); \
115 strcat(version_string," @ "); \
116 strcat(version_string,__TIME__);
117 #endif
118
119
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125
126 void impeg2d_init_arch(void *pv_codec);
127 void impeg2d_init_function_ptr(void *pv_codec);
128 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size);
129
130 /*****************************************************************************/
131 /* */
132 /* Function Name : impeg2d_api_rel_display_frame */
133 /* */
134 /* Description : Release displ buffers that will be shared between decoder */
135 /* and application */
136 /* Inputs : Error message */
137 /* Globals : None */
138 /* Processing : Just prints error message to console */
139 /* Outputs : Error mesage to the console */
140 /* Returns : None */
141 /* */
142 /* Issues : <List any issues or problems with this function> */
143 /* */
144 /* Revision History: */
145 /* */
146 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
147 /* 27 05 2006 Sankar Creation */
148 /* */
149 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)150 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
151 void *pv_api_ip,
152 void *pv_api_op)
153 {
154
155 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
156 ivd_rel_display_frame_op_t *dec_rel_disp_op;
157
158 dec_state_t *ps_dec_state;
159 dec_state_multi_core_t *ps_dec_state_multi_core;
160
161
162 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
163 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
164
165 dec_rel_disp_op->u4_error_code = 0;
166 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
167 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
168
169
170 /* If not in shared disp buf mode, return */
171 if(0 == ps_dec_state->u4_share_disp_buf)
172 return IV_SUCCESS;
173
174 if(NULL == ps_dec_state->pv_pic_buf_mg)
175 return IV_SUCCESS;
176
177
178 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
179
180 return IV_SUCCESS;
181 }
182
183 /*****************************************************************************/
184 /* */
185 /* Function Name : impeg2d_api_set_display_frame */
186 /* */
187 /* Description : Sets display buffers that will be shared between decoder */
188 /* and application */
189 /* Inputs : Error message */
190 /* Globals : None */
191 /* Processing : Just prints error message to console */
192 /* Outputs : Error mesage to the console */
193 /* Returns : None */
194 /* */
195 /* Issues : <List any issues or problems with this function> */
196 /* */
197 /* Revision History: */
198 /* */
199 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
200 /* 27 05 2006 Sankar Creation */
201 /* */
202 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)203 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
204 void *pv_api_ip,
205 void *pv_api_op)
206 {
207
208 ivd_set_display_frame_ip_t *dec_disp_ip;
209 ivd_set_display_frame_op_t *dec_disp_op;
210
211 UWORD32 i;
212 dec_state_t *ps_dec_state;
213 dec_state_multi_core_t *ps_dec_state_multi_core;
214 UWORD32 u4_num_disp_bufs;
215 UWORD32 u4_disp_buf_size[3];
216 UWORD32 num_bufs;
217
218
219 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
220 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
221 dec_disp_op->u4_error_code = 0;
222
223 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
224 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
225 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
226
227 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
228 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
229
230 num_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
231
232 if(ps_dec_state->u4_share_disp_buf)
233 {
234 pic_buf_t *ps_pic_buf;
235 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
236
237 /* Get the sizes of the first buffer structure. Compare this with the
238 * rest to make sure all the buffers are of the same size.
239 */
240 u4_disp_buf_size[0] =
241 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
242 u4_disp_buf_size[1] =
243 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
244 u4_disp_buf_size[2] =
245 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
246 for(i = 0; i < u4_num_disp_bufs; i++)
247 {
248 /* Verify all buffer structures have the same sized buffers as the
249 * first buffer structure*/
250 if ((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
251 != u4_disp_buf_size[0])
252 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
253 != u4_disp_buf_size[1])
254 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
255 != u4_disp_buf_size[2]))
256 {
257 return IV_FAIL;
258 }
259 /* Verify all buffer structures have the same number of
260 * buffers (e.g. y, u, v) */
261 if (dec_disp_ip->s_disp_buffer[i].u4_num_bufs != num_bufs)
262 {
263 return IV_FAIL;
264 }
265
266 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
267 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
268 {
269 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
270 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
271 }
272 else
273 {
274 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
275 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
276 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
277 }
278
279 ps_pic_buf->i4_buf_id = i;
280
281 ps_pic_buf->u1_used_as_ref = 0;
282
283 ps_pic_buf->u4_ts = 0;
284
285 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
286 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
287 ps_pic_buf++;
288
289 }
290 }
291 memcpy(&(ps_dec_state->as_disp_buffers[0]),
292 &(dec_disp_ip->s_disp_buffer),
293 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
294
295 return IV_SUCCESS;
296
297 }
298
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)299 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
300 void *pv_api_ip,
301 void *pv_api_op)
302 {
303 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
304 impeg2d_ctl_set_num_cores_op_t *ps_op;
305 dec_state_t *ps_dec_state;
306 dec_state_multi_core_t *ps_dec_state_multi_core;
307
308 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
309 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
310
311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
312 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
313
314 if(ps_ip->u4_num_cores > 0)
315 {
316
317
318 WORD32 i;
319 for(i = 0; i < MAX_THREADS; i++)
320 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
321 }
322 else
323 {
324 ps_dec_state->i4_num_cores = 1;
325 }
326 ps_op->u4_error_code = IV_SUCCESS;
327
328 return IV_SUCCESS;
329 }
330
impeg2d_api_get_seq_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)331 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl,
332 void *pv_api_ip,
333 void *pv_api_op)
334 {
335 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
336 impeg2d_ctl_get_seq_info_op_t *ps_op;
337 dec_state_t *ps_codec;
338 dec_state_multi_core_t *ps_dec_state_multi_core;
339
340 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
341 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
342
343 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
344 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
345 UNUSED(ps_ip);
346 if(ps_codec->u2_header_done == 1)
347 {
348 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info;
349 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code;
350 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n;
351 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d;
352 if(ps_codec->u1_seq_disp_extn_present == 1)
353 {
354 ps_op->u1_video_format = ps_codec->u1_video_format;
355 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries;
356 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics;
357 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients;
358 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size;
359 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size;
360 }
361 else
362 {
363 ps_op->u1_video_format = 5;
364 ps_op->u1_colour_primaries = 2;
365 ps_op->u1_transfer_characteristics = 2;
366 ps_op->u1_matrix_coefficients = 2;
367 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size;
368 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size;
369 }
370 ps_op->u4_error_code = IV_SUCCESS;
371 return IV_SUCCESS;
372 }
373 else
374 {
375 ps_op->u4_error_code = IV_FAIL;
376 return IV_FAIL;
377 }
378 }
379
380 /**
381 *******************************************************************************
382 *
383 * @brief
384 * Sets Processor type
385 *
386 * @par Description:
387 * Sets Processor type
388 *
389 * @param[in] ps_codec_obj
390 * Pointer to codec object at API level
391 *
392 * @param[in] pv_api_ip
393 * Pointer to input argument structure
394 *
395 * @param[out] pv_api_op
396 * Pointer to output argument structure
397 *
398 * @returns Status
399 *
400 * @remarks
401 *
402 *
403 *******************************************************************************
404 */
405
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)406 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
407 void *pv_api_ip,
408 void *pv_api_op)
409 {
410 impeg2d_ctl_set_processor_ip_t *ps_ip;
411 impeg2d_ctl_set_processor_op_t *ps_op;
412 dec_state_t *ps_codec;
413 dec_state_multi_core_t *ps_dec_state_multi_core;
414
415 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
416 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
417
418 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
419 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
420
421 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
422 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
423
424 impeg2d_init_function_ptr(ps_codec);
425
426
427 ps_op->u4_error_code = 0;
428 return IV_SUCCESS;
429 }
430 /*****************************************************************************/
431 /* */
432 /* Function Name : impeg2d_fill_mem_rec */
433 /* */
434 /* Description : */
435 /* Inputs : */
436 /* Globals : */
437 /* Processing : */
438 /* Outputs : */
439 /* Returns : */
440 /* */
441 /* Issues : */
442 /* */
443 /* Revision History: */
444 /* */
445 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
446 /* 17 09 2007 Rajendra C Y Draft */
447 /* */
448 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)449 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
450 impeg2d_fill_mem_rec_op_t *ps_op)
451 {
452 UWORD32 u4_i;
453
454 UWORD8 u1_no_rec = 0;
455 UWORD32 max_frm_width,max_frm_height,max_frm_size;
456 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
457 WORD32 i4_num_threads;
458 WORD32 i4_share_disp_buf, i4_chroma_format;
459 WORD32 i4_chroma_size;
460 UWORD32 u4_deinterlace;
461 UNUSED(u4_deinterlace);
462 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
463 /* In error clips with field prediction, the mv may incorrectly refer to
464 * the last MB row, causing an out of bounds read access. Allocating 8 extra
465 * rows to handle this. Adding another extra row to handle half_y prediction.
466 */
467 max_frm_height = ALIGN32(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht) + 9;
468
469 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
470
471 i4_chroma_size = max_frm_width * max_frm_height / 4;
472
473 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
474 {
475 #ifndef LOGO_EN
476 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
477 #else
478 i4_share_disp_buf = 0;
479 #endif
480 }
481 else
482 {
483 i4_share_disp_buf = 0;
484 }
485 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
486 {
487 i4_chroma_format = ps_ip->e_output_format;
488 }
489 else
490 {
491 i4_chroma_format = -1;
492 }
493
494 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace))
495 {
496 u4_deinterlace = ps_ip->u4_deinterlace;
497 }
498 else
499 {
500 u4_deinterlace = 0;
501 }
502
503
504 if( (i4_chroma_format != IV_YUV_420P) &&
505 (i4_chroma_format != IV_YUV_420SP_UV) &&
506 (i4_chroma_format != IV_YUV_420SP_VU))
507 {
508 i4_share_disp_buf = 0;
509 }
510
511 /* Disable deinterlacer in shared mode */
512 if(i4_share_disp_buf)
513 {
514 u4_deinterlace = 0;
515 }
516
517 /*************************************************************************/
518 /* Fill the memory requirement XDM Handle */
519 /*************************************************************************/
520 /* ! */
521 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
522 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
523 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
524
525 ps_mem_rec++;
526 u1_no_rec++;
527
528 {
529 /*************************************************************************/
530 /* Fill the memory requirement for threads context */
531 /*************************************************************************/
532 /* ! */
533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
535 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
536
537 ps_mem_rec++;
538 u1_no_rec++;
539 }
540
541 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
542 {
543 /*************************************************************************/
544 /* Fill the memory requirement for MPEG2 Decoder Context */
545 /*************************************************************************/
546 /* ! */
547 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
548 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
549 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
550
551 ps_mem_rec++;
552 u1_no_rec++;
553
554 /* To store thread handle */
555 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
556 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
557 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
558
559 ps_mem_rec++;
560 u1_no_rec++;
561
562 /*************************************************************************/
563 /* Fill the memory requirement for Motion Compensation Buffers */
564 /*************************************************************************/
565 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
566 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
567
568 /* for mc_fw_buf.pu1_y */
569 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
570
571 /* for mc_fw_buf.pu1_u */
572 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
573
574 /* for mc_fw_buf.pu1_v */
575 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
576
577 /* for mc_bk_buf.pu1_y */
578 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
579
580 /* for mc_bk_buf.pu1_u */
581 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
582
583 /* for mc_bk_buf.pu1_v */
584 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
585
586 /* for mc_buf.pu1_y */
587 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
588
589 /* for mc_buf.pu1_u */
590 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
591
592 /* for mc_buf.pu1_v */
593 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
594
595 ps_mem_rec++;
596 u1_no_rec++;
597
598
599 /*************************************************************************/
600 /* Fill the memory requirement Stack Context */
601 /*************************************************************************/
602 /* ! */
603 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
604 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
605 ps_mem_rec->u4_mem_size = 392;
606
607 ps_mem_rec++;
608 u1_no_rec++;
609 }
610
611
612
613 {
614 /*************************************************************************/
615 /* Fill the memory requirement for Picture Buffer Manager */
616 /*************************************************************************/
617 /* ! */
618 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
619 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
620 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
621
622 ps_mem_rec++;
623 u1_no_rec++;
624 }
625 /*************************************************************************/
626 /* Internal Frame Buffers */
627 /*************************************************************************/
628 /* ! */
629
630 {
631 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
632 {
633 /* ! */
634 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
635 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
636 if(0 == i4_share_disp_buf)
637 ps_mem_rec->u4_mem_size = max_frm_size;
638 else if(IV_YUV_420P != i4_chroma_format)
639 {
640 /* If color format is not 420P and it is shared, then allocate for chroma */
641 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
642 }
643 else
644 ps_mem_rec->u4_mem_size = 64;
645 ps_mem_rec++;
646 u1_no_rec++;
647 }
648 }
649
650 ps_mem_rec->u4_mem_alignment = 128;
651 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
652 ps_mem_rec->u4_mem_size = MAX_BITSTREAM_BUFFER_SIZE + MIN_BUFFER_BYTES_AT_EOS;
653 ps_mem_rec++;
654 u1_no_rec++;
655
656 {
657 WORD32 i4_job_queue_size;
658 WORD32 i4_num_jobs;
659
660 /* One job per row of MBs */
661 i4_num_jobs = max_frm_height >> 4;
662
663 /* One format convert/frame copy job per row of MBs for non-shared mode*/
664 i4_num_jobs += max_frm_height >> 4;
665
666
667 i4_job_queue_size = impeg2_jobq_ctxt_size();
668 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
669 ps_mem_rec->u4_mem_size = i4_job_queue_size;
670 ps_mem_rec->u4_mem_alignment = 128;
671 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
672
673 ps_mem_rec++;
674 u1_no_rec++;
675
676 }
677
678 ps_mem_rec->u4_mem_alignment = 128;
679 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
680 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size();
681 ps_mem_rec++;
682 u1_no_rec++;
683
684 ps_mem_rec->u4_mem_alignment = 128;
685 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
686
687 if(IV_YUV_420P != i4_chroma_format)
688 ps_mem_rec->u4_mem_size = max_frm_size;
689 else
690 ps_mem_rec->u4_mem_size = 64;
691
692 ps_mem_rec++;
693 u1_no_rec++;
694
695 ps_mem_rec->u4_mem_alignment = 128;
696 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
697 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
698 ps_mem_rec++;
699 u1_no_rec++;
700
701 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
702 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
703 }
704
705
706 /*****************************************************************************/
707 /* */
708 /* Function Name : impeg2d_api_get_version */
709 /* */
710 /* Description : */
711 /* */
712 /* Inputs : */
713 /* Globals : <Does it use any global variables?> */
714 /* Outputs : */
715 /* Returns : void */
716 /* */
717 /* Issues : none */
718 /* */
719 /* Revision History: */
720 /* */
721 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
722 /* 22 10 2008 100356 Draft */
723 /* */
724 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)725 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
726 void *pv_api_ip,
727 void *pv_api_op)
728 {
729 char au1_version_string[512];
730
731 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
732 impeg2d_ctl_getversioninfo_op_t *ps_op;
733
734 UNUSED(ps_dechdl);
735
736 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
737 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
738
739 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
740
741 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
742 CODEC_VENDOR);
743
744 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
745 {
746 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
747 return (IV_FAIL);
748 }
749
750 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
751 >= (strlen(au1_version_string) + 1))
752 {
753 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
754 au1_version_string, (strlen(au1_version_string) + 1));
755 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
756 }
757 else
758 {
759 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
760 }
761
762 return (IV_SUCCESS);
763 }
764
765 /*****************************************************************************/
766 /* */
767 /* Function Name : impeg2d_api_get_buf_info */
768 /* */
769 /* Description : */
770 /* */
771 /* Inputs : */
772 /* Globals : <Does it use any global variables?> */
773 /* Outputs : */
774 /* Returns : void */
775 /* */
776 /* Issues : none */
777 /* */
778 /* Revision History: */
779 /* */
780 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
781 /* 22 10 2008 100356 Draft */
782 /* */
783 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)784 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
785 void *pv_api_ip,
786 void *pv_api_op)
787 {
788 dec_state_t *ps_dec_state;
789 dec_state_multi_core_t *ps_dec_state_multi_core;
790 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
791 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
792 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
793 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
794 UWORD32 u4_i, u4_stride, u4_height;
795 UNUSED(ps_ctl_bufinfo_ip);
796
797 ps_dec_state_multi_core =
798 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
799 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
800
801 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
802 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
803
804 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
805 {
806 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
807 0;
808 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
809 0;
810 }
811
812 for(u4_i = 0;
813 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
814 u4_i++)
815 {
816 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
817 MAX_BITSTREAM_BUFFER_SIZE;
818 }
819
820 if (0 == ps_dec_state->u4_frm_buf_stride)
821 {
822 if (1 == ps_dec_state->u2_header_done)
823 {
824 u4_stride = ps_dec_state->u2_horizontal_size;
825 }
826 else
827 {
828 u4_stride = ps_dec_state->u2_create_max_width;
829 }
830 }
831 else
832 {
833 u4_stride = ps_dec_state->u4_frm_buf_stride;
834 }
835 u4_stride = ALIGN16(u4_stride);
836 u4_height = ALIGN32(ps_dec_state->u2_frame_height) + 9;
837
838 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
839 impeg2d_get_outbuf_size(
840 u4_stride,
841 u4_height,
842 ps_dec_state->i4_chromaFormat,
843 &ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0]);
844
845 if (0 == ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs)
846 {
847 //Invalid chroma format; Error code may be updated, verify in testing if needed
848 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
849 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
850 return IV_FAIL;
851 }
852
853 /* Adding initialization for 2 uninitialized values */
854 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
855 if(ps_dec_state->u4_share_disp_buf)
856 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
857 NUM_INT_FRAME_BUFFERS;
858 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
859
860 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
861
862 return (IV_SUCCESS);
863 }
864
865 /*****************************************************************************/
866 /* */
867 /* Function Name : impeg2d_api_set_flush_mode */
868 /* */
869 /* Description : */
870 /* */
871 /* Inputs : */
872 /* Globals : <Does it use any global variables?> */
873 /* Outputs : */
874 /* Returns : void */
875 /* */
876 /* Issues : none */
877 /* */
878 /* Revision History: */
879 /* */
880 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
881 /* 08 06 2009 100356 RAVI */
882 /* */
883 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)884 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
885 void *pv_api_ip,
886 void *pv_api_op)
887 {
888 dec_state_t *ps_dec_state;
889 dec_state_multi_core_t *ps_dec_state_multi_core;
890 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
891 (impeg2d_ctl_flush_op_t*)pv_api_op;
892
893 UNUSED(pv_api_ip);
894
895 ps_dec_state_multi_core =
896 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
897 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
898
899 ps_dec_state->u1_flushfrm = 1;
900
901 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
902 sizeof(impeg2d_ctl_flush_op_t);
903 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
904
905 return (IV_SUCCESS);
906 }
907
908 /*****************************************************************************/
909 /* */
910 /* Function Name : impeg2d_api_set_default */
911 /* */
912 /* Description : */
913 /* */
914 /* Inputs : */
915 /* Globals : <Does it use any global variables?> */
916 /* Outputs : */
917 /* Returns : void */
918 /* */
919 /* Issues : none */
920 /* */
921 /* Revision History: */
922 /* */
923 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
924 /* 08 06 2009 100356 RAVI */
925 /* */
926 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)927 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
928 void *pv_api_ip,
929 void *pv_api_op)
930 {
931 dec_state_t *ps_dec_state;
932 dec_state_multi_core_t *ps_dec_state_multi_core;
933 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
934 (impeg2d_ctl_set_config_op_t *)pv_api_op;
935
936 UNUSED(pv_api_ip);
937
938 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
939 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
940 sizeof(impeg2d_ctl_set_config_op_t);
941
942 ps_dec_state_multi_core =
943 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
944 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
945
946 ps_dec_state->u1_flushfrm = 0;
947 ps_dec_state->u2_decode_header = 1;
948
949 if (1 == ps_dec_state->u2_header_done)
950 {
951 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
952 }
953
954 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
955
956 return (IV_SUCCESS);
957
958 }
959
960 /*****************************************************************************/
961 /* */
962 /* Function Name : impeg2d_api_reset */
963 /* */
964 /* Description : */
965 /* */
966 /* Inputs : */
967 /* Globals : <Does it use any global variables?> */
968 /* Outputs : */
969 /* Returns : void */
970 /* */
971 /* Issues : none */
972 /* */
973 /* Revision History: */
974 /* */
975 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
976 /* 08 06 2009 100356 RAVI */
977 /* */
978 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)979 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
980 void *pv_api_ip,
981 void *pv_api_op)
982 {
983 dec_state_t *ps_dec_state;
984 dec_state_multi_core_t *ps_dec_state_multi_core;
985 UNUSED(pv_api_ip);
986 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
987
988 WORD32 i4_num_threads;
989
990 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
991 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
992
993 if(ps_dec_state_multi_core != NULL)
994 {
995 impeg2_buf_mgr_reset(ps_dec_state->pv_pic_buf_mg);
996 /* Display buffer manager init behaves like a reset
997 * as it doesn't need to preserve picture buffer addresses
998 * like buffer manager */
999 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1000
1001 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1002 {
1003 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1004
1005
1006 /* --------------------------------------------------------------------- */
1007 /* Initializations */
1008
1009 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1010 ps_dec_state->u4_frm_buf_stride = 0;
1011 ps_dec_state->i4_pic_count = 0;
1012 ps_dec_state->u2_is_mpeg2 = 0;
1013 ps_dec_state->aps_ref_pics[0] = NULL;
1014 ps_dec_state->aps_ref_pics[1] = NULL;
1015 ps_dec_state->ps_deint_pic = NULL;
1016 }
1017 }
1018 else
1019 {
1020 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
1021 IMPEG2D_INIT_NOT_DONE;
1022 }
1023
1024 return(IV_SUCCESS);
1025 }
1026
1027 /*****************************************************************************/
1028 /* */
1029 /* Function Name : impeg2d_api_set_params */
1030 /* */
1031 /* Description : */
1032 /* */
1033 /* Inputs : */
1034 /* Globals : <Does it use any global variables?> */
1035 /* Outputs : */
1036 /* Returns : void */
1037 /* */
1038 /* Issues : none */
1039 /* */
1040 /* Revision History: */
1041 /* */
1042 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1043 /* 08 06 2009 100356 RAVI */
1044 /* */
1045 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1046 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
1047 {
1048 dec_state_t *ps_dec_state;
1049 dec_state_multi_core_t *ps_dec_state_multi_core;
1050 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
1051 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
1052
1053 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1054 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1055
1056 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
1057 {
1058 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1059 return(IV_FAIL);
1060 }
1061
1062 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
1063 {
1064 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1065 return(IV_FAIL);
1066 }
1067
1068 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
1069 {
1070 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1071 return(IV_FAIL);
1072 }
1073
1074 if(ps_dec_state->u2_header_done == 1)
1075 {
1076 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
1077 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
1078 {
1079 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1080 return(IV_FAIL);
1081 }
1082
1083 }
1084
1085
1086 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1087
1088 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1089 {
1090 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1091 }
1092 else
1093 {
1094
1095 if(ps_dec_state->u2_header_done == 1)
1096 {
1097 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1098 }
1099 else
1100 {
1101 ps_dec_state->u4_frm_buf_stride = 0;
1102 }
1103 }
1104
1105
1106 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1107 {
1108 ps_dec_state->u1_flushfrm = 0;
1109 }
1110
1111
1112 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1113 return(IV_SUCCESS);
1114
1115 }
1116
1117 /*****************************************************************************/
1118 /* */
1119 /* Function Name : impeg2d_api_get_status */
1120 /* */
1121 /* Description : */
1122 /* */
1123 /* Inputs : */
1124 /* Globals : <Does it use any global variables?> */
1125 /* Outputs : */
1126 /* Returns : void */
1127 /* */
1128 /* Issues : none */
1129 /* */
1130 /* Revision History: */
1131 /* */
1132 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1133 /* 08 06 2009 100356 RAVI */
1134 /* */
1135 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1136 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1137 void *pv_api_ip,
1138 void *pv_api_op)
1139 {
1140 dec_state_t *ps_dec_state;
1141 dec_state_multi_core_t *ps_dec_state_multi_core;
1142 UWORD32 u4_i,u4_stride,u4_height;
1143 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1144 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1145 UNUSED(ps_ctl_dec_ip);
1146
1147 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1148 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1149
1150 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1151 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1152 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1153 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1154 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1155
1156
1157 if(ps_dec_state->u2_progressive_sequence == 1)
1158 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1159 else
1160 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1161
1162
1163 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1164 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1165 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1166
1167
1168 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1169 {
1170 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1171 }
1172 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1173 {
1174 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1175 }
1176 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1177 {
1178 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1179 }
1180 else
1181 {
1182 //Invalid chroma format; Error code may be updated, verify in testing if needed
1183 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1184 return IV_FAIL;
1185 }
1186
1187 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1188 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1189
1190 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1191 {
1192 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1193 }
1194
1195 u4_stride = ps_dec_state->u4_frm_buf_stride;
1196 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1197
1198 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1199 {
1200 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1201 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1202 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1203 }
1204 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1205 {
1206 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1207 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1208 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1209 }
1210 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1211 {
1212 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1213 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1214 }
1215
1216 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1217
1218 return(IV_SUCCESS);
1219
1220 }
1221
1222 /**
1223 *******************************************************************************
1224 *
1225 * @brief
1226 * Gets frame dimensions/offsets
1227 *
1228 * @par Description:
1229 * Gets frame buffer chararacteristics such a x & y offsets display and
1230 * buffer dimensions
1231 *
1232 * @param[in] ps_codec_obj
1233 * Pointer to codec object at API level
1234 *
1235 * @param[in] pv_api_ip
1236 * Pointer to input argument structure
1237 *
1238 * @param[out] pv_api_op
1239 * Pointer to output argument structure
1240 *
1241 * @returns Status
1242 *
1243 * @remarks
1244 *
1245 *
1246 *******************************************************************************
1247 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1248 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1249 void *pv_api_ip,
1250 void *pv_api_op)
1251 {
1252 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1253 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1254 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1255 dec_state_t *ps_codec;
1256 dec_state_multi_core_t *ps_dec_state_multi_core;
1257
1258 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1259 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1260
1261
1262 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1263 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1264 UNUSED(ps_ip);
1265 if(ps_codec->u2_header_done)
1266 {
1267 disp_wd = ps_codec->u2_horizontal_size;
1268 disp_ht = ps_codec->u2_vertical_size;
1269
1270 if(0 == ps_codec->u4_share_disp_buf)
1271 {
1272 buffer_wd = disp_wd;
1273 buffer_ht = disp_ht;
1274 }
1275 else
1276 {
1277 buffer_wd = ps_codec->u2_frame_width;
1278 buffer_ht = ps_codec->u2_frame_height;
1279 }
1280 }
1281 else
1282 {
1283
1284 disp_wd = ps_codec->u2_create_max_width;
1285 disp_ht = ps_codec->u2_create_max_height;
1286
1287 if(0 == ps_codec->u4_share_disp_buf)
1288 {
1289 buffer_wd = disp_wd;
1290 buffer_ht = disp_ht;
1291 }
1292 else
1293 {
1294 buffer_wd = ALIGN16(disp_wd);
1295 buffer_ht = ALIGN16(disp_ht);
1296
1297 }
1298 }
1299 if(ps_codec->u2_frame_width > buffer_wd)
1300 buffer_wd = ps_codec->u2_frame_width;
1301
1302 x_offset = 0;
1303 y_offset = 0;
1304
1305
1306 ps_op->u4_disp_wd[0] = disp_wd;
1307 ps_op->u4_disp_ht[0] = disp_ht;
1308 ps_op->u4_buffer_wd[0] = buffer_wd;
1309 ps_op->u4_buffer_ht[0] = buffer_ht;
1310 ps_op->u4_x_offset[0] = x_offset;
1311 ps_op->u4_y_offset[0] = y_offset;
1312
1313 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1314 >> 1);
1315 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1316 >> 1);
1317 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1318 >> 1);
1319 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1320 >> 1);
1321 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1322 >> 1);
1323 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1324 >> 1);
1325
1326 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1327 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1328 {
1329 ps_op->u4_disp_wd[2] = 0;
1330 ps_op->u4_disp_ht[2] = 0;
1331 ps_op->u4_buffer_wd[2] = 0;
1332 ps_op->u4_buffer_ht[2] = 0;
1333 ps_op->u4_x_offset[2] = 0;
1334 ps_op->u4_y_offset[2] = 0;
1335
1336 ps_op->u4_disp_wd[1] <<= 1;
1337 ps_op->u4_buffer_wd[1] <<= 1;
1338 ps_op->u4_x_offset[1] <<= 1;
1339 }
1340
1341 return IV_SUCCESS;
1342
1343 }
1344
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1345 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1346 {
1347 WORD32 i4_cmd;
1348 IV_API_CALL_STATUS_T u4_error_code;
1349 UWORD32 *pu4_api_ip;
1350
1351 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1352 if(IV_SUCCESS != u4_error_code)
1353 {
1354 return u4_error_code;
1355 }
1356
1357
1358 pu4_api_ip = (UWORD32 *)pv_api_ip;
1359 i4_cmd = *(pu4_api_ip + 1);
1360
1361 switch(i4_cmd)
1362 {
1363
1364 case IV_CMD_GET_NUM_MEM_REC:
1365 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1366 break;
1367
1368 case IV_CMD_FILL_NUM_MEM_REC:
1369 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1370 break;
1371
1372 case IV_CMD_INIT:
1373 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1374 break;
1375
1376 case IVD_CMD_SET_DISPLAY_FRAME:
1377 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1378 break;
1379
1380 case IVD_CMD_REL_DISPLAY_FRAME:
1381 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1382 break;
1383
1384 case IVD_CMD_VIDEO_DECODE:
1385 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1386 break;
1387
1388 case IV_CMD_RETRIEVE_MEMREC:
1389 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1390 break;
1391
1392 case IVD_CMD_VIDEO_CTL:
1393 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1394 break;
1395
1396 default:
1397 break;
1398 }
1399
1400 return(u4_error_code);
1401
1402 }
1403
1404 /*****************************************************************************/
1405 /* */
1406 /* Function Name : impeg2d_api_num_mem_rec */
1407 /* */
1408 /* Description : The function get the number mem records library needs */
1409 /* Inputs : Error message */
1410 /* Globals : None */
1411 /* Processing : Just prints error message to console */
1412 /* Outputs : Error mesage to the console */
1413 /* Returns : None */
1414 /* */
1415 /* Issues : <List any issues or problems with this function> */
1416 /* */
1417 /* Revision History: */
1418 /* */
1419 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1420 /* 23 09 2010 Hamsalekha Creation */
1421 /* */
1422 /*****************************************************************************/
1423
1424
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1425 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1426 {
1427 /* To Query No of Memory Records */
1428 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1429 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1430
1431 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1432 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1433
1434 UNUSED(ps_query_mem_rec_ip);
1435 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1436
1437 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1438
1439 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1440
1441
1442 return(IV_SUCCESS);
1443
1444 }
1445
1446
1447 /*****************************************************************************/
1448 /* */
1449 /* Function Name : impeg2d_api_fill_mem_rec */
1450 /* */
1451 /* Description : Thsi functions fills details of each mem record lib needs*/
1452 /* Inputs : Error message */
1453 /* Globals : None */
1454 /* Processing : Just prints error message to console */
1455 /* Outputs : Error mesage to the console */
1456 /* Returns : None */
1457 /* */
1458 /* Issues : <List any issues or problems with this function> */
1459 /* */
1460 /* Revision History: */
1461 /* */
1462 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1463 /* 23 09 2010 Hamsalekha Creation */
1464 /* */
1465 /*****************************************************************************/
1466
1467
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1468 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1469 {
1470
1471 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1472 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1473
1474
1475 ps_mem_q_ip = pv_api_ip;
1476 ps_mem_q_op = pv_api_op;
1477
1478
1479 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1480 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1481
1482
1483 return(IV_SUCCESS);
1484
1485 }
1486
impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,WORD32 u1_chroma_format,UWORD32 * p_buf_size)1487 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size)
1488 {
1489 UWORD32 u4_min_num_out_bufs = 0;
1490 if(u1_chroma_format == IV_YUV_420P)
1491 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1492 else if(u1_chroma_format == IV_YUV_422ILE)
1493 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1494 else if(u1_chroma_format == IV_RGB_565)
1495 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1496 else if((u1_chroma_format == IV_YUV_420SP_UV)
1497 || (u1_chroma_format == IV_YUV_420SP_VU))
1498 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
1499
1500 if(u1_chroma_format == IV_YUV_420P)
1501 {
1502 p_buf_size[0] = (pic_wd * pic_ht);
1503 p_buf_size[1] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1);
1504 p_buf_size[2] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1);
1505 }
1506 else if(u1_chroma_format == IV_YUV_422ILE)
1507 {
1508 p_buf_size[0] = (pic_wd * pic_ht)
1509 * 2;
1510 p_buf_size[1] =
1511 p_buf_size[2] = 0;
1512 }
1513 else if(u1_chroma_format == IV_RGB_565)
1514 {
1515 p_buf_size[0] = (pic_wd * pic_ht)
1516 * 2;
1517 p_buf_size[1] =
1518 p_buf_size[2] = 0;
1519 }
1520 else if((u1_chroma_format == IV_YUV_420SP_UV)
1521 || (u1_chroma_format == IV_YUV_420SP_VU))
1522 {
1523 p_buf_size[0] = (pic_wd * pic_ht);
1524 p_buf_size[1] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1) * 2;
1525 p_buf_size[2] = 0;
1526 }
1527 return u4_min_num_out_bufs;
1528 }
1529
check_app_out_buf_size(dec_state_t * ps_dec)1530 WORD32 check_app_out_buf_size(dec_state_t *ps_dec)
1531 {
1532 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1533 UWORD32 u4_min_num_out_bufs, i;
1534 UWORD32 pic_wd, pic_ht;
1535
1536 pic_wd = ps_dec->u2_horizontal_size;
1537 pic_ht = ps_dec->u2_vertical_size;
1538
1539 if(ps_dec->u4_frm_buf_stride > pic_wd)
1540 pic_wd = ps_dec->u4_frm_buf_stride;
1541
1542 u4_min_num_out_bufs = impeg2d_get_outbuf_size(pic_wd, pic_ht, ps_dec->i4_chromaFormat, &au4_min_out_buf_size[0]);
1543
1544 if (0 == ps_dec->u4_share_disp_buf)
1545 {
1546 if(ps_dec->ps_out_buf->u4_num_bufs < u4_min_num_out_bufs)
1547 {
1548 return IV_FAIL;
1549 }
1550
1551 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1552 {
1553 if(ps_dec->ps_out_buf->u4_min_out_buf_size[i] < au4_min_out_buf_size[i])
1554 return (IV_FAIL);
1555 }
1556 }
1557 else
1558 {
1559 if(ps_dec->as_disp_buffers[0].u4_num_bufs < u4_min_num_out_bufs)
1560 return IV_FAIL;
1561
1562 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1563 {
1564 /* We need to check only with the disp_buffer[0], because we have
1565 * already ensured that all the buffers are of the same size in
1566 * impeg2d_api_set_display_frame.
1567 */
1568 if(ps_dec->as_disp_buffers[0].u4_min_out_buf_size[i] <
1569 au4_min_out_buf_size[i])
1570 return (IV_FAIL);
1571 }
1572 }
1573
1574 return(IV_SUCCESS);
1575 }
1576
1577
1578
1579 /*****************************************************************************/
1580 /* */
1581 /* Function Name : impeg2d_api_init */
1582 /* */
1583 /* Description : */
1584 /* Inputs : */
1585 /* Globals : */
1586 /* Processing : */
1587 /* Outputs : */
1588 /* Returns : */
1589 /* */
1590 /* Issues : */
1591 /* */
1592 /* Revision History: */
1593 /* */
1594 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1595 /* 17 09 2007 Rajendra C Y Draft */
1596 /* */
1597 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1598 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1599 void *ps_ip,
1600 void *ps_op)
1601 {
1602 UWORD32 i;
1603
1604 void *pv;
1605 UWORD32 u4_size;
1606
1607 dec_state_t *ps_dec_state;
1608 dec_state_multi_core_t *ps_dec_state_multi_core;
1609 UWORD32 u4_num_mem_rec;
1610 iv_mem_rec_t *ps_mem_rec ;
1611 iv_mem_rec_t *ps_frm_buf;
1612 iv_obj_t *ps_dec_handle;
1613 WORD32 i4_max_wd, i4_max_ht;
1614
1615 impeg2d_init_ip_t *ps_dec_init_ip;
1616 impeg2d_init_op_t *ps_dec_init_op;
1617 WORD32 i4_num_threads;
1618 UWORD32 u4_share_disp_buf, u4_chroma_format;
1619 UWORD32 u4_deinterlace;
1620
1621 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1622 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1623
1624 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1625 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1626
1627 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1628 {
1629 #ifndef LOGO_EN
1630 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1631 #else
1632 u4_share_disp_buf = 0;
1633 #endif
1634 }
1635 else
1636 {
1637 u4_share_disp_buf = 0;
1638 }
1639
1640 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1641
1642 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace))
1643 {
1644 u4_deinterlace = ps_dec_init_ip->u4_deinterlace;
1645 }
1646 else
1647 {
1648 u4_deinterlace = 0;
1649 }
1650
1651 if( (u4_chroma_format != IV_YUV_420P) &&
1652 (u4_chroma_format != IV_YUV_420SP_UV) &&
1653 (u4_chroma_format != IV_YUV_420SP_VU))
1654 {
1655 u4_share_disp_buf = 0;
1656 }
1657
1658 /* Disable deinterlacer in shared mode */
1659 if(u4_share_disp_buf)
1660 {
1661 u4_deinterlace = 0;
1662 }
1663
1664 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1665 ps_mem_rec ++;
1666
1667
1668 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1669
1670
1671 /* Except memTab[0], all other memTabs are initialized to zero */
1672 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1673 {
1674 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1675 ps_mem_rec++;
1676 }
1677
1678 /* Reinitializing memTab[0] memory base address */
1679 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1680
1681
1682 /* memTab[0] is for codec Handle,redundant currently not being used */
1683 ps_dec_handle = ps_mem_rec->pv_base;
1684 u4_num_mem_rec = 1;
1685 ps_mem_rec++;
1686
1687
1688
1689
1690
1691 /* decoder handle */
1692 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1693 u4_num_mem_rec++;
1694 ps_mem_rec++;
1695
1696
1697 {
1698 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1699
1700 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1701 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1702 }
1703
1704
1705 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1706 {
1707 /*************************************************************************/
1708 /* For MPEG2 Decoder Context */
1709 /*************************************************************************/
1710 ps_dec_state = ps_mem_rec->pv_base;
1711
1712 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1713
1714 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1715
1716 ps_dec_state->i4_num_cores = 1;
1717 /* @ */ /* Used for storing MemRecords */
1718 u4_num_mem_rec++;
1719 ps_mem_rec++;
1720
1721 /* Thread handle */
1722 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1723 u4_num_mem_rec++;
1724 ps_mem_rec++;
1725
1726 /*************************************************************************/
1727 /* For Motion Compensation Buffers */
1728 /*************************************************************************/
1729 pv = ps_mem_rec->pv_base;
1730
1731 /* for mc_fw_buf.pu1_y */
1732
1733 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1734 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1735
1736 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1737 /* for mc_fw_buf.pu1_u */
1738
1739 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1740 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1741
1742 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1743
1744 /* for mc_fw_buf.pu1_v */
1745
1746 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1747 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1748
1749 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1750
1751 /* for mc_bk_buf.pu1_y */
1752
1753 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1754 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1755
1756 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1757
1758 /* for mc_bk_buf.pu1_u */
1759
1760 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1761 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1762
1763 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1764
1765 /* for mc_bk_buf.pu1_v */
1766
1767 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1768 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1769
1770 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1771
1772 /* for mc_buf.pu1_y */
1773
1774 ps_dec_state->s_mc_buf.pu1_y = pv;
1775 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1776
1777 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1778
1779 /* for mc_buf.pu1_u */
1780
1781 ps_dec_state->s_mc_buf.pu1_u = pv;
1782 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1783
1784 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1785
1786 /* for mc_buf.pu1_v */
1787
1788 ps_dec_state->s_mc_buf.pu1_v = pv;
1789
1790 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1791
1792 u4_num_mem_rec++;
1793 ps_mem_rec++;
1794
1795
1796
1797 ps_dec_state->pv_pic_buf_mg = 0;
1798
1799 /*************************************************************************/
1800 /* For saving stack context to support global error handling */
1801 /*************************************************************************/
1802 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1803 u4_num_mem_rec++;
1804 ps_mem_rec++;
1805
1806 }
1807
1808
1809
1810
1811
1812 /*************************************************************************/
1813 /* For Picture Buffer Manager */
1814 /*************************************************************************/
1815 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1816
1817 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1818 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1819
1820 u4_num_mem_rec++;
1821 ps_mem_rec++;
1822
1823
1824
1825 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1826 {
1827
1828 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1829
1830
1831 /* --------------------------------------------------------------------- */
1832 /* Initializations */
1833
1834 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1835
1836
1837 {
1838 UWORD32 u4_max_frm_width,u4_max_frm_height;
1839
1840 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1841 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1842
1843 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1844 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1845
1846 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1847 ps_dec_state->u4_frm_buf_stride = 0 ;
1848 ps_dec_state->u2_frame_width = u4_max_frm_width;
1849 ps_dec_state->u2_picture_width = u4_max_frm_width;
1850 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1851
1852 ps_dec_state->u2_frame_height = u4_max_frm_height;
1853 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1854 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1855 ps_dec_state->u4_deinterlace = u4_deinterlace;
1856 ps_dec_state->ps_deint_pic = NULL;
1857 }
1858 }
1859
1860 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1861
1862 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1863 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1864 {
1865 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1866 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1867 return(IV_FAIL);
1868
1869
1870 }
1871
1872 /* --------------------------------------------------------------------- */
1873
1874
1875 /* ! */
1876 // picture buffer manager initialization will be done only for first thread
1877 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1878 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1879
1880 /*************************************************************************/
1881 /* Internal Frame Buffers */
1882 /*************************************************************************/
1883
1884
1885 /* Set first frame to grey */
1886 {
1887 ps_frm_buf = ps_mem_rec;
1888 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
1889 ps_frm_buf++;
1890 }
1891
1892 if(0 == ps_dec_state->u4_share_disp_buf)
1893 {
1894 pic_buf_t *ps_pic_buf;
1895 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
1896 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1897 {
1898 UWORD8 *pu1_buf;
1899 pu1_buf = ps_mem_rec->pv_base;
1900
1901 ps_pic_buf->pu1_y = pu1_buf;
1902 pu1_buf += i4_max_ht * i4_max_wd;
1903
1904 ps_pic_buf->pu1_u = pu1_buf;
1905 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1906
1907 ps_pic_buf->pu1_v = pu1_buf;
1908 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1909
1910 ps_pic_buf->i4_buf_id = i;
1911
1912 ps_pic_buf->u1_used_as_ref = 0;
1913
1914 ps_pic_buf->u4_ts = 0;
1915
1916 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
1917 ps_mem_rec++;
1918 ps_pic_buf++;
1919 }
1920 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1921 }
1922 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
1923 {
1924 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1925 {
1926 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
1927 ps_mem_rec++;
1928 }
1929
1930 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1931 }
1932 else
1933 {
1934 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
1935 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1936 }
1937
1938
1939 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1940
1941 ps_dec_state->pu1_input_buffer = ps_mem_rec->pv_base;
1942 u4_num_mem_rec++;
1943 ps_mem_rec++;
1944
1945 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
1946 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
1947 u4_num_mem_rec++;
1948 ps_mem_rec++;
1949
1950 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
1951 {
1952 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
1953 return(IV_FAIL);
1954
1955 }
1956
1957 ps_dec_state->u1_flushfrm = 0;
1958 ps_dec_state->u1_flushcnt = 0;
1959 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
1960
1961
1962 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base;
1963 u4_num_mem_rec++;
1964 ps_mem_rec++;
1965
1966 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base;
1967 u4_num_mem_rec++;
1968 ps_mem_rec++;
1969
1970
1971 /*************************************************************************/
1972 /* Last MemTab is used for storing TabRecords */
1973 /*************************************************************************/
1974 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
1975 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
1976 /* Updating in Decoder Context with memRecords */
1977 u4_num_mem_rec++;
1978 ps_mem_rec++;
1979 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
1980
1981
1982 ps_dec_state->u4_num_frames_decoded = 0;
1983 ps_dec_state->aps_ref_pics[0] = NULL;
1984 ps_dec_state->aps_ref_pics[1] = NULL;
1985
1986 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
1987
1988 impeg2d_init_arch(ps_dec_state);
1989
1990 impeg2d_init_function_ptr(ps_dec_state);
1991
1992 return(IV_SUCCESS);
1993 }
1994
1995 /*****************************************************************************/
1996 /* */
1997 /* Function Name : impeg2d_api_retrieve_mem_rec */
1998 /* */
1999 /* Description : */
2000 /* */
2001 /* Inputs : */
2002 /* Globals : <Does it use any global variables?> */
2003 /* Outputs : */
2004 /* Returns : void */
2005 /* */
2006 /* Issues : none */
2007 /* */
2008 /* Revision History: */
2009 /* */
2010 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2011 /* 22 10 2008 100356 Draft */
2012 /* */
2013 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2014 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
2015 void *pv_api_ip,
2016 void *pv_api_op)
2017 {
2018 UWORD32 u4_i;
2019 dec_state_t *ps_dec_state;
2020 dec_state_multi_core_t *ps_dec_state_multi_core;
2021 iv_mem_rec_t *ps_mem_rec;
2022 iv_mem_rec_t *ps_temp_rec;
2023
2024
2025
2026 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
2027 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
2028
2029 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2030 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2031
2032 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2033 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
2034 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
2035 ps_temp_rec = ps_dec_state->pv_memTab;
2036
2037 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
2038 {
2039 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
2040 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
2041 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
2042 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
2043 }
2044
2045 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
2046 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
2047
2048 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
2049 IMPEG2D_PRINT_STATISTICS();
2050
2051
2052 return(IV_SUCCESS);
2053
2054 }
2055
2056 /*****************************************************************************/
2057 /* */
2058 /* Function Name : impeg2d_api_ctl */
2059 /* */
2060 /* Description : */
2061 /* */
2062 /* Inputs : */
2063 /* Globals : <Does it use any global variables?> */
2064 /* Outputs : */
2065 /* Returns : void */
2066 /* */
2067 /* Issues : none */
2068 /* */
2069 /* Revision History: */
2070 /* */
2071 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2072 /* 22 10 2008 100356 Draft */
2073 /* */
2074 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2075 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
2076 void *pv_api_ip,
2077 void *pv_api_op)
2078 {
2079 WORD32 i4_sub_cmd;
2080 UWORD32 *pu4_api_ip;
2081 IV_API_CALL_STATUS_T u4_error_code;
2082
2083 pu4_api_ip = (UWORD32 *)pv_api_ip;
2084 i4_sub_cmd = *(pu4_api_ip + 2);
2085
2086 switch(i4_sub_cmd)
2087 {
2088 case IVD_CMD_CTL_GETPARAMS:
2089 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
2090 (void *)pv_api_op);
2091 break;
2092
2093 case IVD_CMD_CTL_SETPARAMS:
2094 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
2095 (void *)pv_api_op);
2096 break;
2097
2098 case IVD_CMD_CTL_RESET:
2099 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
2100 (void *)pv_api_op);
2101 break;
2102
2103 case IVD_CMD_CTL_SETDEFAULT:
2104 u4_error_code = impeg2d_api_set_default(ps_dechdl,
2105 (void *)pv_api_ip,
2106 (void *)pv_api_op);
2107 break;
2108
2109 case IVD_CMD_CTL_FLUSH:
2110 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
2111 (void *)pv_api_ip,
2112 (void *)pv_api_op);
2113 break;
2114
2115 case IVD_CMD_CTL_GETBUFINFO:
2116 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
2117 (void *)pv_api_ip,
2118 (void *)pv_api_op);
2119 break;
2120
2121 case IVD_CMD_CTL_GETVERSION:
2122 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
2123 (void *)pv_api_op);
2124 break;
2125
2126 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2127 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
2128 (void *)pv_api_ip,
2129 (void *)pv_api_op);
2130 break;
2131
2132 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2133 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
2134 (void *)pv_api_ip,
2135 (void *)pv_api_op);
2136 break;
2137
2138 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2139 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl,
2140 (void *)pv_api_ip,
2141 (void *)pv_api_op);
2142 break;
2143
2144 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2145 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
2146 (void *)pv_api_op);
2147 break;
2148
2149 default:
2150 u4_error_code = IV_FAIL;
2151 break;
2152 }
2153
2154 return (u4_error_code);
2155
2156 }
2157
2158 /*****************************************************************************/
2159 /* */
2160 /* Function Name : impeg2d_api_check_struct_sanity */
2161 /* */
2162 /* Description : */
2163 /* */
2164 /* Inputs : */
2165 /* Globals : <Does it use any global variables?> */
2166 /* Outputs : */
2167 /* Returns : void */
2168 /* */
2169 /* Issues : none */
2170 /* */
2171 /* Revision History: */
2172 /* */
2173 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2174 /* 22 10 2008 100356 Draft */
2175 /* */
2176 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)2177 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
2178 void *pv_api_ip,
2179 void *pv_api_op)
2180 {
2181 WORD32 i4_cmd;
2182 UWORD32 *pu4_api_ip;
2183 UWORD32 *pu4_api_op;
2184 WORD32 i,j;
2185
2186 if(NULL == pv_api_op)
2187 return(IV_FAIL);
2188
2189 if(NULL == pv_api_ip)
2190 return(IV_FAIL);
2191
2192 pu4_api_ip = (UWORD32 *)pv_api_ip;
2193 pu4_api_op = (UWORD32 *)pv_api_op;
2194 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2195
2196 /* error checks on handle */
2197 switch(i4_cmd)
2198 {
2199 case IV_CMD_GET_NUM_MEM_REC:
2200 case IV_CMD_FILL_NUM_MEM_REC:
2201 break;
2202 case IV_CMD_INIT:
2203 if(ps_handle == NULL)
2204 {
2205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2206 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2207 return IV_FAIL;
2208 }
2209
2210 if(ps_handle->u4_size != sizeof(iv_obj_t))
2211 {
2212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2213 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2214 return IV_FAIL;
2215 }
2216 break;
2217 case IVD_CMD_GET_DISPLAY_FRAME:
2218 case IVD_CMD_VIDEO_DECODE:
2219 case IV_CMD_RETRIEVE_MEMREC:
2220 case IVD_CMD_SET_DISPLAY_FRAME:
2221 case IVD_CMD_REL_DISPLAY_FRAME:
2222 case IVD_CMD_VIDEO_CTL:
2223 {
2224 if(ps_handle == NULL)
2225 {
2226 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2227 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2228 return IV_FAIL;
2229 }
2230
2231 if(ps_handle->u4_size != sizeof(iv_obj_t))
2232 {
2233 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2234 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2235 return IV_FAIL;
2236 }
2237 if(ps_handle->pv_fxns != impeg2d_api_function)
2238 {
2239 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2240 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2241 return IV_FAIL;
2242 }
2243
2244 if(ps_handle->pv_codec_handle == NULL)
2245 {
2246 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2247 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2248 return IV_FAIL;
2249 }
2250 }
2251 break;
2252 default:
2253 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2254 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2255 return IV_FAIL;
2256 }
2257
2258 switch(i4_cmd)
2259 {
2260 case IV_CMD_GET_NUM_MEM_REC:
2261 {
2262 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2263 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2264 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2265
2266 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2267 {
2268 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2269 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2270 return(IV_FAIL);
2271 }
2272
2273 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2274 {
2275 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2276 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2277 return(IV_FAIL);
2278 }
2279 }
2280 break;
2281 case IV_CMD_FILL_NUM_MEM_REC:
2282 {
2283 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2284 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2285 iv_mem_rec_t *ps_mem_rec;
2286
2287 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2288
2289 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2290 {
2291 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2292 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2293 return(IV_FAIL);
2294 }
2295
2296 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2297 {
2298 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2299 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2300 return(IV_FAIL);
2301 }
2302
2303 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2304 {
2305 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2306 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2307 return(IV_FAIL);
2308 }
2309
2310 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2311 {
2312 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2313 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2314 return(IV_FAIL);
2315 }
2316
2317 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2318 {
2319 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2320 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2321 return(IV_FAIL);
2322 }
2323
2324 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2325 {
2326 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2327 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2328 return(IV_FAIL);
2329 }
2330
2331 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2332 {
2333 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2334 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2335 return(IV_FAIL);
2336 }
2337
2338 /* check memrecords sizes are correct */
2339 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2340 for(i=0;i<NUM_MEM_RECORDS;i++)
2341 {
2342 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2343 {
2344 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2345 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2346 return IV_FAIL;
2347 }
2348 }
2349 }
2350 break;
2351
2352 case IV_CMD_INIT:
2353 {
2354 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2355 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2356 iv_mem_rec_t *ps_mem_rec;
2357 UWORD32 u4_tot_num_mem_recs;
2358
2359 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2360
2361 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2362 {
2363 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2364 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2365 return(IV_FAIL);
2366 }
2367
2368 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2369 {
2370 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2371 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2372 return(IV_FAIL);
2373 }
2374
2375 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2376
2377
2378
2379
2380 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2381 {
2382 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2383 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2384 return(IV_FAIL);
2385 }
2386
2387 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2388 {
2389 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2390 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2391 return(IV_FAIL);
2392 }
2393
2394 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2395 {
2396 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2397 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2398 return(IV_FAIL);
2399 }
2400
2401 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2402 {
2403 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2404 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2405 return(IV_FAIL);
2406 }
2407
2408 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2409 {
2410 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2411 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2412 return(IV_FAIL);
2413 }
2414
2415 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2416 {
2417 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2418 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2419 return(IV_FAIL);
2420 }
2421
2422 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2423 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2424 {
2425 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2426 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2427 return(IV_FAIL);
2428 }
2429
2430 /* verify number of mem records */
2431 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2432 {
2433 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2434 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2435 return IV_FAIL;
2436 }
2437
2438 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2439 /* verify wether first memrecord is handle or not */
2440 /*
2441 if(ps_mem_rec->pv_base != ps_handle)
2442 {
2443 // indicate the incorrect handle error
2444 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2445 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2446 return IV_FAIL;
2447 }
2448 */
2449 /* check memrecords sizes are correct */
2450 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2451 {
2452 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2453 {
2454 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2455 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2456 return IV_FAIL;
2457 }
2458 }
2459
2460 /* verify memtabs for overlapping regions */
2461 {
2462 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2463 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2464
2465
2466 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2467 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2468 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2469 {
2470 /* This array is populated to check memtab overlapp */
2471 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2472 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2473
2474 for(j = 0; j < i; j++)
2475 {
2476 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2477 {
2478 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2479 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2480 return IV_FAIL;
2481 }
2482
2483 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2484 {
2485 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2486 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2487 return IV_FAIL;
2488 }
2489
2490 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2491 {
2492 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2493 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2494 return IV_FAIL;
2495 }
2496 }
2497 }
2498 }
2499
2500
2501
2502
2503 {
2504 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2505
2506 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2507 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2508 IV_API_CALL_STATUS_T e_status;
2509 WORD32 i4_num_memrec;
2510 {
2511
2512 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2513 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2514
2515
2516 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2517 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2518
2519 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2520 impeg2d_api_function(NULL,
2521 (void *)&s_no_of_mem_rec_query_ip,
2522 (void *)&s_no_of_mem_rec_query_op);
2523
2524 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2525
2526
2527
2528 }
2529
2530
2531 /* initialize mem records array with sizes */
2532 for(i = 0; i < i4_num_memrec; i++)
2533 {
2534 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2535 }
2536
2537 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2538 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2539 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2540 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2541 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2542 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2543 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2544 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2545
2546
2547 e_status = impeg2d_api_function(NULL,
2548 (void *)&s_fill_mem_rec_ip,
2549 (void *)&s_fill_mem_rec_op);
2550 if(IV_FAIL == e_status)
2551 {
2552 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2553 return(IV_FAIL);
2554 }
2555
2556
2557
2558 for(i = 0; i < i4_num_memrec; i ++)
2559 {
2560 if(ps_mem_rec[i].pv_base == NULL)
2561 {
2562 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2563 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2564 return IV_FAIL;
2565 }
2566 #ifdef CHECK_ALIGN
2567
2568 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2569 {
2570 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2571 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2572 return IV_FAIL;
2573 }
2574 #endif //CHECK_ALIGN
2575 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2576 {
2577 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2578 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2579 return IV_FAIL;
2580 }
2581
2582 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2583 {
2584 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2585 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2586 return IV_FAIL;
2587 }
2588
2589 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2590 {
2591 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2592 {
2593 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2594 {
2595 continue;
2596 }
2597 }
2598 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2599 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2600 return IV_FAIL;
2601 }
2602 }
2603 }
2604
2605
2606 }
2607 break;
2608
2609 case IVD_CMD_GET_DISPLAY_FRAME:
2610 {
2611 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2612 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2613
2614 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2615
2616 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2617 {
2618 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2619 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2620 return(IV_FAIL);
2621 }
2622
2623 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2624 {
2625 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2626 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2627 return(IV_FAIL);
2628 }
2629
2630 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2631 {
2632 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2633 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2634 return IV_FAIL;
2635 }
2636
2637 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2638 {
2639 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2640 {
2641 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2642 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2643 return IV_FAIL;
2644 }
2645
2646 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2647 {
2648 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2649 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2650 return IV_FAIL;
2651 }
2652 /*
2653 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2654 {
2655 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2656 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2657 return IV_FAIL;
2658 }
2659 */
2660 }
2661 }
2662 break;
2663 case IVD_CMD_REL_DISPLAY_FRAME:
2664 {
2665 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2666 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2667
2668 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2669
2670 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2671 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2672 {
2673 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2674 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2675 return(IV_FAIL);
2676 }
2677
2678 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2679 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2680 {
2681 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2682 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2683 return(IV_FAIL);
2684 }
2685
2686 }
2687 break;
2688
2689
2690 case IVD_CMD_SET_DISPLAY_FRAME:
2691 {
2692 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2693 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2694 UWORD32 j, i;
2695
2696 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2697
2698 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2699 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2700 {
2701 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2702 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2703 return(IV_FAIL);
2704 }
2705
2706 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2707 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2708 {
2709 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2710 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2711 return(IV_FAIL);
2712 }
2713
2714 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2715 {
2716 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2717 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2718 return IV_FAIL;
2719 }
2720
2721 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2722 {
2723 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2724 {
2725 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2726 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2727 return IV_FAIL;
2728 }
2729
2730 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2731 {
2732 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2733 {
2734 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2735 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2736 return IV_FAIL;
2737 }
2738
2739 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2740 {
2741 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2742 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2743 return IV_FAIL;
2744 }
2745 }
2746 }
2747 }
2748 break;
2749
2750 case IVD_CMD_VIDEO_DECODE:
2751 {
2752 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2753 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2754
2755 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2756
2757 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2758 {
2759 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2760 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2761 return(IV_FAIL);
2762 }
2763
2764 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2765 {
2766 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2767 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2768 return(IV_FAIL);
2769 }
2770
2771 }
2772 break;
2773
2774 case IV_CMD_RETRIEVE_MEMREC:
2775 {
2776 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2777 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2778 iv_mem_rec_t *ps_mem_rec;
2779
2780 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2781
2782 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2783 {
2784 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2785 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2786 return(IV_FAIL);
2787 }
2788
2789 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2790 {
2791 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2792 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2793 return(IV_FAIL);
2794 }
2795
2796 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2797 /* check memrecords sizes are correct */
2798 for(i=0;i < NUM_MEM_RECORDS ; i++)
2799 {
2800 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2801 {
2802 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2803 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2804 return IV_FAIL;
2805 }
2806 }
2807 }
2808 break;
2809
2810 case IVD_CMD_VIDEO_CTL:
2811 {
2812 UWORD32 *pu4_ptr_cmd;
2813 UWORD32 u4_sub_command;
2814
2815 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2816 pu4_ptr_cmd += 2;
2817 u4_sub_command = *pu4_ptr_cmd;
2818
2819 switch(u4_sub_command)
2820 {
2821 case IVD_CMD_CTL_SETPARAMS:
2822 {
2823 impeg2d_ctl_set_config_ip_t *ps_ip;
2824 impeg2d_ctl_set_config_op_t *ps_op;
2825 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2826 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2827
2828 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2829
2830 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2831 {
2832 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2833 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2834 return IV_FAIL;
2835 }
2836 }
2837 case IVD_CMD_CTL_SETDEFAULT:
2838 {
2839 impeg2d_ctl_set_config_op_t *ps_op;
2840 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2841 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2842
2843 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2844 {
2845 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2846 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2847 return IV_FAIL;
2848 }
2849 }
2850 break;
2851
2852 case IVD_CMD_CTL_GETPARAMS:
2853 {
2854 impeg2d_ctl_getstatus_ip_t *ps_ip;
2855 impeg2d_ctl_getstatus_op_t *ps_op;
2856
2857 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
2858 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
2859
2860 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
2861
2862 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
2863 {
2864 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2865 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2866 return IV_FAIL;
2867 }
2868 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
2869 {
2870 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2871 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2872 return IV_FAIL;
2873 }
2874 }
2875 break;
2876
2877 case IVD_CMD_CTL_GETBUFINFO:
2878 {
2879 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
2880 impeg2d_ctl_getbufinfo_op_t *ps_op;
2881 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
2882 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
2883
2884 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
2885
2886 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
2887 {
2888 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2889 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2890 return IV_FAIL;
2891 }
2892 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
2893 {
2894 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2895 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2896 return IV_FAIL;
2897 }
2898 }
2899 break;
2900
2901 case IVD_CMD_CTL_GETVERSION:
2902 {
2903 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
2904 impeg2d_ctl_getversioninfo_op_t *ps_op;
2905 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
2906 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
2907
2908 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
2909
2910 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
2911 {
2912 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2913 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2914 return IV_FAIL;
2915 }
2916 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
2917 {
2918 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2919 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2920 return IV_FAIL;
2921 }
2922 }
2923 break;
2924
2925 case IVD_CMD_CTL_FLUSH:
2926 {
2927 impeg2d_ctl_flush_ip_t *ps_ip;
2928 impeg2d_ctl_flush_op_t *ps_op;
2929 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
2930 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
2931
2932 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
2933
2934 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
2935 {
2936 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2937 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2938 return IV_FAIL;
2939 }
2940 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
2941 {
2942 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2943 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2944 return IV_FAIL;
2945 }
2946 }
2947 break;
2948
2949 case IVD_CMD_CTL_RESET:
2950 {
2951 impeg2d_ctl_reset_ip_t *ps_ip;
2952 impeg2d_ctl_reset_op_t *ps_op;
2953 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
2954 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
2955
2956 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
2957
2958 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
2959 {
2960 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2961 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2962 return IV_FAIL;
2963 }
2964 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
2965 {
2966 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2967 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2968 return IV_FAIL;
2969 }
2970 }
2971 break;
2972
2973 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2974 {
2975 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
2976 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
2977
2978 ps_ip =
2979 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
2980 ps_op =
2981 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
2982
2983 if(ps_ip->u4_size
2984 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
2985 {
2986 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2987 ps_op->u4_error_code |=
2988 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2989 return IV_FAIL;
2990 }
2991
2992 if(ps_op->u4_size
2993 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
2994 {
2995 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2996 ps_op->u4_error_code |=
2997 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2998 return IV_FAIL;
2999 }
3000
3001 break;
3002 }
3003 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
3004 {
3005 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
3006 impeg2d_ctl_get_seq_info_op_t *ps_op;
3007
3008 ps_ip =
3009 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
3010 ps_op =
3011 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
3012
3013 if(ps_ip->u4_size
3014 != sizeof(impeg2d_ctl_get_seq_info_ip_t))
3015 {
3016 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3017 ps_op->u4_error_code |=
3018 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3019 return IV_FAIL;
3020 }
3021
3022 if(ps_op->u4_size
3023 != sizeof(impeg2d_ctl_get_seq_info_op_t))
3024 {
3025 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3026 ps_op->u4_error_code |=
3027 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3028 return IV_FAIL;
3029 }
3030
3031 break;
3032 }
3033 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
3034 {
3035 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
3036 impeg2d_ctl_set_num_cores_op_t *ps_op;
3037
3038 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
3039 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
3040
3041 if(ps_ip->u4_size
3042 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
3043 {
3044 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3045 ps_op->u4_error_code |=
3046 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3047 return IV_FAIL;
3048 }
3049
3050 if(ps_op->u4_size
3051 != sizeof(impeg2d_ctl_set_num_cores_op_t))
3052 {
3053 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3054 ps_op->u4_error_code |=
3055 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3056 return IV_FAIL;
3057 }
3058
3059 #ifdef MULTICORE
3060 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
3061 #else
3062 if(ps_ip->u4_num_cores != 1)
3063 #endif
3064 {
3065 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3066 return IV_FAIL;
3067 }
3068 break;
3069 }
3070 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
3071 {
3072 impeg2d_ctl_set_processor_ip_t *ps_ip;
3073 impeg2d_ctl_set_processor_op_t *ps_op;
3074
3075 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
3076 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
3077
3078 if(ps_ip->u4_size
3079 != sizeof(impeg2d_ctl_set_processor_ip_t))
3080 {
3081 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3082 ps_op->u4_error_code |=
3083 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3084 return IV_FAIL;
3085 }
3086
3087 if(ps_op->u4_size
3088 != sizeof(impeg2d_ctl_set_processor_op_t))
3089 {
3090 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3091 ps_op->u4_error_code |=
3092 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3093 return IV_FAIL;
3094 }
3095
3096 break;
3097 }
3098 default:
3099 break;
3100
3101 }
3102 }
3103 break;
3104
3105 default:
3106 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
3107 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
3108 return IV_FAIL;
3109 }
3110
3111
3112 }
3113
3114 return IV_SUCCESS;
3115 }
3116
3117 /*****************************************************************************/
3118 /* */
3119 /* Function Name : impeg2d_api_entity */
3120 /* */
3121 /* Description : */
3122 /* */
3123 /* Inputs : */
3124 /* Globals : <Does it use any global variables?> */
3125 /* Outputs : */
3126 /* Returns : void */
3127 /* */
3128 /* Issues : none */
3129 /* */
3130 /* Revision History: */
3131 /* */
3132 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3133 /* 22 10 2008 100356 Draft */
3134 /* */
3135 /*****************************************************************************/
3136
3137
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)3138 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
3139 void *pv_api_ip,
3140 void *pv_api_op)
3141 {
3142 iv_obj_t *ps_dec_handle;
3143 dec_state_t *ps_dec_state;
3144 dec_state_multi_core_t *ps_dec_state_multi_core;
3145
3146 impeg2d_video_decode_ip_t *ps_dec_ip;
3147
3148 impeg2d_video_decode_op_t *ps_dec_op;
3149 WORD32 bytes_remaining;
3150 pic_buf_t *ps_disp_pic;
3151
3152
3153
3154 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
3155 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
3156
3157 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
3158
3159 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3160 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3161 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3162
3163 ps_dec_handle = (iv_obj_t *)ps_dechdl;
3164
3165 if(ps_dechdl == NULL)
3166 {
3167 return(IV_FAIL);
3168 }
3169
3170
3171
3172 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
3173 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
3174
3175 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3176 if(0 == ps_dec_state->u4_share_disp_buf)
3177 {
3178 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3179 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3180 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3181 }
3182
3183 ps_dec_state->ps_disp_pic = NULL;
3184 ps_dec_state->i4_frame_decoded = 0;
3185 /*rest bytes consumed */
3186 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
3187
3188 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
3189
3190 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
3191 {
3192 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3193 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
3194 return IV_FAIL;
3195 }
3196
3197
3198 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
3199 {
3200 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
3201 return(IV_FAIL);
3202 }
3203
3204 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
3205 {
3206 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
3207 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
3208 }
3209
3210 if((1 != ps_dec_state->u2_decode_header) &&
3211 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm))
3212 {
3213 if(ps_dec_state->u1_flushfrm)
3214 {
3215 if(ps_dec_state->aps_ref_pics[1] != NULL)
3216 {
3217 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
3218 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
3219 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3220
3221 ps_dec_state->aps_ref_pics[1] = NULL;
3222 ps_dec_state->aps_ref_pics[0] = NULL;
3223
3224 }
3225 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3226 {
3227 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3228 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3229
3230 ps_dec_state->aps_ref_pics[0] = NULL;
3231 }
3232 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3233 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3234
3235 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3236
3237 ps_dec_state->ps_disp_pic = ps_disp_pic;
3238 if(ps_disp_pic == NULL)
3239 {
3240 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3241 }
3242 else
3243 {
3244 WORD32 fmt_conv;
3245 if(0 == ps_dec_state->u4_share_disp_buf)
3246 {
3247 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3248 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3249 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3250 fmt_conv = 1;
3251 }
3252 else
3253 {
3254 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3255 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3256 {
3257 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3258 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3259 fmt_conv = 0;
3260 }
3261 else
3262 {
3263 UWORD8 *pu1_buf;
3264
3265 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3266 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3267
3268 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3269 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3270 fmt_conv = 1;
3271 }
3272 }
3273
3274 if(fmt_conv == 1)
3275 {
3276 iv_yuv_buf_t *ps_dst;
3277
3278
3279 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3280 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame))
3281 {
3282 impeg2d_deinterlace(ps_dec_state,
3283 ps_disp_pic,
3284 ps_dst,
3285 0,
3286 ps_dec_state->u2_vertical_size);
3287
3288 }
3289 else
3290 {
3291 impeg2d_format_convert(ps_dec_state,
3292 ps_disp_pic,
3293 ps_dst,
3294 0,
3295 ps_dec_state->u2_vertical_size);
3296 }
3297 }
3298
3299 if(ps_dec_state->u4_deinterlace)
3300 {
3301 if(ps_dec_state->ps_deint_pic)
3302 {
3303 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3304 ps_dec_state->ps_deint_pic->i4_buf_id,
3305 MPEG2_BUF_MGR_DEINT);
3306 }
3307 ps_dec_state->ps_deint_pic = ps_disp_pic;
3308 }
3309 if(0 == ps_dec_state->u4_share_disp_buf)
3310 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3311
3312 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3313 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3314 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3315
3316 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3317 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3318
3319 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3320
3321 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3322
3323 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3324
3325 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3326 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3327 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3328
3329 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3330 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3331 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3332
3333 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3334 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3335 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3336 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3337
3338 switch(ps_dec_state->i4_chromaFormat)
3339 {
3340 case IV_YUV_420SP_UV:
3341 case IV_YUV_420SP_VU:
3342 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (((ps_dec_state->u2_horizontal_size + 1) >> 1) << 1);
3343 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3344 break;
3345 case IV_YUV_422ILE:
3346 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3347 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3348 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3349 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3350 break;
3351 default:
3352 break;
3353 }
3354
3355
3356 }
3357 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3358 {
3359 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3360 {
3361 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3362 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3363 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3364 ps_dec_state->u4_frm_buf_stride,
3365 ps_dec_state->u2_horizontal_size,
3366 ps_dec_state->u2_vertical_size,
3367 ps_dec_state->i4_chromaFormat,
3368 ps_dec_state->u2_horizontal_size,
3369 ps_dec_state->u2_vertical_size);
3370 }
3371 return(IV_SUCCESS);
3372 }
3373 else
3374 {
3375 ps_dec_state->u1_flushfrm = 0;
3376
3377 return(IV_FAIL);
3378 }
3379
3380 }
3381 else if(ps_dec_state->u1_flushfrm==0)
3382 {
3383 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3384 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3385 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3386 {
3387 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3388 return(IV_FAIL);
3389 }
3390
3391 if(1 == ps_dec_state->u4_share_disp_buf)
3392 {
3393 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3394 {
3395 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3396 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3397 return IV_FAIL;
3398 }
3399 }
3400
3401
3402 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3403
3404 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3405
3406 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3407
3408 if (0 == ps_dec_state->u4_frm_buf_stride)
3409 {
3410 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size);
3411 }
3412
3413 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3414 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3415 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3416
3417 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3418 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3419 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3420
3421 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3422 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3423 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3424 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3425
3426 switch(ps_dec_state->i4_chromaFormat)
3427 {
3428 case IV_YUV_420SP_UV:
3429 case IV_YUV_420SP_VU:
3430 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (((ps_dec_state->u2_horizontal_size + 1) >> 1) << 1);
3431 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3432 break;
3433 case IV_YUV_422ILE:
3434 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3435 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3436 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3437 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3438 break;
3439 default:
3440 break;
3441 }
3442
3443 if( ps_dec_state->u1_flushfrm == 0)
3444 {
3445 ps_dec_state->u1_flushcnt = 0;
3446
3447 ps_dec_state->ps_out_buf = &ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer;
3448 if (IV_SUCCESS != check_app_out_buf_size(ps_dec_state))
3449 {
3450 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
3451 return IV_FAIL;
3452 }
3453
3454 /*************************************************************************/
3455 /* Frame Decode */
3456 /*************************************************************************/
3457 ps_dec_state->u4_inp_ts = ps_dec_ip->s_ivd_video_decode_ip_t.u4_ts;
3458
3459 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3460
3461 if (IVD_ERROR_NONE ==
3462 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3463 {
3464 if(ps_dec_state->u1_first_frame_done == 0)
3465 {
3466 ps_dec_state->u1_first_frame_done = 1;
3467 }
3468
3469 if(ps_dec_state->ps_disp_pic)
3470 {
3471 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3472 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3473 {
3474 case I_PIC :
3475 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3476 break;
3477
3478 case P_PIC:
3479 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3480 break;
3481
3482 case B_PIC:
3483 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3484 break;
3485
3486 case D_PIC:
3487 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3488 break;
3489
3490 default :
3491 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3492 break;
3493 }
3494 }
3495 else
3496 {
3497 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3498 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3499 }
3500
3501 ps_dec_state->u4_num_frames_decoded++;
3502 }
3503 }
3504 else
3505 {
3506 ps_dec_state->u1_flushcnt++;
3507 }
3508 }
3509 if(ps_dec_state->ps_disp_pic)
3510 {
3511 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3512 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3513
3514 if(0 == ps_dec_state->u4_share_disp_buf)
3515 {
3516 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3517 }
3518 }
3519
3520 if(ps_dec_state->u4_deinterlace)
3521 {
3522 if(ps_dec_state->ps_deint_pic)
3523 {
3524 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3525 ps_dec_state->ps_deint_pic->i4_buf_id,
3526 MPEG2_BUF_MGR_DEINT);
3527 }
3528 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic;
3529 }
3530
3531 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3532 {
3533 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3534 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3535 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3536 ps_dec_state->u4_frm_buf_stride,
3537 ps_dec_state->u2_horizontal_size,
3538 ps_dec_state->u2_vertical_size,
3539 ps_dec_state->i4_chromaFormat,
3540 ps_dec_state->u2_horizontal_size,
3541 ps_dec_state->u2_vertical_size);
3542 }
3543
3544 }
3545
3546 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3547 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3548
3549
3550 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3551 return IV_FAIL;
3552 else
3553 return IV_SUCCESS;
3554 }
3555