1 /**************************************************************************
2 *
3 * Copyright 2020 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <stdio.h>
29
30 #include "pipe/p_video_codec.h"
31
32 #include "util/u_video.h"
33
34 #include "si_pipe.h"
35 #include "radeon_video.h"
36 #include "radeon_vcn_enc.h"
37
38 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
39 #define RENCODE_FW_INTERFACE_MINOR_VERSION 0
40
radeon_enc_spec_misc(struct radeon_encoder * enc)41 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
42 {
43 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
44 enc->enc_pic.spec_misc.cabac_enable = 0;
45 enc->enc_pic.spec_misc.cabac_init_idc = 0;
46 enc->enc_pic.spec_misc.half_pel_enabled = 1;
47 enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
48 enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
49 enc->enc_pic.spec_misc.level_idc = enc->base.level;
50 enc->enc_pic.spec_misc.b_picture_enabled = 0;
51 enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
52
53 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
54 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
55 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
56 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
57 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
58 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
59 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
60 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
61 RADEON_ENC_CS(enc->enc_pic.spec_misc.b_picture_enabled);
62 RADEON_ENC_CS(enc->enc_pic.spec_misc.weighted_bipred_idc);
63 RADEON_ENC_END();
64 }
65
radeon_enc_quality_params(struct radeon_encoder * enc)66 static void radeon_enc_quality_params(struct radeon_encoder *enc)
67 {
68 enc->enc_pic.quality_params.vbaq_mode = 0;
69 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
70 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
71 enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
72
73 RADEON_ENC_BEGIN(enc->cmd.quality_params);
74 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
75 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
76 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
77 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
78 RADEON_ENC_CS(0);
79 RADEON_ENC_END();
80 }
81
radeon_enc_encode_params_h264(struct radeon_encoder * enc)82 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
83 {
84 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
85 enc->enc_pic.h264_enc_params.input_pic_order_cnt = 0;
86 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
87 enc->enc_pic.h264_enc_params.l0_reference_picture1_index = 0xFFFFFFFF;
88 enc->enc_pic.h264_enc_params.l1_reference_picture0_index= 0xFFFFFFFF;
89
90 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
91 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
92 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_pic_order_cnt);
93 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
94 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_type);
95 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.is_long_term);
96 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.picture_structure);
97 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_order_cnt);
98 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l0_reference_picture1_index);
99 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_type);
100 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.is_long_term);
101 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.picture_structure);
102 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_order_cnt);
103 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l1_reference_picture0_index);
104 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_type);
105 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.is_long_term);
106 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.picture_structure);
107 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_order_cnt);
108 RADEON_ENC_END();
109 }
110
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)111 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
112 {
113 uint32_t *size_in_bytes;
114
115 RADEON_ENC_BEGIN(enc->cmd.nalu);
116 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
117 size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
118
119 radeon_enc_reset(enc);
120 radeon_enc_set_emulation_prevention(enc, false);
121 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
122 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
123 radeon_enc_byte_align(enc);
124 radeon_enc_set_emulation_prevention(enc, true);
125 radeon_enc_code_ue(enc, 0x0);
126 radeon_enc_code_ue(enc, 0x0);
127 radeon_enc_code_fixed_bits(enc, 0x1, 1);
128 radeon_enc_code_fixed_bits(enc, 0x0, 4);
129 radeon_enc_code_fixed_bits(enc, 0x0, 1);
130 radeon_enc_code_fixed_bits(enc, 0x1, 1);
131 radeon_enc_code_ue(enc, 0x0);
132 radeon_enc_code_ue(enc, 0x0);
133 radeon_enc_code_se(enc, 0x0);
134 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
135 radeon_enc_code_fixed_bits(enc, 0x1, 1);
136 if (enc->enc_pic.rc_session_init.rate_control_method ==
137 RENCODE_RATE_CONTROL_METHOD_NONE)
138 radeon_enc_code_fixed_bits(enc, 0x0, 1);
139 else {
140 radeon_enc_code_fixed_bits(enc, 0x1, 1);
141 radeon_enc_code_ue(enc, 0x0);
142 }
143 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
144 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
145 radeon_enc_code_fixed_bits(enc, 0x0, 1);
146 radeon_enc_code_fixed_bits(enc, 0x0, 2);
147 radeon_enc_code_fixed_bits(enc, 0x0, 1);
148 radeon_enc_code_fixed_bits(enc, 0x0, 1);
149 radeon_enc_code_fixed_bits(enc, 0x0, 1);
150 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
151 radeon_enc_code_fixed_bits(enc, 0x1, 1);
152 radeon_enc_code_fixed_bits(enc, 0x0, 1);
153 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
154
155 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
156 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
157 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
158 }
159
160 radeon_enc_code_fixed_bits(enc, 0x0, 1);
161 radeon_enc_code_fixed_bits(enc, 0x0, 1);
162 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
163 radeon_enc_code_fixed_bits(enc, 0x0, 2);
164
165 radeon_enc_code_fixed_bits(enc, 0x1, 1);
166
167 radeon_enc_byte_align(enc);
168 radeon_enc_flush_headers(enc);
169 *size_in_bytes = (enc->bits_output + 7) / 8;
170 RADEON_ENC_END();
171 }
172
radeon_enc_3_0_init(struct radeon_encoder * enc)173 void radeon_enc_3_0_init(struct radeon_encoder *enc)
174 {
175 radeon_enc_2_0_init(enc);
176
177 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
178 enc->spec_misc = radeon_enc_spec_misc;
179 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
180 enc->quality_params = radeon_enc_quality_params;
181 }
182
183 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)
184 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
185
186 enc->enc_pic.session_info.interface_version =
187 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
188 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
189 }
190