1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> %a) { 5; CHECK-LABEL: test_vclsq_s8: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vcls.s8 q0, q0 8; CHECK-NEXT: bx lr 9entry: 10 %0 = tail call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %a) 11 ret <16 x i8> %0 12} 13 14define arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> %a) { 15; CHECK-LABEL: test_vclsq_s16: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: vcls.s16 q0, q0 18; CHECK-NEXT: bx lr 19entry: 20 %0 = tail call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %a) 21 ret <8 x i16> %0 22} 23 24define arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> %a) { 25; CHECK-LABEL: test_vclsq_s32: 26; CHECK: @ %bb.0: @ %entry 27; CHECK-NEXT: vcls.s32 q0, q0 28; CHECK-NEXT: bx lr 29entry: 30 %0 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %a) 31 ret <4 x i32> %0 32} 33 34declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) 35declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) 36declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) 37