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1; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s
2
3define arm_aapcs_vfpcc <16 x i8> @vqabs_test16(<16 x i8> %A) nounwind {
4; CHECK-LABEL: vqabs_test16:
5; CHECK:       @ %bb.0: @ %entry
6; CHECK-NEXT:    vqabs.s8 q0, q0
7; CHECK-NEXT:    bx lr
8entry:
9
10  %0 = icmp sgt <16 x i8> %A, zeroinitializer
11  %1 = icmp eq <16 x i8> %A, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
12  %2 = sub nsw <16 x i8> zeroinitializer, %A
13  %3 = select <16 x i1> %1, <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>, <16 x i8> %2
14  %4 = select <16 x i1> %0, <16 x i8> %A, <16 x i8> %3
15
16  ret <16 x i8> %4
17}
18
19define arm_aapcs_vfpcc <8 x i16> @vqabs_test8(<8 x i16> %A) nounwind {
20; CHECK-LABEL: vqabs_test8:
21; CHECK:       @ %bb.0: @ %entry
22; CHECK-NEXT:    vqabs.s16 q0, q0
23; CHECK-NEXT:    bx lr
24entry:
25
26  %0 = icmp sgt <8 x i16> %A, zeroinitializer
27  %1 = icmp eq <8 x i16> %A, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
28  %2 = sub nsw <8 x i16> zeroinitializer, %A
29  %3 = select <8 x i1> %1, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>, <8 x i16> %2
30  %4 = select <8 x i1> %0, <8 x i16> %A, <8 x i16> %3
31
32  ret <8 x i16> %4
33}
34
35define arm_aapcs_vfpcc <4 x i32> @vqabs_test4(<4 x i32> %A) nounwind {
36; CHECK-LABEL: vqabs_test4:
37; CHECK:       @ %bb.0: @ %entry
38; CHECK-NEXT:    vqabs.s32 q0, q0
39; CHECK-NEXT:    bx lr
40entry:
41
42  %0 = icmp sgt <4 x i32> %A, zeroinitializer
43  %1 = icmp eq <4 x i32> %A, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
44  %2 = sub nsw <4 x i32> zeroinitializer, %A
45  %3 = select <4 x i1> %1, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %2
46  %4 = select <4 x i1> %0, <4 x i32> %A, <4 x i32> %3
47
48  ret <4 x i32> %4
49}
50
51