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1<?xml version="1.0" encoding="UTF-8"?>
2<database xmlns="http://nouveau.freedesktop.org/"
3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5<import file="freedreno_copyright.xml"/>
6<import file="adreno/adreno_common.xml"/>
7<import file="adreno/adreno_pm4.xml"/>
8
9<enum name="a5xx_color_fmt">
10	<value value="0x02" name="RB5_A8_UNORM"/>
11	<value value="0x03" name="RB5_R8_UNORM"/>
12	<value value="0x04" name="RB5_R8_SNORM"/>
13	<value value="0x05" name="RB5_R8_UINT"/>
14	<value value="0x06" name="RB5_R8_SINT"/>
15	<value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16	<value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17	<value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18	<value value="0x0f" name="RB5_R8G8_UNORM"/>
19	<value value="0x10" name="RB5_R8G8_SNORM"/>
20	<value value="0x11" name="RB5_R8G8_UINT"/>
21	<value value="0x12" name="RB5_R8G8_SINT"/>
22	<value value="0x15" name="RB5_R16_UNORM"/>
23	<value value="0x16" name="RB5_R16_SNORM"/>
24	<value value="0x17" name="RB5_R16_FLOAT"/>
25	<value value="0x18" name="RB5_R16_UINT"/>
26	<value value="0x19" name="RB5_R16_SINT"/>
27	<value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
28	<value value="0x31" name="RB5_R8G8B8_UNORM"/>
29	<value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
30	<value value="0x33" name="RB5_R8G8B8A8_UINT"/>
31	<value value="0x34" name="RB5_R8G8B8A8_SINT"/>
32	<value value="0x37" name="RB5_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
33	<value value="0x3a" name="RB5_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
34	<value value="0x42" name="RB5_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
35	<value value="0x43" name="RB5_R16G16_UNORM"/>
36	<value value="0x44" name="RB5_R16G16_SNORM"/>
37	<value value="0x45" name="RB5_R16G16_FLOAT"/>
38	<value value="0x46" name="RB5_R16G16_UINT"/>
39	<value value="0x47" name="RB5_R16G16_SINT"/>
40	<value value="0x4a" name="RB5_R32_FLOAT"/>
41	<value value="0x4b" name="RB5_R32_UINT"/>
42	<value value="0x4c" name="RB5_R32_SINT"/>
43	<value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
44	<value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
45	<value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
46	<value value="0x63" name="RB5_R16G16B16A16_UINT"/>
47	<value value="0x64" name="RB5_R16G16B16A16_SINT"/>
48	<value value="0x67" name="RB5_R32G32_FLOAT"/>
49	<value value="0x68" name="RB5_R32G32_UINT"/>
50	<value value="0x69" name="RB5_R32G32_SINT"/>
51	<value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
52	<value value="0x83" name="RB5_R32G32B32A32_UINT"/>
53	<value value="0x84" name="RB5_R32G32B32A32_SINT"/>
54
55	<value value="0xff" name="RB5_NONE"/>
56</enum>
57
58<enum name="a5xx_tile_mode">
59	<value name="TILE5_LINEAR" value="0"/>
60	<value name="TILE5_2" value="2"/>
61	<value name="TILE5_3" value="3"/>
62</enum>
63
64<enum name="a5xx_vtx_fmt" prefix="chipset">
65	<value value="0x03" name="VFMT5_8_UNORM"/>
66	<value value="0x04" name="VFMT5_8_SNORM"/>
67	<value value="0x05" name="VFMT5_8_UINT"/>
68	<value value="0x06" name="VFMT5_8_SINT"/>
69
70	<value value="0x0f" name="VFMT5_8_8_UNORM"/>
71	<value value="0x10" name="VFMT5_8_8_SNORM"/>
72	<value value="0x11" name="VFMT5_8_8_UINT"/>
73	<value value="0x12" name="VFMT5_8_8_SINT"/>
74
75	<value value="0x15" name="VFMT5_16_UNORM"/>
76	<value value="0x16" name="VFMT5_16_SNORM"/>
77	<value value="0x17" name="VFMT5_16_FLOAT"/>
78	<value value="0x18" name="VFMT5_16_UINT"/>
79	<value value="0x19" name="VFMT5_16_SINT"/>
80
81	<value value="0x21" name="VFMT5_8_8_8_UNORM"/>
82	<value value="0x22" name="VFMT5_8_8_8_SNORM"/>
83	<value value="0x23" name="VFMT5_8_8_8_UINT"/>
84	<value value="0x24" name="VFMT5_8_8_8_SINT"/>
85
86	<value value="0x30" name="VFMT5_8_8_8_8_UNORM"/>
87	<value value="0x32" name="VFMT5_8_8_8_8_SNORM"/>
88	<value value="0x33" name="VFMT5_8_8_8_8_UINT"/>
89	<value value="0x34" name="VFMT5_8_8_8_8_SINT"/>
90
91	<value value="0x36" name="VFMT5_10_10_10_2_UNORM"/>
92	<value value="0x39" name="VFMT5_10_10_10_2_SNORM"/>
93	<value value="0x3a" name="VFMT5_10_10_10_2_UINT"/>
94	<value value="0x3b" name="VFMT5_10_10_10_2_SINT"/>
95
96	<value value="0x42" name="VFMT5_11_11_10_FLOAT"/>
97
98	<value value="0x43" name="VFMT5_16_16_UNORM"/>
99	<value value="0x44" name="VFMT5_16_16_SNORM"/>
100	<value value="0x45" name="VFMT5_16_16_FLOAT"/>
101	<value value="0x46" name="VFMT5_16_16_UINT"/>
102	<value value="0x47" name="VFMT5_16_16_SINT"/>
103
104	<value value="0x48" name="VFMT5_32_UNORM"/>
105	<value value="0x49" name="VFMT5_32_SNORM"/>
106	<value value="0x4a" name="VFMT5_32_FLOAT"/>
107	<value value="0x4b" name="VFMT5_32_UINT"/>
108	<value value="0x4c" name="VFMT5_32_SINT"/>
109	<value value="0x4d" name="VFMT5_32_FIXED"/>
110
111	<value value="0x58" name="VFMT5_16_16_16_UNORM"/>
112	<value value="0x59" name="VFMT5_16_16_16_SNORM"/>
113	<value value="0x5a" name="VFMT5_16_16_16_FLOAT"/>
114	<value value="0x5b" name="VFMT5_16_16_16_UINT"/>
115	<value value="0x5c" name="VFMT5_16_16_16_SINT"/>
116
117	<value value="0x60" name="VFMT5_16_16_16_16_UNORM"/>
118	<value value="0x61" name="VFMT5_16_16_16_16_SNORM"/>
119	<value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/>
120	<value value="0x63" name="VFMT5_16_16_16_16_UINT"/>
121	<value value="0x64" name="VFMT5_16_16_16_16_SINT"/>
122
123	<value value="0x65" name="VFMT5_32_32_UNORM"/>
124	<value value="0x66" name="VFMT5_32_32_SNORM"/>
125	<value value="0x67" name="VFMT5_32_32_FLOAT"/>
126	<value value="0x68" name="VFMT5_32_32_UINT"/>
127	<value value="0x69" name="VFMT5_32_32_SINT"/>
128	<value value="0x6a" name="VFMT5_32_32_FIXED"/>
129
130	<value value="0x70" name="VFMT5_32_32_32_UNORM"/>
131	<value value="0x71" name="VFMT5_32_32_32_SNORM"/>
132	<value value="0x72" name="VFMT5_32_32_32_UINT"/>
133	<value value="0x73" name="VFMT5_32_32_32_SINT"/>
134	<value value="0x74" name="VFMT5_32_32_32_FLOAT"/>
135	<value value="0x75" name="VFMT5_32_32_32_FIXED"/>
136
137	<value value="0x80" name="VFMT5_32_32_32_32_UNORM"/>
138	<value value="0x81" name="VFMT5_32_32_32_32_SNORM"/>
139	<value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/>
140	<value value="0x83" name="VFMT5_32_32_32_32_UINT"/>
141	<value value="0x84" name="VFMT5_32_32_32_32_SINT"/>
142	<value value="0x85" name="VFMT5_32_32_32_32_FIXED"/>
143
144	<value value="0xff" name="VFMT5_NONE"/>
145</enum>
146
147<enum name="a5xx_tex_fmt">
148	<value value="0x02" name="TFMT5_A8_UNORM"/>
149	<value value="0x03" name="TFMT5_8_UNORM"/>
150	<value value="0x04" name="TFMT5_8_SNORM"/>
151	<value value="0x05" name="TFMT5_8_UINT"/>
152	<value value="0x06" name="TFMT5_8_SINT"/>
153	<value value="0x08" name="TFMT5_4_4_4_4_UNORM"/>
154	<value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/>
155	<value value="0x0e" name="TFMT5_5_6_5_UNORM"/>
156	<value value="0x0f" name="TFMT5_8_8_UNORM"/>
157	<value value="0x10" name="TFMT5_8_8_SNORM"/>
158	<value value="0x11" name="TFMT5_8_8_UINT"/>
159	<value value="0x12" name="TFMT5_8_8_SINT"/>
160	<value value="0x13" name="TFMT5_L8_A8_UNORM"/>
161	<value value="0x15" name="TFMT5_16_UNORM"/>
162	<value value="0x16" name="TFMT5_16_SNORM"/>
163	<value value="0x17" name="TFMT5_16_FLOAT"/>
164	<value value="0x18" name="TFMT5_16_UINT"/>
165	<value value="0x19" name="TFMT5_16_SINT"/>
166	<value value="0x30" name="TFMT5_8_8_8_8_UNORM"/>
167	<value value="0x31" name="TFMT5_8_8_8_UNORM"/>
168	<value value="0x32" name="TFMT5_8_8_8_8_SNORM"/>
169	<value value="0x33" name="TFMT5_8_8_8_8_UINT"/>
170	<value value="0x34" name="TFMT5_8_8_8_8_SINT"/>
171	<value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/>
172	<value value="0x36" name="TFMT5_10_10_10_2_UNORM"/>
173	<value value="0x3a" name="TFMT5_10_10_10_2_UINT"/>
174	<value value="0x42" name="TFMT5_11_11_10_FLOAT"/>
175	<value value="0x43" name="TFMT5_16_16_UNORM"/>
176	<value value="0x44" name="TFMT5_16_16_SNORM"/>
177	<value value="0x45" name="TFMT5_16_16_FLOAT"/>
178	<value value="0x46" name="TFMT5_16_16_UINT"/>
179	<value value="0x47" name="TFMT5_16_16_SINT"/>
180	<value value="0x4a" name="TFMT5_32_FLOAT"/>
181	<value value="0x4b" name="TFMT5_32_UINT"/>
182	<value value="0x4c" name="TFMT5_32_SINT"/>
183	<value value="0x60" name="TFMT5_16_16_16_16_UNORM"/>
184	<value value="0x61" name="TFMT5_16_16_16_16_SNORM"/>
185	<value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/>
186	<value value="0x63" name="TFMT5_16_16_16_16_UINT"/>
187	<value value="0x64" name="TFMT5_16_16_16_16_SINT"/>
188	<value value="0x67" name="TFMT5_32_32_FLOAT"/>
189	<value value="0x68" name="TFMT5_32_32_UINT"/>
190	<value value="0x69" name="TFMT5_32_32_SINT"/>
191	<value value="0x72" name="TFMT5_32_32_32_UINT"/>
192	<value value="0x73" name="TFMT5_32_32_32_SINT"/>
193	<value value="0x74" name="TFMT5_32_32_32_FLOAT"/>
194	<value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/>
195	<value value="0x83" name="TFMT5_32_32_32_32_UINT"/>
196	<value value="0x84" name="TFMT5_32_32_32_32_SINT"/>
197	<value value="0xa0" name="TFMT5_X8Z24_UNORM"/>
198
199	<value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/>
200	<value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/>
201	<value value="0xad" name="TFMT5_ETC2_R11_UNORM"/>
202	<value value="0xae" name="TFMT5_ETC2_R11_SNORM"/>
203	<value value="0xaf" name="TFMT5_ETC1"/>
204	<value value="0xb0" name="TFMT5_ETC2_RGB8"/>
205	<value value="0xb1" name="TFMT5_ETC2_RGBA8"/>
206	<value value="0xb2" name="TFMT5_ETC2_RGB8A1"/>
207	<value value="0xb3" name="TFMT5_DXT1"/>
208	<value value="0xb4" name="TFMT5_DXT3"/>
209	<value value="0xb5" name="TFMT5_DXT5"/>
210	<value value="0xb7" name="TFMT5_RGTC1_UNORM"/>
211	<value value="0xb8" name="TFMT5_RGTC1_SNORM"/>
212	<value value="0xbb" name="TFMT5_RGTC2_UNORM"/>
213	<value value="0xbc" name="TFMT5_RGTC2_SNORM"/>
214	<value value="0xbe" name="TFMT5_BPTC_UFLOAT"/>
215	<value value="0xbf" name="TFMT5_BPTC_FLOAT"/>
216	<value value="0xc0" name="TFMT5_BPTC"/>
217	<value value="0xc1" name="TFMT5_ASTC_4x4"/>
218	<value value="0xc2" name="TFMT5_ASTC_5x4"/>
219	<value value="0xc3" name="TFMT5_ASTC_5x5"/>
220	<value value="0xc4" name="TFMT5_ASTC_6x5"/>
221	<value value="0xc5" name="TFMT5_ASTC_6x6"/>
222	<value value="0xc6" name="TFMT5_ASTC_8x5"/>
223	<value value="0xc7" name="TFMT5_ASTC_8x6"/>
224	<value value="0xc8" name="TFMT5_ASTC_8x8"/>
225	<value value="0xc9" name="TFMT5_ASTC_10x5"/>
226	<value value="0xca" name="TFMT5_ASTC_10x6"/>
227	<value value="0xcb" name="TFMT5_ASTC_10x8"/>
228	<value value="0xcc" name="TFMT5_ASTC_10x10"/>
229	<value value="0xcd" name="TFMT5_ASTC_12x10"/>
230	<value value="0xce" name="TFMT5_ASTC_12x12"/>
231
232	<value value="0xff" name="TFMT5_NONE"/>
233</enum>
234
235<enum name="a5xx_depth_format">
236	<value name="DEPTH5_NONE" value="0"/>
237	<value name="DEPTH5_16" value="1"/>
238	<value name="DEPTH5_24_8" value="2"/>
239	<value name="DEPTH5_32" value="4"/>
240</enum>
241
242<enum name="a5xx_blit_buf">
243	<value value="0" name="BLIT_MRT0"/>
244	<value value="1" name="BLIT_MRT1"/>
245	<value value="2" name="BLIT_MRT2"/>
246	<value value="3" name="BLIT_MRT3"/>
247	<value value="4" name="BLIT_MRT4"/>
248	<value value="5" name="BLIT_MRT5"/>
249	<value value="6" name="BLIT_MRT6"/>
250	<value value="7" name="BLIT_MRT7"/>
251	<value value="8" name="BLIT_ZS"/>       <!-- depth or combined depth+stencil -->
252	<value value="9" name="BLIT_S"/>        <!-- separate stencil -->
253</enum>
254
255<!-- see comment in a4xx.xml about script to extract countables from test-perf output -->
256<enum name="a5xx_cp_perfcounter_select">
257	<value value="0" name="PERF_CP_ALWAYS_COUNT"/>
258	<value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
259	<value value="2" name="PERF_CP_BUSY_CYCLES"/>
260	<value value="3" name="PERF_CP_PFP_IDLE"/>
261	<value value="4" name="PERF_CP_PFP_BUSY_WORKING"/>
262	<value value="5" name="PERF_CP_PFP_STALL_CYCLES_ANY"/>
263	<value value="6" name="PERF_CP_PFP_STARVE_CYCLES_ANY"/>
264	<value value="7" name="PERF_CP_PFP_ICACHE_MISS"/>
265	<value value="8" name="PERF_CP_PFP_ICACHE_HIT"/>
266	<value value="9" name="PERF_CP_PFP_MATCH_PM4_PKT_PROFILE"/>
267	<value value="10" name="PERF_CP_ME_BUSY_WORKING"/>
268	<value value="11" name="PERF_CP_ME_IDLE"/>
269	<value value="12" name="PERF_CP_ME_STARVE_CYCLES_ANY"/>
270	<value value="13" name="PERF_CP_ME_FIFO_EMPTY_PFP_IDLE"/>
271	<value value="14" name="PERF_CP_ME_FIFO_EMPTY_PFP_BUSY"/>
272	<value value="15" name="PERF_CP_ME_FIFO_FULL_ME_BUSY"/>
273	<value value="16" name="PERF_CP_ME_FIFO_FULL_ME_NON_WORKING"/>
274	<value value="17" name="PERF_CP_ME_STALL_CYCLES_ANY"/>
275	<value value="18" name="PERF_CP_ME_ICACHE_MISS"/>
276	<value value="19" name="PERF_CP_ME_ICACHE_HIT"/>
277	<value value="20" name="PERF_CP_NUM_PREEMPTIONS"/>
278	<value value="21" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
279	<value value="22" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
280	<value value="23" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
281	<value value="24" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
282	<value value="25" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
283	<value value="26" name="PERF_CP_MODE_SWITCH"/>
284	<value value="27" name="PERF_CP_ZPASS_DONE"/>
285	<value value="28" name="PERF_CP_CONTEXT_DONE"/>
286	<value value="29" name="PERF_CP_CACHE_FLUSH"/>
287	<value value="30" name="PERF_CP_LONG_PREEMPTIONS"/>
288</enum>
289
290<enum name="a5xx_rbbm_perfcounter_select">
291	<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
292	<value value="1" name="PERF_RBBM_ALWAYS_ON"/>
293	<value value="2" name="PERF_RBBM_TSE_BUSY"/>
294	<value value="3" name="PERF_RBBM_RAS_BUSY"/>
295	<value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
296	<value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
297	<value value="6" name="PERF_RBBM_STATUS_MASKED"/>
298	<value value="7" name="PERF_RBBM_COM_BUSY"/>
299	<value value="8" name="PERF_RBBM_DCOM_BUSY"/>
300	<value value="9" name="PERF_RBBM_VBIF_BUSY"/>
301	<value value="10" name="PERF_RBBM_VSC_BUSY"/>
302	<value value="11" name="PERF_RBBM_TESS_BUSY"/>
303	<value value="12" name="PERF_RBBM_UCHE_BUSY"/>
304	<value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
305</enum>
306
307<enum name="a5xx_pc_perfcounter_select">
308	<value value="0" name="PERF_PC_BUSY_CYCLES"/>
309	<value value="1" name="PERF_PC_WORKING_CYCLES"/>
310	<value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
311	<value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
312	<value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
313	<value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
314	<value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
315	<value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
316	<value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
317	<value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
318	<value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
319	<value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
320	<value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
321	<value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
322	<value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
323	<value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
324	<value value="16" name="PERF_PC_INSTANCES"/>
325	<value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
326	<value value="18" name="PERF_PC_DEAD_PRIM"/>
327	<value value="19" name="PERF_PC_LIVE_PRIM"/>
328	<value value="20" name="PERF_PC_VERTEX_HITS"/>
329	<value value="21" name="PERF_PC_IA_VERTICES"/>
330	<value value="22" name="PERF_PC_IA_PRIMITIVES"/>
331	<value value="23" name="PERF_PC_GS_PRIMITIVES"/>
332	<value value="24" name="PERF_PC_HS_INVOCATIONS"/>
333	<value value="25" name="PERF_PC_DS_INVOCATIONS"/>
334	<value value="26" name="PERF_PC_VS_INVOCATIONS"/>
335	<value value="27" name="PERF_PC_GS_INVOCATIONS"/>
336	<value value="28" name="PERF_PC_DS_PRIMITIVES"/>
337	<value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
338	<value value="30" name="PERF_PC_3D_DRAWCALLS"/>
339	<value value="31" name="PERF_PC_2D_DRAWCALLS"/>
340	<value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
341	<value value="33" name="PERF_TESS_BUSY_CYCLES"/>
342	<value value="34" name="PERF_TESS_WORKING_CYCLES"/>
343	<value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
344	<value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
345</enum>
346
347<enum name="a5xx_vfd_perfcounter_select">
348	<value value="0" name="PERF_VFD_BUSY_CYCLES"/>
349	<value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
350	<value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
351	<value value="3" name="PERF_VFD_STALL_CYCLES_MISS_VB"/>
352	<value value="4" name="PERF_VFD_STALL_CYCLES_MISS_Q"/>
353	<value value="5" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
354	<value value="6" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
355	<value value="7" name="PERF_VFD_STALL_CYCLES_VFDP_VB"/>
356	<value value="8" name="PERF_VFD_STALL_CYCLES_VFDP_Q"/>
357	<value value="9" name="PERF_VFD_DECODER_PACKER_STALL"/>
358	<value value="10" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
359	<value value="11" name="PERF_VFD_RBUFFER_FULL"/>
360	<value value="12" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
361	<value value="13" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
362	<value value="14" name="PERF_VFD_NUM_ATTRIBUTES"/>
363	<value value="15" name="PERF_VFD_INSTRUCTIONS"/>
364	<value value="16" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
365	<value value="17" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
366	<value value="18" name="PERF_VFD_MODE_0_FIBERS"/>
367	<value value="19" name="PERF_VFD_MODE_1_FIBERS"/>
368	<value value="20" name="PERF_VFD_MODE_2_FIBERS"/>
369	<value value="21" name="PERF_VFD_MODE_3_FIBERS"/>
370	<value value="22" name="PERF_VFD_MODE_4_FIBERS"/>
371	<value value="23" name="PERF_VFD_TOTAL_VERTICES"/>
372	<value value="24" name="PERF_VFD_NUM_ATTR_MISS"/>
373	<value value="25" name="PERF_VFD_1_BURST_REQ"/>
374	<value value="26" name="PERF_VFDP_STALL_CYCLES_VFD"/>
375	<value value="27" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
376	<value value="28" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
377	<value value="29" name="PERF_VFDP_STARVE_CYCLES_PC"/>
378	<value value="30" name="PERF_VFDP_VS_STAGE_32_WAVES"/>
379</enum>
380
381<enum name="a5xx_hlsq_perfcounter_select">
382	<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
383	<value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
384	<value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
385	<value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
386	<value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
387	<value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
388	<value value="6" name="PERF_HLSQ_FS_STAGE_32_WAVES"/>
389	<value value="7" name="PERF_HLSQ_FS_STAGE_64_WAVES"/>
390	<value value="8" name="PERF_HLSQ_QUADS"/>
391	<value value="9" name="PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE"/>
392	<value value="10" name="PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE"/>
393	<value value="11" name="PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE"/>
394	<value value="12" name="PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE"/>
395	<value value="13" name="PERF_HLSQ_CS_INVOCATIONS"/>
396	<value value="14" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
397</enum>
398
399<enum name="a5xx_vpc_perfcounter_select">
400	<value value="0" name="PERF_VPC_BUSY_CYCLES"/>
401	<value value="1" name="PERF_VPC_WORKING_CYCLES"/>
402	<value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
403	<value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
404	<value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
405	<value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
406	<value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
407	<value value="7" name="PERF_VPC_POS_EXPORT_STALL_CYCLES"/>
408	<value value="8" name="PERF_VPC_STARVE_CYCLES_SP"/>
409	<value value="9" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
410	<value value="10" name="PERF_VPC_PC_PRIMITIVES"/>
411	<value value="11" name="PERF_VPC_SP_COMPONENTS"/>
412	<value value="12" name="PERF_VPC_SP_LM_PRIMITIVES"/>
413	<value value="13" name="PERF_VPC_SP_LM_COMPONENTS"/>
414	<value value="14" name="PERF_VPC_SP_LM_DWORDS"/>
415	<value value="15" name="PERF_VPC_STREAMOUT_COMPONENTS"/>
416	<value value="16" name="PERF_VPC_GRANT_PHASES"/>
417</enum>
418
419<enum name="a5xx_tse_perfcounter_select">
420	<value value="0" name="PERF_TSE_BUSY_CYCLES"/>
421	<value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
422	<value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
423	<value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
424	<value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
425	<value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
426	<value value="6" name="PERF_TSE_INPUT_PRIM"/>
427	<value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
428	<value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
429	<value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
430	<value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
431	<value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
432	<value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
433	<value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
434	<value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
435	<value value="15" name="PERF_TSE_CINVOCATION"/>
436	<value value="16" name="PERF_TSE_CPRIMITIVES"/>
437	<value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
438	<value value="18" name="PERF_TSE_2D_ALIVE_CLCLES"/>
439</enum>
440
441<enum name="a5xx_ras_perfcounter_select">
442	<value value="0" name="PERF_RAS_BUSY_CYCLES"/>
443	<value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
444	<value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
445	<value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
446	<value value="4" name="PERF_RAS_SUPER_TILES"/>
447	<value value="5" name="PERF_RAS_8X4_TILES"/>
448	<value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
449	<value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
450	<value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
451	<value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
452</enum>
453
454<enum name="a5xx_lrz_perfcounter_select">
455	<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
456	<value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
457	<value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
458	<value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
459	<value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
460	<value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
461	<value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
462	<value value="7" name="PERF_LRZ_LRZ_READ"/>
463	<value value="8" name="PERF_LRZ_LRZ_WRITE"/>
464	<value value="9" name="PERF_LRZ_READ_LATENCY"/>
465	<value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
466	<value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
467	<value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
468	<value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
469	<value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
470	<value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
471	<value value="16" name="PERF_LRZ_TILE_KILLED"/>
472	<value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
473	<value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
474</enum>
475
476<enum name="a5xx_uche_perfcounter_select">
477	<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
478	<value value="1" name="PERF_UCHE_STALL_CYCLES_VBIF"/>
479	<value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
480	<value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
481	<value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
482	<value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
483	<value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
484	<value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
485	<value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
486	<value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
487	<value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
488	<value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
489	<value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
490	<value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
491	<value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
492	<value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
493	<value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
494	<value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
495	<value value="18" name="PERF_UCHE_EVICTS"/>
496	<value value="19" name="PERF_UCHE_BANK_REQ0"/>
497	<value value="20" name="PERF_UCHE_BANK_REQ1"/>
498	<value value="21" name="PERF_UCHE_BANK_REQ2"/>
499	<value value="22" name="PERF_UCHE_BANK_REQ3"/>
500	<value value="23" name="PERF_UCHE_BANK_REQ4"/>
501	<value value="24" name="PERF_UCHE_BANK_REQ5"/>
502	<value value="25" name="PERF_UCHE_BANK_REQ6"/>
503	<value value="26" name="PERF_UCHE_BANK_REQ7"/>
504	<value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
505	<value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
506	<value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
507	<value value="30" name="PERF_UCHE_FLAG_COUNT"/>
508</enum>
509
510<enum name="a5xx_tp_perfcounter_select">
511	<value value="0" name="PERF_TP_BUSY_CYCLES"/>
512	<value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
513	<value value="2" name="PERF_TP_LATENCY_CYCLES"/>
514	<value value="3" name="PERF_TP_LATENCY_TRANS"/>
515	<value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
516	<value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
517	<value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
518	<value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
519	<value value="8" name="PERF_TP_SP_TP_TRANS"/>
520	<value value="9" name="PERF_TP_TP_SP_TRANS"/>
521	<value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
522	<value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
523	<value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
524	<value value="13" name="PERF_TP_QUADS_RECEIVED"/>
525	<value value="14" name="PERF_TP_QUADS_OFFSET"/>
526	<value value="15" name="PERF_TP_QUADS_SHADOW"/>
527	<value value="16" name="PERF_TP_QUADS_ARRAY"/>
528	<value value="17" name="PERF_TP_QUADS_GRADIENT"/>
529	<value value="18" name="PERF_TP_QUADS_1D"/>
530	<value value="19" name="PERF_TP_QUADS_2D"/>
531	<value value="20" name="PERF_TP_QUADS_BUFFER"/>
532	<value value="21" name="PERF_TP_QUADS_3D"/>
533	<value value="22" name="PERF_TP_QUADS_CUBE"/>
534	<value value="23" name="PERF_TP_STATE_CACHE_REQUESTS"/>
535	<value value="24" name="PERF_TP_STATE_CACHE_MISSES"/>
536	<value value="25" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
537	<value value="26" name="PERF_TP_BINDLESS_STATE_CACHE_REQUESTS"/>
538	<value value="27" name="PERF_TP_BINDLESS_STATE_CACHE_MISSES"/>
539	<value value="28" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
540	<value value="29" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
541	<value value="30" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
542	<value value="31" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
543	<value value="32" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
544	<value value="33" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
545	<value value="34" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
546	<value value="35" name="PERF_TP_FLAG_CACHE_MISSES"/>
547	<value value="36" name="PERF_TP_L1_5_L2_REQUESTS"/>
548	<value value="37" name="PERF_TP_2D_OUTPUT_PIXELS"/>
549	<value value="38" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
550	<value value="39" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
551	<value value="40" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
552	<value value="41" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
553</enum>
554
555<enum name="a5xx_sp_perfcounter_select">
556	<value value="0" name="PERF_SP_BUSY_CYCLES"/>
557	<value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
558	<value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
559	<value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
560	<value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
561	<value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
562	<value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
563	<value value="7" name="PERF_SP_SCHEDULER_NON_WORKING"/>
564	<value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
565	<value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
566	<value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
567	<value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
568	<value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
569	<value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
570	<value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
571	<value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
572	<value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
573	<value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
574	<value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
575	<value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
576	<value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
577	<value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
578	<value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
579	<value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
580	<value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
581	<value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
582	<value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
583	<value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
584	<value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
585	<value value="29" name="PERF_SP_LM_ATOMICS"/>
586	<value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
587	<value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
588	<value value="32" name="PERF_SP_GM_ATOMICS"/>
589	<value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
590	<value value="34" name="PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
591	<value value="35" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
592	<value value="36" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
593	<value value="37" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
594	<value value="38" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
595	<value value="39" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
596	<value value="40" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
597	<value value="41" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
598	<value value="42" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
599	<value value="43" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
600	<value value="44" name="PERF_SP_VS_INSTRUCTIONS"/>
601	<value value="45" name="PERF_SP_FS_INSTRUCTIONS"/>
602	<value value="46" name="PERF_SP_ADDR_LOCK_COUNT"/>
603	<value value="47" name="PERF_SP_UCHE_READ_TRANS"/>
604	<value value="48" name="PERF_SP_UCHE_WRITE_TRANS"/>
605	<value value="49" name="PERF_SP_EXPORT_VPC_TRANS"/>
606	<value value="50" name="PERF_SP_EXPORT_RB_TRANS"/>
607	<value value="51" name="PERF_SP_PIXELS_KILLED"/>
608	<value value="52" name="PERF_SP_ICL1_REQUESTS"/>
609	<value value="53" name="PERF_SP_ICL1_MISSES"/>
610	<value value="54" name="PERF_SP_ICL0_REQUESTS"/>
611	<value value="55" name="PERF_SP_ICL0_MISSES"/>
612	<value value="56" name="PERF_SP_HS_INSTRUCTIONS"/>
613	<value value="57" name="PERF_SP_DS_INSTRUCTIONS"/>
614	<value value="58" name="PERF_SP_GS_INSTRUCTIONS"/>
615	<value value="59" name="PERF_SP_CS_INSTRUCTIONS"/>
616	<value value="60" name="PERF_SP_GPR_READ"/>
617	<value value="61" name="PERF_SP_GPR_WRITE"/>
618	<value value="62" name="PERF_SP_LM_CH0_REQUESTS"/>
619	<value value="63" name="PERF_SP_LM_CH1_REQUESTS"/>
620	<value value="64" name="PERF_SP_LM_BANK_CONFLICTS"/>
621</enum>
622
623<enum name="a5xx_rb_perfcounter_select">
624	<value value="0" name="PERF_RB_BUSY_CYCLES"/>
625	<value value="1" name="PERF_RB_STALL_CYCLES_CCU"/>
626	<value value="2" name="PERF_RB_STALL_CYCLES_HLSQ"/>
627	<value value="3" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
628	<value value="4" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
629	<value value="5" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
630	<value value="6" name="PERF_RB_STARVE_CYCLES_SP"/>
631	<value value="7" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
632	<value value="8" name="PERF_RB_STARVE_CYCLES_CCU"/>
633	<value value="9" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
634	<value value="10" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
635	<value value="11" name="PERF_RB_Z_WORKLOAD"/>
636	<value value="12" name="PERF_RB_HLSQ_ACTIVE"/>
637	<value value="13" name="PERF_RB_Z_READ"/>
638	<value value="14" name="PERF_RB_Z_WRITE"/>
639	<value value="15" name="PERF_RB_C_READ"/>
640	<value value="16" name="PERF_RB_C_WRITE"/>
641	<value value="17" name="PERF_RB_TOTAL_PASS"/>
642	<value value="18" name="PERF_RB_Z_PASS"/>
643	<value value="19" name="PERF_RB_Z_FAIL"/>
644	<value value="20" name="PERF_RB_S_FAIL"/>
645	<value value="21" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
646	<value value="22" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
647	<value value="23" name="RB_RESERVED"/>
648	<value value="24" name="PERF_RB_2D_ALIVE_CYCLES"/>
649	<value value="25" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
650	<value value="26" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
651	<value value="27" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
652	<value value="28" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
653	<value value="29" name="PERF_RB_2D_VALID_PIXELS"/>
654</enum>
655
656<enum name="a5xx_rb_samples_perfcounter_select">
657	<value value="0" name="TOTAL_SAMPLES"/>
658	<value value="1" name="ZPASS_SAMPLES"/>
659	<value value="2" name="ZFAIL_SAMPLES"/>
660	<value value="3" name="SFAIL_SAMPLES"/>
661</enum>
662
663<enum name="a5xx_vsc_perfcounter_select">
664	<value value="0" name="PERF_VSC_BUSY_CYCLES"/>
665	<value value="1" name="PERF_VSC_WORKING_CYCLES"/>
666	<value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
667	<value value="3" name="PERF_VSC_EOT_NUM"/>
668</enum>
669
670<enum name="a5xx_ccu_perfcounter_select">
671	<value value="0" name="PERF_CCU_BUSY_CYCLES"/>
672	<value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
673	<value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
674	<value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
675	<value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
676	<value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
677	<value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
678	<value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
679	<value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
680	<value value="9" name="PERF_CCU_GMEM_READ"/>
681	<value value="10" name="PERF_CCU_GMEM_WRITE"/>
682	<value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
683	<value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
684	<value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
685	<value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
686	<value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
687	<value value="16" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
688	<value value="17" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
689	<value value="18" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
690	<value value="19" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
691	<value value="20" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
692	<value value="21" name="PERF_CCU_2D_BUSY_CYCLES"/>
693	<value value="22" name="PERF_CCU_2D_RD_REQ"/>
694	<value value="23" name="PERF_CCU_2D_WR_REQ"/>
695	<value value="24" name="PERF_CCU_2D_REORDER_STARVE_CYCLES"/>
696	<value value="25" name="PERF_CCU_2D_PIXELS"/>
697</enum>
698
699<enum name="a5xx_cmp_perfcounter_select">
700	<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/>
701	<value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
702	<value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
703	<value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
704	<value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
705	<value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
706	<value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
707	<value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
708	<value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
709	<value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
710	<value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
711	<value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
712	<value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
713	<value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
714	<value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
715	<value value="15" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
716	<value value="16" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
717	<value value="17" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
718	<value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
719	<value value="19" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
720	<value value="20" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
721	<value value="21" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
722	<value value="22" name="PERF_CMPDECMP_2D_RD_DATA"/>
723	<value value="23" name="PERF_CMPDECMP_2D_WR_DATA"/>
724</enum>
725
726<enum name="a5xx_vbif_perfcounter_select">
727	<value value="0" name="AXI_READ_REQUESTS_ID_0"/>
728	<value value="1" name="AXI_READ_REQUESTS_ID_1"/>
729	<value value="2" name="AXI_READ_REQUESTS_ID_2"/>
730	<value value="3" name="AXI_READ_REQUESTS_ID_3"/>
731	<value value="4" name="AXI_READ_REQUESTS_ID_4"/>
732	<value value="5" name="AXI_READ_REQUESTS_ID_5"/>
733	<value value="6" name="AXI_READ_REQUESTS_ID_6"/>
734	<value value="7" name="AXI_READ_REQUESTS_ID_7"/>
735	<value value="8" name="AXI_READ_REQUESTS_ID_8"/>
736	<value value="9" name="AXI_READ_REQUESTS_ID_9"/>
737	<value value="10" name="AXI_READ_REQUESTS_ID_10"/>
738	<value value="11" name="AXI_READ_REQUESTS_ID_11"/>
739	<value value="12" name="AXI_READ_REQUESTS_ID_12"/>
740	<value value="13" name="AXI_READ_REQUESTS_ID_13"/>
741	<value value="14" name="AXI_READ_REQUESTS_ID_14"/>
742	<value value="15" name="AXI_READ_REQUESTS_ID_15"/>
743	<value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
744	<value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
745	<value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
746	<value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
747	<value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
748	<value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
749	<value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
750	<value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
751	<value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
752	<value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
753	<value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
754	<value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
755	<value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
756	<value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
757	<value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
758	<value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
759	<value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
760	<value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
761	<value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
762	<value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
763	<value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
764	<value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
765	<value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
766	<value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
767	<value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
768	<value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
769	<value value="42" name="AXI_TOTAL_REQUESTS"/>
770	<value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
771	<value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
772	<value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
773	<value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
774	<value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
775	<value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
776	<value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
777	<value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
778	<value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
779	<value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
780	<value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
781	<value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
782	<value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
783	<value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
784	<value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
785	<value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
786	<value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
787	<value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
788	<value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
789	<value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
790	<value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
791	<value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
792	<value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
793	<value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
794	<value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
795	<value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
796	<value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
797	<value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
798	<value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
799	<value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
800	<value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
801	<value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
802	<value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
803	<value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
804	<value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
805	<value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
806	<value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
807	<value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
808	<value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
809	<value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
810	<value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
811	<value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
812	<value value="85" name="AXI_DATA_BEATS_TOTAL"/>
813</enum>
814
815<domain name="A5XX" width="32">
816	<bitset name="A5XX_INT0">
817		<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
818		<bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
819		<bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
820		<bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
821		<bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
822		<bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
823		<bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
824		<bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
825		<bitfield name="CP_SW" pos="8" type="boolean"/>
826		<bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
827		<bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
828		<bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
829		<bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
830		<bitfield name="CP_IB2" pos="13" type="boolean"/>
831		<bitfield name="CP_IB1" pos="14" type="boolean"/>
832		<bitfield name="CP_RB" pos="15" type="boolean"/>
833		<bitfield name="CP_UNUSED_1" pos="16" type="boolean"/>
834		<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
835		<bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
836		<bitfield name="UNKNOWN_1" pos="19" type="boolean"/>
837		<bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
838		<bitfield name="UNUSED_2" pos="21" type="boolean"/>
839		<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
840		<bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
841		<bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
842		<bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
843		<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
844		<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
845		<bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
846		<bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
847		<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
848		<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
849	</bitset>
850
851	<!-- CP Interrupt bits -->
852	<bitset name="A5XX_CP_INT">
853		<bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
854		<bitfield name="CP_RESERVED_BIT_ERROR" pos="1" type="boolean"/>
855		<bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
856		<bitfield name="CP_DMA_ERROR" pos="3" type="boolean"/>
857		<bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
858		<bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
859	</bitset>
860
861	<!-- CP registers -->
862	<reg32 offset="0x0800" name="CP_RB_BASE"/>
863	<reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864	<reg32 offset="0x0802" name="CP_RB_CNTL"/>
865	<reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866	<reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867	<reg32 offset="0x0806" name="CP_RB_RPTR"/>
868	<reg32 offset="0x0807" name="CP_RB_WPTR"/>
869	<reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870	<reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871	<reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
872	<reg32 offset="0x080c" name="CP_DRAW_STATE_DATA"/>
873	<reg32 offset="0x080d" name="CP_ME_NRT_ADDR_LO"/>
874	<reg32 offset="0x080e" name="CP_ME_NRT_ADDR_HI"/>
875	<reg32 offset="0x0810" name="CP_ME_NRT_DATA"/>
876	<reg32 offset="0x0817" name="CP_CRASH_SCRIPT_BASE_LO"/>
877	<reg32 offset="0x0818" name="CP_CRASH_SCRIPT_BASE_HI"/>
878	<reg32 offset="0x0819" name="CP_CRASH_DUMP_CNTL"/>
879	<reg32 offset="0x081a" name="CP_ME_STAT_ADDR"/>
880	<reg32 offset="0x081f" name="CP_ROQ_THRESHOLDS_1"/>
881	<reg32 offset="0x0820" name="CP_ROQ_THRESHOLDS_2"/>
882	<reg32 offset="0x0821" name="CP_ROQ_DBG_ADDR"/>
883	<reg32 offset="0x0822" name="CP_ROQ_DBG_DATA"/>
884	<reg32 offset="0x0823" name="CP_MEQ_DBG_ADDR"/>
885	<reg32 offset="0x0824" name="CP_MEQ_DBG_DATA"/>
886	<reg32 offset="0x0825" name="CP_MEQ_THRESHOLDS"/>
887	<reg32 offset="0x0826" name="CP_MERCIU_SIZE"/>
888	<reg32 offset="0x0827" name="CP_MERCIU_DBG_ADDR"/>
889	<reg32 offset="0x0828" name="CP_MERCIU_DBG_DATA_1"/>
890	<reg32 offset="0x0829" name="CP_MERCIU_DBG_DATA_2"/>
891	<reg32 offset="0x082a" name="CP_PFP_UCODE_DBG_ADDR"/>
892	<reg32 offset="0x082b" name="CP_PFP_UCODE_DBG_DATA"/>
893	<reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/>
894	<reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/>
895	<reg32 offset="0x0831" name="CP_CNTL"/>
896	<reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/>
897	<reg32 offset="0x0833" name="CP_CHICKEN_DBG"/>
898	<reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/>
899	<reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/>
900	<reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/>
901	<reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/>
902	<reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/>
903	<reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/>
904	<reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/>
905	<reg32 offset="0x083e" name="CP_CONTEXT_SWITCH_SAVE_ADDR_LO"/>
906	<reg32 offset="0x083f" name="CP_CONTEXT_SWITCH_SAVE_ADDR_HI"/>
907	<reg32 offset="0x0840" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
908	<reg32 offset="0x0841" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
909	<reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
910	<reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/>
911	<reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/>
912	<reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/>
913	<reg32 offset="0x0b1a" name="CP_HW_FAULT"/>
914	<reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/>
915	<reg32 offset="0x0b1f" name="CP_IB1_BASE"/>
916	<reg32 offset="0x0b20" name="CP_IB1_BASE_HI"/>
917	<reg32 offset="0x0b21" name="CP_IB1_BUFSZ"/>
918	<reg32 offset="0x0b22" name="CP_IB2_BASE"/>
919	<reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/>
920	<reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/>
921	<array offset="0x0b78" name="CP_SCRATCH" stride="1" length="8">
922		<reg32 offset="0x0" name="REG" type="uint"/>
923	</array>
924	<array offset="0x0880" name="CP_PROTECT" stride="1" length="32">
925		<reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
926	</array>
927	<reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/>
928	<reg32 offset="0x0b1b" name="CP_AHB_FAULT"/>
929	<reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0" type="a5xx_cp_perfcounter_select"/>
930	<reg32 offset="0x0bb1" name="CP_PERFCTR_CP_SEL_1" type="a5xx_cp_perfcounter_select"/>
931	<reg32 offset="0x0bb2" name="CP_PERFCTR_CP_SEL_2" type="a5xx_cp_perfcounter_select"/>
932	<reg32 offset="0x0bb3" name="CP_PERFCTR_CP_SEL_3" type="a5xx_cp_perfcounter_select"/>
933	<reg32 offset="0x0bb4" name="CP_PERFCTR_CP_SEL_4" type="a5xx_cp_perfcounter_select"/>
934	<reg32 offset="0x0bb5" name="CP_PERFCTR_CP_SEL_5" type="a5xx_cp_perfcounter_select"/>
935	<reg32 offset="0x0bb6" name="CP_PERFCTR_CP_SEL_6" type="a5xx_cp_perfcounter_select"/>
936	<reg32 offset="0x0bb7" name="CP_PERFCTR_CP_SEL_7" type="a5xx_cp_perfcounter_select"/>
937	<reg32 offset="0x0bc1" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
938	<reg32 offset="0x0bba" name="CP_POWERCTR_CP_SEL_0"/>
939	<reg32 offset="0x0bbb" name="CP_POWERCTR_CP_SEL_1"/>
940	<reg32 offset="0x0bbc" name="CP_POWERCTR_CP_SEL_2"/>
941	<reg32 offset="0x0bbd" name="CP_POWERCTR_CP_SEL_3"/>
942
943	<!-- RBBM registers -->
944	<reg32 offset="0x0004" name="RBBM_CFG_DBGBUS_SEL_A"/>
945	<reg32 offset="0x0005" name="RBBM_CFG_DBGBUS_SEL_B"/>
946	<reg32 offset="0x0006" name="RBBM_CFG_DBGBUS_SEL_C"/>
947	<reg32 offset="0x0007" name="RBBM_CFG_DBGBUS_SEL_D"/>
948<!--
949#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT    0x0
950#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT  0x8
951#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT    0x10
952#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT  0x18
953 -->
954	<reg32 offset="0x0008" name="RBBM_CFG_DBGBUS_CNTLT"/>
955	<reg32 offset="0x0009" name="RBBM_CFG_DBGBUS_CNTLM"/>
956	<reg32 offset="0x0018" name="RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT"/>
957	<reg32 offset="0x000a" name="RBBM_CFG_DBGBUS_OPL"/>
958	<reg32 offset="0x000b" name="RBBM_CFG_DBGBUS_OPE"/>
959	<reg32 offset="0x000c" name="RBBM_CFG_DBGBUS_IVTL_0"/>
960	<reg32 offset="0x000d" name="RBBM_CFG_DBGBUS_IVTL_1"/>
961	<reg32 offset="0x000e" name="RBBM_CFG_DBGBUS_IVTL_2"/>
962	<reg32 offset="0x000f" name="RBBM_CFG_DBGBUS_IVTL_3"/>
963	<reg32 offset="0x0010" name="RBBM_CFG_DBGBUS_MASKL_0"/>
964	<reg32 offset="0x0011" name="RBBM_CFG_DBGBUS_MASKL_1"/>
965	<reg32 offset="0x0012" name="RBBM_CFG_DBGBUS_MASKL_2"/>
966	<reg32 offset="0x0013" name="RBBM_CFG_DBGBUS_MASKL_3"/>
967	<reg32 offset="0x0014" name="RBBM_CFG_DBGBUS_BYTEL_0"/>
968	<reg32 offset="0x0015" name="RBBM_CFG_DBGBUS_BYTEL_1"/>
969	<reg32 offset="0x0016" name="RBBM_CFG_DBGBUS_IVTE_0"/>
970	<reg32 offset="0x0017" name="RBBM_CFG_DBGBUS_IVTE_1"/>
971	<reg32 offset="0x0018" name="RBBM_CFG_DBGBUS_IVTE_2"/>
972	<reg32 offset="0x0019" name="RBBM_CFG_DBGBUS_IVTE_3"/>
973	<reg32 offset="0x001a" name="RBBM_CFG_DBGBUS_MASKE_0"/>
974	<reg32 offset="0x001b" name="RBBM_CFG_DBGBUS_MASKE_1"/>
975	<reg32 offset="0x001c" name="RBBM_CFG_DBGBUS_MASKE_2"/>
976	<reg32 offset="0x001d" name="RBBM_CFG_DBGBUS_MASKE_3"/>
977	<reg32 offset="0x001e" name="RBBM_CFG_DBGBUS_NIBBLEE"/>
978	<reg32 offset="0x001f" name="RBBM_CFG_DBGBUS_PTRC0"/>
979	<reg32 offset="0x0020" name="RBBM_CFG_DBGBUS_PTRC1"/>
980	<reg32 offset="0x0021" name="RBBM_CFG_DBGBUS_LOADREG"/>
981	<reg32 offset="0x0022" name="RBBM_CFG_DBGBUS_IDX"/>
982	<reg32 offset="0x0023" name="RBBM_CFG_DBGBUS_CLRC"/>
983	<reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/>
984	<reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
985	<reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
986	<reg32 offset="0x0038" name="RBBM_INT_0_MASK">
987		<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
988		<bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
989		<bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
990		<bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
991		<bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
992		<bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
993		<bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
994		<bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
995		<bitfield name="CP_SW" pos="8" type="boolean"/>
996		<bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
997		<bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
998		<bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
999		<bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
1000		<bitfield name="CP_IB2" pos="13" type="boolean"/>
1001		<bitfield name="CP_IB1" pos="14" type="boolean"/>
1002		<bitfield name="CP_RB" pos="15" type="boolean"/>
1003		<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
1004		<bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
1005		<bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
1006		<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
1007		<bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
1008		<bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
1009		<bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
1010		<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
1011		<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
1012		<bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
1013		<bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
1014		<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
1015		<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
1016	</reg32>
1017	<reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/>
1018	<reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/>
1019	<reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
1020	<reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1021	<reg32 offset="0x0046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1022	<reg32 offset="0x0048" name="RBBM_DBG_LO_HI_GPIO"/>
1023	<reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CNTL"/>
1024	<reg32 offset="0x004a" name="RBBM_CLOCK_CNTL_TP0"/>
1025	<reg32 offset="0x004b" name="RBBM_CLOCK_CNTL_TP1"/>
1026	<reg32 offset="0x004c" name="RBBM_CLOCK_CNTL_TP2"/>
1027	<reg32 offset="0x004d" name="RBBM_CLOCK_CNTL_TP3"/>
1028	<reg32 offset="0x004e" name="RBBM_CLOCK_CNTL2_TP0"/>
1029	<reg32 offset="0x004f" name="RBBM_CLOCK_CNTL2_TP1"/>
1030	<reg32 offset="0x0050" name="RBBM_CLOCK_CNTL2_TP2"/>
1031	<reg32 offset="0x0051" name="RBBM_CLOCK_CNTL2_TP3"/>
1032	<reg32 offset="0x0052" name="RBBM_CLOCK_CNTL3_TP0"/>
1033	<reg32 offset="0x0053" name="RBBM_CLOCK_CNTL3_TP1"/>
1034	<reg32 offset="0x0054" name="RBBM_CLOCK_CNTL3_TP2"/>
1035	<reg32 offset="0x0055" name="RBBM_CLOCK_CNTL3_TP3"/>
1036	<reg32 offset="0x0059" name="RBBM_READ_AHB_THROUGH_DBG"/>
1037	<reg32 offset="0x005a" name="RBBM_CLOCK_CNTL_UCHE"/>
1038	<reg32 offset="0x005b" name="RBBM_CLOCK_CNTL2_UCHE"/>
1039	<reg32 offset="0x005c" name="RBBM_CLOCK_CNTL3_UCHE"/>
1040	<reg32 offset="0x005d" name="RBBM_CLOCK_CNTL4_UCHE"/>
1041	<reg32 offset="0x005e" name="RBBM_CLOCK_HYST_UCHE"/>
1042	<reg32 offset="0x005f" name="RBBM_CLOCK_DELAY_UCHE"/>
1043	<reg32 offset="0x0060" name="RBBM_CLOCK_MODE_GPC"/>
1044	<reg32 offset="0x0061" name="RBBM_CLOCK_DELAY_GPC"/>
1045	<reg32 offset="0x0062" name="RBBM_CLOCK_HYST_GPC"/>
1046	<reg32 offset="0x0063" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1047	<reg32 offset="0x0064" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1048	<reg32 offset="0x0065" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1049	<reg32 offset="0x0066" name="RBBM_CLOCK_DELAY_HLSQ"/>
1050	<reg32 offset="0x0067" name="RBBM_CLOCK_CNTL"/>
1051	<reg32 offset="0x0068" name="RBBM_CLOCK_CNTL_SP0"/>
1052	<reg32 offset="0x0069" name="RBBM_CLOCK_CNTL_SP1"/>
1053	<reg32 offset="0x006a" name="RBBM_CLOCK_CNTL_SP2"/>
1054	<reg32 offset="0x006b" name="RBBM_CLOCK_CNTL_SP3"/>
1055	<reg32 offset="0x006c" name="RBBM_CLOCK_CNTL2_SP0"/>
1056	<reg32 offset="0x006d" name="RBBM_CLOCK_CNTL2_SP1"/>
1057	<reg32 offset="0x006e" name="RBBM_CLOCK_CNTL2_SP2"/>
1058	<reg32 offset="0x006f" name="RBBM_CLOCK_CNTL2_SP3"/>
1059	<reg32 offset="0x0070" name="RBBM_CLOCK_HYST_SP0"/>
1060	<reg32 offset="0x0071" name="RBBM_CLOCK_HYST_SP1"/>
1061	<reg32 offset="0x0072" name="RBBM_CLOCK_HYST_SP2"/>
1062	<reg32 offset="0x0073" name="RBBM_CLOCK_HYST_SP3"/>
1063	<reg32 offset="0x0074" name="RBBM_CLOCK_DELAY_SP0"/>
1064	<reg32 offset="0x0075" name="RBBM_CLOCK_DELAY_SP1"/>
1065	<reg32 offset="0x0076" name="RBBM_CLOCK_DELAY_SP2"/>
1066	<reg32 offset="0x0077" name="RBBM_CLOCK_DELAY_SP3"/>
1067	<reg32 offset="0x0078" name="RBBM_CLOCK_CNTL_RB0"/>
1068	<reg32 offset="0x0079" name="RBBM_CLOCK_CNTL_RB1"/>
1069	<reg32 offset="0x007a" name="RBBM_CLOCK_CNTL_RB2"/>
1070	<reg32 offset="0x007b" name="RBBM_CLOCK_CNTL_RB3"/>
1071	<reg32 offset="0x007c" name="RBBM_CLOCK_CNTL2_RB0"/>
1072	<reg32 offset="0x007d" name="RBBM_CLOCK_CNTL2_RB1"/>
1073	<reg32 offset="0x007e" name="RBBM_CLOCK_CNTL2_RB2"/>
1074	<reg32 offset="0x007f" name="RBBM_CLOCK_CNTL2_RB3"/>
1075	<reg32 offset="0x0080" name="RBBM_CLOCK_HYST_RAC"/>
1076	<reg32 offset="0x0081" name="RBBM_CLOCK_DELAY_RAC"/>
1077	<reg32 offset="0x0082" name="RBBM_CLOCK_CNTL_CCU0"/>
1078	<reg32 offset="0x0083" name="RBBM_CLOCK_CNTL_CCU1"/>
1079	<reg32 offset="0x0084" name="RBBM_CLOCK_CNTL_CCU2"/>
1080	<reg32 offset="0x0085" name="RBBM_CLOCK_CNTL_CCU3"/>
1081	<reg32 offset="0x0086" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1082	<reg32 offset="0x0087" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1083	<reg32 offset="0x0088" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1084	<reg32 offset="0x0089" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1085	<reg32 offset="0x008a" name="RBBM_CLOCK_CNTL_RAC"/>
1086	<reg32 offset="0x008b" name="RBBM_CLOCK_CNTL2_RAC"/>
1087	<reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_RB_CCU_L1_0"/>
1088	<reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_RB_CCU_L1_1"/>
1089	<reg32 offset="0x008e" name="RBBM_CLOCK_DELAY_RB_CCU_L1_2"/>
1090	<reg32 offset="0x008f" name="RBBM_CLOCK_DELAY_RB_CCU_L1_3"/>
1091	<reg32 offset="0x0090" name="RBBM_CLOCK_HYST_VFD"/>
1092	<reg32 offset="0x0091" name="RBBM_CLOCK_MODE_VFD"/>
1093	<reg32 offset="0x0092" name="RBBM_CLOCK_DELAY_VFD"/>
1094	<reg32 offset="0x0093" name="RBBM_AHB_CNTL0"/>
1095	<reg32 offset="0x0094" name="RBBM_AHB_CNTL1"/>
1096	<reg32 offset="0x0095" name="RBBM_AHB_CNTL2"/>
1097	<reg32 offset="0x0096" name="RBBM_AHB_CMD"/>
1098	<reg32 offset="0x009c" name="RBBM_INTERFACE_HANG_MASK_CNTL11"/>
1099	<reg32 offset="0x009d" name="RBBM_INTERFACE_HANG_MASK_CNTL12"/>
1100	<reg32 offset="0x009e" name="RBBM_INTERFACE_HANG_MASK_CNTL13"/>
1101	<reg32 offset="0x009f" name="RBBM_INTERFACE_HANG_MASK_CNTL14"/>
1102	<reg32 offset="0x00a0" name="RBBM_INTERFACE_HANG_MASK_CNTL15"/>
1103	<reg32 offset="0x00a1" name="RBBM_INTERFACE_HANG_MASK_CNTL16"/>
1104	<reg32 offset="0x00a2" name="RBBM_INTERFACE_HANG_MASK_CNTL17"/>
1105	<reg32 offset="0x00a3" name="RBBM_INTERFACE_HANG_MASK_CNTL18"/>
1106	<reg32 offset="0x00a4" name="RBBM_CLOCK_DELAY_TP0"/>
1107	<reg32 offset="0x00a5" name="RBBM_CLOCK_DELAY_TP1"/>
1108	<reg32 offset="0x00a6" name="RBBM_CLOCK_DELAY_TP2"/>
1109	<reg32 offset="0x00a7" name="RBBM_CLOCK_DELAY_TP3"/>
1110	<reg32 offset="0x00a8" name="RBBM_CLOCK_DELAY2_TP0"/>
1111	<reg32 offset="0x00a9" name="RBBM_CLOCK_DELAY2_TP1"/>
1112	<reg32 offset="0x00aa" name="RBBM_CLOCK_DELAY2_TP2"/>
1113	<reg32 offset="0x00ab" name="RBBM_CLOCK_DELAY2_TP3"/>
1114	<reg32 offset="0x00ac" name="RBBM_CLOCK_DELAY3_TP0"/>
1115	<reg32 offset="0x00ad" name="RBBM_CLOCK_DELAY3_TP1"/>
1116	<reg32 offset="0x00ae" name="RBBM_CLOCK_DELAY3_TP2"/>
1117	<reg32 offset="0x00af" name="RBBM_CLOCK_DELAY3_TP3"/>
1118	<reg32 offset="0x00b0" name="RBBM_CLOCK_HYST_TP0"/>
1119	<reg32 offset="0x00b1" name="RBBM_CLOCK_HYST_TP1"/>
1120	<reg32 offset="0x00b2" name="RBBM_CLOCK_HYST_TP2"/>
1121	<reg32 offset="0x00b3" name="RBBM_CLOCK_HYST_TP3"/>
1122	<reg32 offset="0x00b4" name="RBBM_CLOCK_HYST2_TP0"/>
1123	<reg32 offset="0x00b5" name="RBBM_CLOCK_HYST2_TP1"/>
1124	<reg32 offset="0x00b6" name="RBBM_CLOCK_HYST2_TP2"/>
1125	<reg32 offset="0x00b7" name="RBBM_CLOCK_HYST2_TP3"/>
1126	<reg32 offset="0x00b8" name="RBBM_CLOCK_HYST3_TP0"/>
1127	<reg32 offset="0x00b9" name="RBBM_CLOCK_HYST3_TP1"/>
1128	<reg32 offset="0x00ba" name="RBBM_CLOCK_HYST3_TP2"/>
1129	<reg32 offset="0x00bb" name="RBBM_CLOCK_HYST3_TP3"/>
1130	<reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL_GPMU"/>
1131	<reg32 offset="0x00c9" name="RBBM_CLOCK_DELAY_GPMU"/>
1132	<reg32 offset="0x00ca" name="RBBM_CLOCK_HYST_GPMU"/>
1133	<reg32 offset="0x03a0" name="RBBM_PERFCTR_CP_0_LO"/>
1134	<reg32 offset="0x03a1" name="RBBM_PERFCTR_CP_0_HI"/>
1135	<reg32 offset="0x03a2" name="RBBM_PERFCTR_CP_1_LO"/>
1136	<reg32 offset="0x03a3" name="RBBM_PERFCTR_CP_1_HI"/>
1137	<reg32 offset="0x03a4" name="RBBM_PERFCTR_CP_2_LO"/>
1138	<reg32 offset="0x03a5" name="RBBM_PERFCTR_CP_2_HI"/>
1139	<reg32 offset="0x03a6" name="RBBM_PERFCTR_CP_3_LO"/>
1140	<reg32 offset="0x03a7" name="RBBM_PERFCTR_CP_3_HI"/>
1141	<reg32 offset="0x03a8" name="RBBM_PERFCTR_CP_4_LO"/>
1142	<reg32 offset="0x03a9" name="RBBM_PERFCTR_CP_4_HI"/>
1143	<reg32 offset="0x03aa" name="RBBM_PERFCTR_CP_5_LO"/>
1144	<reg32 offset="0x03ab" name="RBBM_PERFCTR_CP_5_HI"/>
1145	<reg32 offset="0x03ac" name="RBBM_PERFCTR_CP_6_LO"/>
1146	<reg32 offset="0x03ad" name="RBBM_PERFCTR_CP_6_HI"/>
1147	<reg32 offset="0x03ae" name="RBBM_PERFCTR_CP_7_LO"/>
1148	<reg32 offset="0x03af" name="RBBM_PERFCTR_CP_7_HI"/>
1149	<reg32 offset="0x03b0" name="RBBM_PERFCTR_RBBM_0_LO"/>
1150	<reg32 offset="0x03b1" name="RBBM_PERFCTR_RBBM_0_HI"/>
1151	<reg32 offset="0x03b2" name="RBBM_PERFCTR_RBBM_1_LO"/>
1152	<reg32 offset="0x03b3" name="RBBM_PERFCTR_RBBM_1_HI"/>
1153	<reg32 offset="0x03b4" name="RBBM_PERFCTR_RBBM_2_LO"/>
1154	<reg32 offset="0x03b5" name="RBBM_PERFCTR_RBBM_2_HI"/>
1155	<reg32 offset="0x03b6" name="RBBM_PERFCTR_RBBM_3_LO"/>
1156	<reg32 offset="0x03b7" name="RBBM_PERFCTR_RBBM_3_HI"/>
1157	<reg32 offset="0x03b8" name="RBBM_PERFCTR_PC_0_LO"/>
1158	<reg32 offset="0x03b9" name="RBBM_PERFCTR_PC_0_HI"/>
1159	<reg32 offset="0x03ba" name="RBBM_PERFCTR_PC_1_LO"/>
1160	<reg32 offset="0x03bb" name="RBBM_PERFCTR_PC_1_HI"/>
1161	<reg32 offset="0x03bc" name="RBBM_PERFCTR_PC_2_LO"/>
1162	<reg32 offset="0x03bd" name="RBBM_PERFCTR_PC_2_HI"/>
1163	<reg32 offset="0x03be" name="RBBM_PERFCTR_PC_3_LO"/>
1164	<reg32 offset="0x03bf" name="RBBM_PERFCTR_PC_3_HI"/>
1165	<reg32 offset="0x03c0" name="RBBM_PERFCTR_PC_4_LO"/>
1166	<reg32 offset="0x03c1" name="RBBM_PERFCTR_PC_4_HI"/>
1167	<reg32 offset="0x03c2" name="RBBM_PERFCTR_PC_5_LO"/>
1168	<reg32 offset="0x03c3" name="RBBM_PERFCTR_PC_5_HI"/>
1169	<reg32 offset="0x03c4" name="RBBM_PERFCTR_PC_6_LO"/>
1170	<reg32 offset="0x03c5" name="RBBM_PERFCTR_PC_6_HI"/>
1171	<reg32 offset="0x03c6" name="RBBM_PERFCTR_PC_7_LO"/>
1172	<reg32 offset="0x03c7" name="RBBM_PERFCTR_PC_7_HI"/>
1173	<reg32 offset="0x03c8" name="RBBM_PERFCTR_VFD_0_LO"/>
1174	<reg32 offset="0x03c9" name="RBBM_PERFCTR_VFD_0_HI"/>
1175	<reg32 offset="0x03ca" name="RBBM_PERFCTR_VFD_1_LO"/>
1176	<reg32 offset="0x03cb" name="RBBM_PERFCTR_VFD_1_HI"/>
1177	<reg32 offset="0x03cc" name="RBBM_PERFCTR_VFD_2_LO"/>
1178	<reg32 offset="0x03cd" name="RBBM_PERFCTR_VFD_2_HI"/>
1179	<reg32 offset="0x03ce" name="RBBM_PERFCTR_VFD_3_LO"/>
1180	<reg32 offset="0x03cf" name="RBBM_PERFCTR_VFD_3_HI"/>
1181	<reg32 offset="0x03d0" name="RBBM_PERFCTR_VFD_4_LO"/>
1182	<reg32 offset="0x03d1" name="RBBM_PERFCTR_VFD_4_HI"/>
1183	<reg32 offset="0x03d2" name="RBBM_PERFCTR_VFD_5_LO"/>
1184	<reg32 offset="0x03d3" name="RBBM_PERFCTR_VFD_5_HI"/>
1185	<reg32 offset="0x03d4" name="RBBM_PERFCTR_VFD_6_LO"/>
1186	<reg32 offset="0x03d5" name="RBBM_PERFCTR_VFD_6_HI"/>
1187	<reg32 offset="0x03d6" name="RBBM_PERFCTR_VFD_7_LO"/>
1188	<reg32 offset="0x03d7" name="RBBM_PERFCTR_VFD_7_HI"/>
1189	<reg32 offset="0x03d8" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1190	<reg32 offset="0x03d9" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1191	<reg32 offset="0x03da" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1192	<reg32 offset="0x03db" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1193	<reg32 offset="0x03dc" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1194	<reg32 offset="0x03dd" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1195	<reg32 offset="0x03de" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1196	<reg32 offset="0x03df" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1197	<reg32 offset="0x03e0" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1198	<reg32 offset="0x03e1" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1199	<reg32 offset="0x03e2" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1200	<reg32 offset="0x03e3" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1201	<reg32 offset="0x03e4" name="RBBM_PERFCTR_HLSQ_6_LO"/>
1202	<reg32 offset="0x03e5" name="RBBM_PERFCTR_HLSQ_6_HI"/>
1203	<reg32 offset="0x03e6" name="RBBM_PERFCTR_HLSQ_7_LO"/>
1204	<reg32 offset="0x03e7" name="RBBM_PERFCTR_HLSQ_7_HI"/>
1205	<reg32 offset="0x03e8" name="RBBM_PERFCTR_VPC_0_LO"/>
1206	<reg32 offset="0x03e9" name="RBBM_PERFCTR_VPC_0_HI"/>
1207	<reg32 offset="0x03ea" name="RBBM_PERFCTR_VPC_1_LO"/>
1208	<reg32 offset="0x03eb" name="RBBM_PERFCTR_VPC_1_HI"/>
1209	<reg32 offset="0x03ec" name="RBBM_PERFCTR_VPC_2_LO"/>
1210	<reg32 offset="0x03ed" name="RBBM_PERFCTR_VPC_2_HI"/>
1211	<reg32 offset="0x03ee" name="RBBM_PERFCTR_VPC_3_LO"/>
1212	<reg32 offset="0x03ef" name="RBBM_PERFCTR_VPC_3_HI"/>
1213	<reg32 offset="0x03f0" name="RBBM_PERFCTR_CCU_0_LO"/>
1214	<reg32 offset="0x03f1" name="RBBM_PERFCTR_CCU_0_HI"/>
1215	<reg32 offset="0x03f2" name="RBBM_PERFCTR_CCU_1_LO"/>
1216	<reg32 offset="0x03f3" name="RBBM_PERFCTR_CCU_1_HI"/>
1217	<reg32 offset="0x03f4" name="RBBM_PERFCTR_CCU_2_LO"/>
1218	<reg32 offset="0x03f5" name="RBBM_PERFCTR_CCU_2_HI"/>
1219	<reg32 offset="0x03f6" name="RBBM_PERFCTR_CCU_3_LO"/>
1220	<reg32 offset="0x03f7" name="RBBM_PERFCTR_CCU_3_HI"/>
1221	<reg32 offset="0x03f8" name="RBBM_PERFCTR_TSE_0_LO"/>
1222	<reg32 offset="0x03f9" name="RBBM_PERFCTR_TSE_0_HI"/>
1223	<reg32 offset="0x03fa" name="RBBM_PERFCTR_TSE_1_LO"/>
1224	<reg32 offset="0x03fb" name="RBBM_PERFCTR_TSE_1_HI"/>
1225	<reg32 offset="0x03fc" name="RBBM_PERFCTR_TSE_2_LO"/>
1226	<reg32 offset="0x03fd" name="RBBM_PERFCTR_TSE_2_HI"/>
1227	<reg32 offset="0x03fe" name="RBBM_PERFCTR_TSE_3_LO"/>
1228	<reg32 offset="0x03ff" name="RBBM_PERFCTR_TSE_3_HI"/>
1229	<reg32 offset="0x0400" name="RBBM_PERFCTR_RAS_0_LO"/>
1230	<reg32 offset="0x0401" name="RBBM_PERFCTR_RAS_0_HI"/>
1231	<reg32 offset="0x0402" name="RBBM_PERFCTR_RAS_1_LO"/>
1232	<reg32 offset="0x0403" name="RBBM_PERFCTR_RAS_1_HI"/>
1233	<reg32 offset="0x0404" name="RBBM_PERFCTR_RAS_2_LO"/>
1234	<reg32 offset="0x0405" name="RBBM_PERFCTR_RAS_2_HI"/>
1235	<reg32 offset="0x0406" name="RBBM_PERFCTR_RAS_3_LO"/>
1236	<reg32 offset="0x0407" name="RBBM_PERFCTR_RAS_3_HI"/>
1237	<reg32 offset="0x0408" name="RBBM_PERFCTR_UCHE_0_LO"/>
1238	<reg32 offset="0x0409" name="RBBM_PERFCTR_UCHE_0_HI"/>
1239	<reg32 offset="0x040a" name="RBBM_PERFCTR_UCHE_1_LO"/>
1240	<reg32 offset="0x040b" name="RBBM_PERFCTR_UCHE_1_HI"/>
1241	<reg32 offset="0x040c" name="RBBM_PERFCTR_UCHE_2_LO"/>
1242	<reg32 offset="0x040d" name="RBBM_PERFCTR_UCHE_2_HI"/>
1243	<reg32 offset="0x040e" name="RBBM_PERFCTR_UCHE_3_LO"/>
1244	<reg32 offset="0x040f" name="RBBM_PERFCTR_UCHE_3_HI"/>
1245	<reg32 offset="0x0410" name="RBBM_PERFCTR_UCHE_4_LO"/>
1246	<reg32 offset="0x0411" name="RBBM_PERFCTR_UCHE_4_HI"/>
1247	<reg32 offset="0x0412" name="RBBM_PERFCTR_UCHE_5_LO"/>
1248	<reg32 offset="0x0413" name="RBBM_PERFCTR_UCHE_5_HI"/>
1249	<reg32 offset="0x0414" name="RBBM_PERFCTR_UCHE_6_LO"/>
1250	<reg32 offset="0x0415" name="RBBM_PERFCTR_UCHE_6_HI"/>
1251	<reg32 offset="0x0416" name="RBBM_PERFCTR_UCHE_7_LO"/>
1252	<reg32 offset="0x0417" name="RBBM_PERFCTR_UCHE_7_HI"/>
1253	<reg32 offset="0x0418" name="RBBM_PERFCTR_TP_0_LO"/>
1254	<reg32 offset="0x0419" name="RBBM_PERFCTR_TP_0_HI"/>
1255	<reg32 offset="0x041a" name="RBBM_PERFCTR_TP_1_LO"/>
1256	<reg32 offset="0x041b" name="RBBM_PERFCTR_TP_1_HI"/>
1257	<reg32 offset="0x041c" name="RBBM_PERFCTR_TP_2_LO"/>
1258	<reg32 offset="0x041d" name="RBBM_PERFCTR_TP_2_HI"/>
1259	<reg32 offset="0x041e" name="RBBM_PERFCTR_TP_3_LO"/>
1260	<reg32 offset="0x041f" name="RBBM_PERFCTR_TP_3_HI"/>
1261	<reg32 offset="0x0420" name="RBBM_PERFCTR_TP_4_LO"/>
1262	<reg32 offset="0x0421" name="RBBM_PERFCTR_TP_4_HI"/>
1263	<reg32 offset="0x0422" name="RBBM_PERFCTR_TP_5_LO"/>
1264	<reg32 offset="0x0423" name="RBBM_PERFCTR_TP_5_HI"/>
1265	<reg32 offset="0x0424" name="RBBM_PERFCTR_TP_6_LO"/>
1266	<reg32 offset="0x0425" name="RBBM_PERFCTR_TP_6_HI"/>
1267	<reg32 offset="0x0426" name="RBBM_PERFCTR_TP_7_LO"/>
1268	<reg32 offset="0x0427" name="RBBM_PERFCTR_TP_7_HI"/>
1269	<reg32 offset="0x0428" name="RBBM_PERFCTR_SP_0_LO"/>
1270	<reg32 offset="0x0429" name="RBBM_PERFCTR_SP_0_HI"/>
1271	<reg32 offset="0x042a" name="RBBM_PERFCTR_SP_1_LO"/>
1272	<reg32 offset="0x042b" name="RBBM_PERFCTR_SP_1_HI"/>
1273	<reg32 offset="0x042c" name="RBBM_PERFCTR_SP_2_LO"/>
1274	<reg32 offset="0x042d" name="RBBM_PERFCTR_SP_2_HI"/>
1275	<reg32 offset="0x042e" name="RBBM_PERFCTR_SP_3_LO"/>
1276	<reg32 offset="0x042f" name="RBBM_PERFCTR_SP_3_HI"/>
1277	<reg32 offset="0x0430" name="RBBM_PERFCTR_SP_4_LO"/>
1278	<reg32 offset="0x0431" name="RBBM_PERFCTR_SP_4_HI"/>
1279	<reg32 offset="0x0432" name="RBBM_PERFCTR_SP_5_LO"/>
1280	<reg32 offset="0x0433" name="RBBM_PERFCTR_SP_5_HI"/>
1281	<reg32 offset="0x0434" name="RBBM_PERFCTR_SP_6_LO"/>
1282	<reg32 offset="0x0435" name="RBBM_PERFCTR_SP_6_HI"/>
1283	<reg32 offset="0x0436" name="RBBM_PERFCTR_SP_7_LO"/>
1284	<reg32 offset="0x0437" name="RBBM_PERFCTR_SP_7_HI"/>
1285	<reg32 offset="0x0438" name="RBBM_PERFCTR_SP_8_LO"/>
1286	<reg32 offset="0x0439" name="RBBM_PERFCTR_SP_8_HI"/>
1287	<reg32 offset="0x043a" name="RBBM_PERFCTR_SP_9_LO"/>
1288	<reg32 offset="0x043b" name="RBBM_PERFCTR_SP_9_HI"/>
1289	<reg32 offset="0x043c" name="RBBM_PERFCTR_SP_10_LO"/>
1290	<reg32 offset="0x043d" name="RBBM_PERFCTR_SP_10_HI"/>
1291	<reg32 offset="0x043e" name="RBBM_PERFCTR_SP_11_LO"/>
1292	<reg32 offset="0x043f" name="RBBM_PERFCTR_SP_11_HI"/>
1293	<reg32 offset="0x0440" name="RBBM_PERFCTR_RB_0_LO"/>
1294	<reg32 offset="0x0441" name="RBBM_PERFCTR_RB_0_HI"/>
1295	<reg32 offset="0x0442" name="RBBM_PERFCTR_RB_1_LO"/>
1296	<reg32 offset="0x0443" name="RBBM_PERFCTR_RB_1_HI"/>
1297	<reg32 offset="0x0444" name="RBBM_PERFCTR_RB_2_LO"/>
1298	<reg32 offset="0x0445" name="RBBM_PERFCTR_RB_2_HI"/>
1299	<reg32 offset="0x0446" name="RBBM_PERFCTR_RB_3_LO"/>
1300	<reg32 offset="0x0447" name="RBBM_PERFCTR_RB_3_HI"/>
1301	<reg32 offset="0x0448" name="RBBM_PERFCTR_RB_4_LO"/>
1302	<reg32 offset="0x0449" name="RBBM_PERFCTR_RB_4_HI"/>
1303	<reg32 offset="0x044a" name="RBBM_PERFCTR_RB_5_LO"/>
1304	<reg32 offset="0x044b" name="RBBM_PERFCTR_RB_5_HI"/>
1305	<reg32 offset="0x044c" name="RBBM_PERFCTR_RB_6_LO"/>
1306	<reg32 offset="0x044d" name="RBBM_PERFCTR_RB_6_HI"/>
1307	<reg32 offset="0x044e" name="RBBM_PERFCTR_RB_7_LO"/>
1308	<reg32 offset="0x044f" name="RBBM_PERFCTR_RB_7_HI"/>
1309	<reg32 offset="0x0450" name="RBBM_PERFCTR_VSC_0_LO"/>
1310	<reg32 offset="0x0451" name="RBBM_PERFCTR_VSC_0_HI"/>
1311	<reg32 offset="0x0452" name="RBBM_PERFCTR_VSC_1_LO"/>
1312	<reg32 offset="0x0453" name="RBBM_PERFCTR_VSC_1_HI"/>
1313	<reg32 offset="0x0454" name="RBBM_PERFCTR_LRZ_0_LO"/>
1314	<reg32 offset="0x0455" name="RBBM_PERFCTR_LRZ_0_HI"/>
1315	<reg32 offset="0x0456" name="RBBM_PERFCTR_LRZ_1_LO"/>
1316	<reg32 offset="0x0457" name="RBBM_PERFCTR_LRZ_1_HI"/>
1317	<reg32 offset="0x0458" name="RBBM_PERFCTR_LRZ_2_LO"/>
1318	<reg32 offset="0x0459" name="RBBM_PERFCTR_LRZ_2_HI"/>
1319	<reg32 offset="0x045a" name="RBBM_PERFCTR_LRZ_3_LO"/>
1320	<reg32 offset="0x045b" name="RBBM_PERFCTR_LRZ_3_HI"/>
1321	<reg32 offset="0x045c" name="RBBM_PERFCTR_CMP_0_LO"/>
1322	<reg32 offset="0x045d" name="RBBM_PERFCTR_CMP_0_HI"/>
1323	<reg32 offset="0x045e" name="RBBM_PERFCTR_CMP_1_LO"/>
1324	<reg32 offset="0x045f" name="RBBM_PERFCTR_CMP_1_HI"/>
1325	<reg32 offset="0x0460" name="RBBM_PERFCTR_CMP_2_LO"/>
1326	<reg32 offset="0x0461" name="RBBM_PERFCTR_CMP_2_HI"/>
1327	<reg32 offset="0x0462" name="RBBM_PERFCTR_CMP_3_LO"/>
1328	<reg32 offset="0x0463" name="RBBM_PERFCTR_CMP_3_HI"/>
1329	<reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0" type="a5xx_rbbm_perfcounter_select"/>
1330	<reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1" type="a5xx_rbbm_perfcounter_select"/>
1331	<reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2" type="a5xx_rbbm_perfcounter_select"/>
1332	<reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3" type="a5xx_rbbm_perfcounter_select"/>
1333	<reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/>
1334	<reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/>
1335	<reg32 offset="0x04f5" name="RBBM_STATUS">
1336		<bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" />
1337		<bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" />
1338		<bitfield high="29" low="29" name="HLSQ_BUSY" />
1339		<bitfield high="28" low="28" name="VSC_BUSY" />
1340		<bitfield high="27" low="27" name="TPL1_BUSY" />
1341		<bitfield high="26" low="26" name="SP_BUSY" />
1342		<bitfield high="25" low="25" name="UCHE_BUSY" />
1343		<bitfield high="24" low="24" name="VPC_BUSY" />
1344		<bitfield high="23" low="23" name="VFDP_BUSY" />
1345		<bitfield high="22" low="22" name="VFD_BUSY" />
1346		<bitfield high="21" low="21" name="TESS_BUSY" />
1347		<bitfield high="20" low="20" name="PC_VSD_BUSY" />
1348		<bitfield high="19" low="19" name="PC_DCALL_BUSY" />
1349		<bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" />
1350		<bitfield high="17" low="17" name="DCOM_BUSY" />
1351		<bitfield high="16" low="16" name="COM_BUSY" />
1352		<bitfield high="15" low="15" name="LRZ_BUZY" />
1353		<bitfield high="14" low="14" name="A2D_DSP_BUSY" />
1354		<bitfield high="13" low="13" name="CCUFCHE_BUSY" />
1355		<bitfield high="12" low="12" name="RB_BUSY" />
1356		<bitfield high="11" low="11" name="RAS_BUSY" />
1357		<bitfield high="10" low="10" name="TSE_BUSY" />
1358		<bitfield high="9" low="9" name="VBIF_BUSY" />
1359		<bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" />
1360		<bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" />
1361		<bitfield high="6" low="6" name="CP_BUSY" />
1362		<bitfield high="5" low="5" name="GPMU_MASTER_BUSY" />
1363		<bitfield high="4" low="4" name="CP_CRASH_BUSY" />
1364		<bitfield high="3" low="3" name="CP_ETS_BUSY" />
1365		<bitfield high="2" low="2" name="CP_PFP_BUSY" />
1366		<bitfield high="1" low="1" name="CP_ME_BUSY" />
1367		<bitfield high="0" low="0" name="HI_BUSY" />
1368	</reg32>
1369	<reg32 offset="0x0530" name="RBBM_STATUS3"/>
1370	<reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/>
1371	<reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/>
1372	<reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
1373	<reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/>
1374	<reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/>
1375	<reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/>
1376	<reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/>
1377	<reg32 offset="0x0466" name="RBBM_PERFCTR_LOAD_CMD1"/>
1378	<reg32 offset="0x0467" name="RBBM_PERFCTR_LOAD_CMD2"/>
1379	<reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/>
1380	<reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1381	<reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1382	<reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1383	<reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/>
1384	<reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/>
1385	<reg32 offset="0x0505" name="RBBM_CFG_DBGBUS_OVER"/>
1386	<reg32 offset="0x0506" name="RBBM_CFG_DBGBUS_COUNT0"/>
1387	<reg32 offset="0x0507" name="RBBM_CFG_DBGBUS_COUNT1"/>
1388	<reg32 offset="0x0508" name="RBBM_CFG_DBGBUS_COUNT2"/>
1389	<reg32 offset="0x0509" name="RBBM_CFG_DBGBUS_COUNT3"/>
1390	<reg32 offset="0x050a" name="RBBM_CFG_DBGBUS_COUNT4"/>
1391	<reg32 offset="0x050b" name="RBBM_CFG_DBGBUS_COUNT5"/>
1392	<reg32 offset="0x050c" name="RBBM_CFG_DBGBUS_TRACE_ADDR"/>
1393	<reg32 offset="0x050d" name="RBBM_CFG_DBGBUS_TRACE_BUF0"/>
1394	<reg32 offset="0x050e" name="RBBM_CFG_DBGBUS_TRACE_BUF1"/>
1395	<reg32 offset="0x050f" name="RBBM_CFG_DBGBUS_TRACE_BUF2"/>
1396	<reg32 offset="0x0510" name="RBBM_CFG_DBGBUS_TRACE_BUF3"/>
1397	<reg32 offset="0x0511" name="RBBM_CFG_DBGBUS_TRACE_BUF4"/>
1398	<reg32 offset="0x0512" name="RBBM_CFG_DBGBUS_MISR0"/>
1399	<reg32 offset="0x0513" name="RBBM_CFG_DBGBUS_MISR1"/>
1400	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1401	<reg32 offset="0xf000" name="RBBM_SECVID_TRUST_CONFIG"/>
1402	<reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/>
1403	<reg32 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1404	<reg32 offset="0xf801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1405	<reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1406	<reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/>
1407	<reg32 offset="0xf804" name="RBBM_SECVID_TSB_COMP_STATUS_LO"/>
1408	<reg32 offset="0xf805" name="RBBM_SECVID_TSB_COMP_STATUS_HI"/>
1409	<reg32 offset="0xf806" name="RBBM_SECVID_TSB_UCHE_STATUS_LO"/>
1410	<reg32 offset="0xf807" name="RBBM_SECVID_TSB_UCHE_STATUS_HI"/>
1411	<reg32 offset="0xf810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1412
1413	<!-- VSC registers -->
1414	<reg32 offset="0x0bc2" name="VSC_BIN_SIZE">
1415		<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1416		<bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
1417		<!-- b17 maybe BYPASS like RB_CNTL, but reg not written for bypass -->
1418	</reg32>
1419	<reg32 offset="0x0bc3" name="VSC_SIZE_ADDRESS_LO"/>
1420	<reg32 offset="0x0bc4" name="VSC_SIZE_ADDRESS_HI"/>
1421	<reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? -->
1422	<reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? -->
1423	<array offset="0x0bd0" name="VSC_PIPE_CONFIG" stride="1" length="16">
1424		<reg32 offset="0x0" name="REG">
1425			<doc>
1426				Configures the mapping between VSC_PIPE buffer and
1427				bin, X/Y specify the bin index in the horiz/vert
1428				direction (0,0 is upper left, 0,1 is leftmost bin
1429				on second row, and so on).  W/H specify the number
1430				of bins assigned to this VSC_PIPE in the horiz/vert
1431				dimension.
1432			</doc>
1433			<bitfield name="X" low="0" high="9" type="uint"/>
1434			<bitfield name="Y" low="10" high="19" type="uint"/>
1435			<bitfield name="W" low="20" high="23" type="uint"/>
1436			<bitfield name="H" low="24" high="27" type="uint"/>
1437		</reg32>
1438	</array>
1439	<array offset="0x0be0" name="VSC_PIPE_DATA_ADDRESS" stride="2" length="16">
1440		<reg32 offset="0x0" name="LO"/>
1441		<reg32 offset="0x1" name="HI"/>
1442	</array>
1443	<array offset="0x0c00" name="VSC_PIPE_DATA_LENGTH" stride="1" length="16">
1444		<reg32 offset="0x0" name="REG"/>
1445	</array>
1446	<reg32 offset="0x0c60" name="VSC_PERFCTR_VSC_SEL_0" type="a5xx_vsc_perfcounter_select"/>
1447	<reg32 offset="0x0c61" name="VSC_PERFCTR_VSC_SEL_1" type="a5xx_vsc_perfcounter_select"/>
1448
1449	<!-- used for some blits?? -->
1450	<reg32 offset="0x0cdd" name="VSC_RESOLVE_CNTL" type="adreno_reg_xy"/>
1451
1452	<!-- GRAS registers -->
1453	<reg32 offset="0x0c81" name="GRAS_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1454	<reg32 offset="0x0c90" name="GRAS_PERFCTR_TSE_SEL_0" type="a5xx_tse_perfcounter_select"/>
1455	<reg32 offset="0x0c91" name="GRAS_PERFCTR_TSE_SEL_1" type="a5xx_tse_perfcounter_select"/>
1456	<reg32 offset="0x0c92" name="GRAS_PERFCTR_TSE_SEL_2" type="a5xx_tse_perfcounter_select"/>
1457	<reg32 offset="0x0c93" name="GRAS_PERFCTR_TSE_SEL_3" type="a5xx_tse_perfcounter_select"/>
1458	<reg32 offset="0x0c94" name="GRAS_PERFCTR_RAS_SEL_0" type="a5xx_ras_perfcounter_select"/>
1459	<reg32 offset="0x0c95" name="GRAS_PERFCTR_RAS_SEL_1" type="a5xx_ras_perfcounter_select"/>
1460	<reg32 offset="0x0c96" name="GRAS_PERFCTR_RAS_SEL_2" type="a5xx_ras_perfcounter_select"/>
1461	<reg32 offset="0x0c97" name="GRAS_PERFCTR_RAS_SEL_3" type="a5xx_ras_perfcounter_select"/>
1462	<reg32 offset="0x0c98" name="GRAS_PERFCTR_LRZ_SEL_0" type="a5xx_lrz_perfcounter_select"/>
1463	<reg32 offset="0x0c99" name="GRAS_PERFCTR_LRZ_SEL_1" type="a5xx_lrz_perfcounter_select"/>
1464	<reg32 offset="0x0c9a" name="GRAS_PERFCTR_LRZ_SEL_2" type="a5xx_lrz_perfcounter_select"/>
1465	<reg32 offset="0x0c9b" name="GRAS_PERFCTR_LRZ_SEL_3" type="a5xx_lrz_perfcounter_select"/>
1466
1467	<reg32 offset="0x0cc4" name="RB_DBG_ECO_CNTL"/> <!-- always 00100000? -->
1468	<reg32 offset="0x0cc5" name="RB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1469	<reg32 offset="0x0cc6" name="RB_MODE_CNTL"/> <!-- always 00000044? -->
1470	<reg32 offset="0x0cc7" name="RB_CCU_CNTL"/> <!-- always b0056080 or 10000000? -->
1471	<reg32 offset="0x0cd0" name="RB_PERFCTR_RB_SEL_0" type="a5xx_rb_perfcounter_select"/>
1472	<reg32 offset="0x0cd1" name="RB_PERFCTR_RB_SEL_1" type="a5xx_rb_perfcounter_select"/>
1473	<reg32 offset="0x0cd2" name="RB_PERFCTR_RB_SEL_2" type="a5xx_rb_perfcounter_select"/>
1474	<reg32 offset="0x0cd3" name="RB_PERFCTR_RB_SEL_3" type="a5xx_rb_perfcounter_select"/>
1475	<reg32 offset="0x0cd4" name="RB_PERFCTR_RB_SEL_4" type="a5xx_rb_perfcounter_select"/>
1476	<reg32 offset="0x0cd5" name="RB_PERFCTR_RB_SEL_5" type="a5xx_rb_perfcounter_select"/>
1477	<reg32 offset="0x0cd6" name="RB_PERFCTR_RB_SEL_6" type="a5xx_rb_perfcounter_select"/>
1478	<reg32 offset="0x0cd7" name="RB_PERFCTR_RB_SEL_7" type="a5xx_rb_perfcounter_select"/>
1479	<reg32 offset="0x0cd8" name="RB_PERFCTR_CCU_SEL_0" type="a5xx_ccu_perfcounter_select"/>
1480	<reg32 offset="0x0cd9" name="RB_PERFCTR_CCU_SEL_1" type="a5xx_ccu_perfcounter_select"/>
1481	<reg32 offset="0x0cda" name="RB_PERFCTR_CCU_SEL_2" type="a5xx_ccu_perfcounter_select"/>
1482	<reg32 offset="0x0cdb" name="RB_PERFCTR_CCU_SEL_3" type="a5xx_ccu_perfcounter_select"/>
1483	<reg32 offset="0x0ce0" name="RB_POWERCTR_RB_SEL_0"/>
1484	<reg32 offset="0x0ce1" name="RB_POWERCTR_RB_SEL_1"/>
1485	<reg32 offset="0x0ce2" name="RB_POWERCTR_RB_SEL_2"/>
1486	<reg32 offset="0x0ce3" name="RB_POWERCTR_RB_SEL_3"/>
1487	<reg32 offset="0x0ce4" name="RB_POWERCTR_CCU_SEL_0"/>
1488	<reg32 offset="0x0ce5" name="RB_POWERCTR_CCU_SEL_1"/>
1489	<reg32 offset="0x0cec" name="RB_PERFCTR_CMP_SEL_0" type="a5xx_cmp_perfcounter_select"/>
1490	<reg32 offset="0x0ced" name="RB_PERFCTR_CMP_SEL_1" type="a5xx_cmp_perfcounter_select"/>
1491	<reg32 offset="0x0cee" name="RB_PERFCTR_CMP_SEL_2" type="a5xx_cmp_perfcounter_select"/>
1492	<reg32 offset="0x0cef" name="RB_PERFCTR_CMP_SEL_3" type="a5xx_cmp_perfcounter_select"/>
1493
1494	<reg32 offset="0x0d00" name="PC_DBG_ECO_CNTL">
1495		<bitfield name="TWOPASSUSEWFI" pos="8" type="boolean"/>
1496	</reg32>
1497	<reg32 offset="0x0d01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1498	<reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? -->
1499	<reg32 offset="0x0d04" name="PC_INDEX_BUF_LO"/>
1500	<reg32 offset="0x0d05" name="PC_INDEX_BUF_HI"/>
1501	<reg32 offset="0x0d06" name="PC_START_INDEX"/>
1502	<reg32 offset="0x0d07" name="PC_MAX_INDEX"/>
1503	<reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR_LO"/>
1504	<reg32 offset="0x0d09" name="PC_TESSFACTOR_ADDR_HI"/>
1505	<reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a5xx_pc_perfcounter_select"/>
1506	<reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a5xx_pc_perfcounter_select"/>
1507	<reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a5xx_pc_perfcounter_select"/>
1508	<reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a5xx_pc_perfcounter_select"/>
1509	<reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a5xx_pc_perfcounter_select"/>
1510	<reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a5xx_pc_perfcounter_select"/>
1511	<reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a5xx_pc_perfcounter_select"/>
1512	<reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a5xx_pc_perfcounter_select"/>
1513
1514	<reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD_0"/>
1515	<reg32 offset="0x0e01" name="HLSQ_TIMEOUT_THRESHOLD_1"/>
1516	<reg32 offset="0x0e04" name="HLSQ_DBG_ECO_CNTL"/>
1517	<reg32 offset="0x0e05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1518	<reg32 offset="0x0e06" name="HLSQ_MODE_CNTL"/> <!-- always 00000001? -->
1519	<reg32 offset="0x0e10" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a5xx_hlsq_perfcounter_select"/>
1520	<reg32 offset="0x0e11" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a5xx_hlsq_perfcounter_select"/>
1521	<reg32 offset="0x0e12" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a5xx_hlsq_perfcounter_select"/>
1522	<reg32 offset="0x0e13" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a5xx_hlsq_perfcounter_select"/>
1523	<reg32 offset="0x0e14" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a5xx_hlsq_perfcounter_select"/>
1524	<reg32 offset="0x0e15" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a5xx_hlsq_perfcounter_select"/>
1525	<reg32 offset="0x0e16" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a5xx_hlsq_perfcounter_select"/>
1526	<reg32 offset="0x0e17" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a5xx_hlsq_perfcounter_select"/>
1527	<reg32 offset="0x0f08" name="HLSQ_SPTP_RDSEL"/>
1528	<reg32 offset="0xbc00" name="HLSQ_DBG_READ_SEL"/>
1529	<reg32 offset="0xa000" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1530
1531	<reg32 offset="0x0e41" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1532	<reg32 offset="0x0e42" name="VFD_MODE_CNTL"/> <!-- always 00000000? -->
1533	<reg32 offset="0x0e50" name="VFD_PERFCTR_VFD_SEL_0" type="a5xx_vfd_perfcounter_select"/>
1534	<reg32 offset="0x0e51" name="VFD_PERFCTR_VFD_SEL_1" type="a5xx_vfd_perfcounter_select"/>
1535	<reg32 offset="0x0e52" name="VFD_PERFCTR_VFD_SEL_2" type="a5xx_vfd_perfcounter_select"/>
1536	<reg32 offset="0x0e53" name="VFD_PERFCTR_VFD_SEL_3" type="a5xx_vfd_perfcounter_select"/>
1537	<reg32 offset="0x0e54" name="VFD_PERFCTR_VFD_SEL_4" type="a5xx_vfd_perfcounter_select"/>
1538	<reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/>
1539	<reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/>
1540	<reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/>
1541	<reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL">
1542		<bitfield name="ALLFLATOPTDIS" pos="10" type="boolean"/>
1543	</reg32>
1544	<reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1545	<reg32 offset="0x0e62" name="VPC_MODE_CNTL">
1546		<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1547	</reg32>
1548	<reg32 offset="0x0e64" name="VPC_PERFCTR_VPC_SEL_0" type="a5xx_vpc_perfcounter_select"/>
1549	<reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_1" type="a5xx_vpc_perfcounter_select"/>
1550	<reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_2" type="a5xx_vpc_perfcounter_select"/>
1551	<reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/>
1552
1553	<reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1554	<reg32 offset="0x0e81" name="UCHE_MODE_CNTL"/>
1555	<reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
1556	<reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
1557	<reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>
1558	<reg32 offset="0x0e89" name="UCHE_TRAP_BASE_LO"/>
1559	<reg32 offset="0x0e8a" name="UCHE_TRAP_BASE_HI"/>
1560	<reg32 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN_LO"/>
1561	<reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/>
1562	<reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/>
1563	<reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/>
1564	<reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/>
1565	<reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/>
1566	<reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/>
1567	<reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/>
1568	<reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/>
1569	<reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/>
1570	<reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/>
1571	<reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/>
1572	<reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0" type="a5xx_uche_perfcounter_select"/>
1573	<reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1" type="a5xx_uche_perfcounter_select"/>
1574	<reg32 offset="0x0ea2" name="UCHE_PERFCTR_UCHE_SEL_2" type="a5xx_uche_perfcounter_select"/>
1575	<reg32 offset="0x0ea3" name="UCHE_PERFCTR_UCHE_SEL_3" type="a5xx_uche_perfcounter_select"/>
1576	<reg32 offset="0x0ea4" name="UCHE_PERFCTR_UCHE_SEL_4" type="a5xx_uche_perfcounter_select"/>
1577	<reg32 offset="0x0ea5" name="UCHE_PERFCTR_UCHE_SEL_5" type="a5xx_uche_perfcounter_select"/>
1578	<reg32 offset="0x0ea6" name="UCHE_PERFCTR_UCHE_SEL_6" type="a5xx_uche_perfcounter_select"/>
1579	<reg32 offset="0x0ea7" name="UCHE_PERFCTR_UCHE_SEL_7" type="a5xx_uche_perfcounter_select"/>
1580	<reg32 offset="0x0ea8" name="UCHE_POWERCTR_UCHE_SEL_0"/>
1581	<reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/>
1582	<reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/>
1583	<reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/>
1584	<reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/>
1585	<reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/>
1586
1587	<reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/>
1588	<reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1589	<reg32 offset="0x0ec2" name="SP_MODE_CNTL"/> <!-- always 0000001e? -->
1590	<reg32 offset="0x0ed0" name="SP_PERFCTR_SP_SEL_0"  type="a5xx_sp_perfcounter_select"/>
1591	<reg32 offset="0x0ed1" name="SP_PERFCTR_SP_SEL_1"  type="a5xx_sp_perfcounter_select"/>
1592	<reg32 offset="0x0ed2" name="SP_PERFCTR_SP_SEL_2"  type="a5xx_sp_perfcounter_select"/>
1593	<reg32 offset="0x0ed3" name="SP_PERFCTR_SP_SEL_3"  type="a5xx_sp_perfcounter_select"/>
1594	<reg32 offset="0x0ed4" name="SP_PERFCTR_SP_SEL_4"  type="a5xx_sp_perfcounter_select"/>
1595	<reg32 offset="0x0ed5" name="SP_PERFCTR_SP_SEL_5"  type="a5xx_sp_perfcounter_select"/>
1596	<reg32 offset="0x0ed6" name="SP_PERFCTR_SP_SEL_6"  type="a5xx_sp_perfcounter_select"/>
1597	<reg32 offset="0x0ed7" name="SP_PERFCTR_SP_SEL_7"  type="a5xx_sp_perfcounter_select"/>
1598	<reg32 offset="0x0ed8" name="SP_PERFCTR_SP_SEL_8"  type="a5xx_sp_perfcounter_select"/>
1599	<reg32 offset="0x0ed9" name="SP_PERFCTR_SP_SEL_9"  type="a5xx_sp_perfcounter_select"/>
1600	<reg32 offset="0x0eda" name="SP_PERFCTR_SP_SEL_10" type="a5xx_sp_perfcounter_select"/>
1601	<reg32 offset="0x0edb" name="SP_PERFCTR_SP_SEL_11" type="a5xx_sp_perfcounter_select"/>
1602	<reg32 offset="0x0edc" name="SP_POWERCTR_SP_SEL_0"/>
1603	<reg32 offset="0x0edd" name="SP_POWERCTR_SP_SEL_1"/>
1604	<reg32 offset="0x0ede" name="SP_POWERCTR_SP_SEL_2"/>
1605	<reg32 offset="0x0edf" name="SP_POWERCTR_SP_SEL_3"/>
1606
1607	<reg32 offset="0x0f01" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1608	<reg32 offset="0x0f02" name="TPL1_MODE_CNTL"/> <!-- always 00000544? -->
1609	<reg32 offset="0x0f10" name="TPL1_PERFCTR_TP_SEL_0" type="a5xx_tp_perfcounter_select"/>
1610	<reg32 offset="0x0f11" name="TPL1_PERFCTR_TP_SEL_1" type="a5xx_tp_perfcounter_select"/>
1611	<reg32 offset="0x0f12" name="TPL1_PERFCTR_TP_SEL_2" type="a5xx_tp_perfcounter_select"/>
1612	<reg32 offset="0x0f13" name="TPL1_PERFCTR_TP_SEL_3" type="a5xx_tp_perfcounter_select"/>
1613	<reg32 offset="0x0f14" name="TPL1_PERFCTR_TP_SEL_4" type="a5xx_tp_perfcounter_select"/>
1614	<reg32 offset="0x0f15" name="TPL1_PERFCTR_TP_SEL_5" type="a5xx_tp_perfcounter_select"/>
1615	<reg32 offset="0x0f16" name="TPL1_PERFCTR_TP_SEL_6" type="a5xx_tp_perfcounter_select"/>
1616	<reg32 offset="0x0f17" name="TPL1_PERFCTR_TP_SEL_7" type="a5xx_tp_perfcounter_select"/>
1617	<reg32 offset="0x0f18" name="TPL1_POWERCTR_TP_SEL_0"/>
1618	<reg32 offset="0x0f19" name="TPL1_POWERCTR_TP_SEL_1"/>
1619	<reg32 offset="0x0f1a" name="TPL1_POWERCTR_TP_SEL_2"/>
1620	<reg32 offset="0x0f1b" name="TPL1_POWERCTR_TP_SEL_3"/>
1621
1622	<reg32 offset="0x3000" name="VBIF_VERSION"/>
1623	<reg32 offset="0x3001" name="VBIF_CLKON"/>
1624<!--
1625#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK   0x1
1626#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT  0x1
1627 -->
1628	<reg32 offset="0x3028" name="VBIF_ABIT_SORT"/>
1629	<reg32 offset="0x3029" name="VBIF_ABIT_SORT_CONF"/>
1630	<reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
1631	<reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
1632	<reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
1633	<reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
1634	<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1635<!--
1636#define A5XX_VBIF_XIN_HALT_CTRL0_MASK	   0xF
1637#define A510_VBIF_XIN_HALT_CTRL0_MASK	   0x7
1638 -->
1639	<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1640	<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1641<!--
1642#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK    0x1
1643#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT   0x0
1644 -->
1645	<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1646	<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/>
1647<!--
1648#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK  0xF
1649#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT 0x0
1650 -->
1651	<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1652	<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/>
1653<!--
1654#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK     0xF
1655#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT    0x0
1656 -->
1657	<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1658	<reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
1659	<reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
1660	<reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
1661	<reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
1662	<reg32 offset="0x30c8" name="VBIF_PERF_CNT_CLR0"/>
1663	<reg32 offset="0x30c9" name="VBIF_PERF_CNT_CLR1"/>
1664	<reg32 offset="0x30ca" name="VBIF_PERF_CNT_CLR2"/>
1665	<reg32 offset="0x30cb" name="VBIF_PERF_CNT_CLR3"/>
1666	<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a5xx_vbif_perfcounter_select"/>
1667	<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a5xx_vbif_perfcounter_select"/>
1668	<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a5xx_vbif_perfcounter_select"/>
1669	<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a5xx_vbif_perfcounter_select"/>
1670	<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1671	<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1672	<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1673	<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1674	<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1675	<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1676	<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1677	<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1678	<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1679	<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1680	<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1681	<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1682	<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1683	<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1684	<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1685	<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1686	<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1687
1688	<reg32 offset="0x8800" name="GPMU_INST_RAM_BASE"/>
1689	<reg32 offset="0x9800" name="GPMU_DATA_RAM_BASE"/>
1690	<reg32 offset="0xa881" name="GPMU_SP_POWER_CNTL"/>
1691	<reg32 offset="0xa886" name="GPMU_RBCCU_CLOCK_CNTL"/>
1692	<reg32 offset="0xa887" name="GPMU_RBCCU_POWER_CNTL"/>
1693	<reg32 offset="0xa88b" name="GPMU_SP_PWR_CLK_STATUS">
1694		<bitfield name="PWR_ON" pos="20" type="boolean"/>
1695	</reg32>
1696	<reg32 offset="0xa88d" name="GPMU_RBCCU_PWR_CLK_STATUS">
1697		<bitfield name="PWR_ON" pos="20" type="boolean"/>
1698	</reg32>
1699	<reg32 offset="0xa891" name="GPMU_PWR_COL_STAGGER_DELAY"/>
1700	<reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/>
1701	<reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/>
1702	<reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/>
1703	<reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/>
1704	<reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/>
1705	<reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/>
1706	<reg32 offset="0xa8e0" name="GPMU_GENERAL_0"/>
1707	<reg32 offset="0xa8e1" name="GPMU_GENERAL_1"/>
1708
1709<!--
1710/* COUNTABLE FOR SP PERFCOUNTER */
1711#define A5XX_SP_ALU_ACTIVE_CYCLES          0x1
1712#define A5XX_SP0_ICL1_MISSES               0x35
1713#define A5XX_SP_FS_CFLOW_INSTRUCTIONS      0x27
1714
1715/* COUNTABLE FOR TSE PERFCOUNTER */
1716#define A5XX_TSE_INPUT_PRIM_NUM            0x6
1717 -->
1718	<reg32 offset="0xa840" name="SP_POWER_COUNTER_0_LO"/>
1719	<reg32 offset="0xa841" name="SP_POWER_COUNTER_0_HI"/>
1720	<reg32 offset="0xa842" name="SP_POWER_COUNTER_1_LO"/>
1721	<reg32 offset="0xa843" name="SP_POWER_COUNTER_1_HI"/>
1722	<reg32 offset="0xa844" name="SP_POWER_COUNTER_2_LO"/>
1723	<reg32 offset="0xa845" name="SP_POWER_COUNTER_2_HI"/>
1724	<reg32 offset="0xa846" name="SP_POWER_COUNTER_3_LO"/>
1725	<reg32 offset="0xa847" name="SP_POWER_COUNTER_3_HI"/>
1726	<reg32 offset="0xa848" name="TP_POWER_COUNTER_0_LO"/>
1727	<reg32 offset="0xa849" name="TP_POWER_COUNTER_0_HI"/>
1728	<reg32 offset="0xa84a" name="TP_POWER_COUNTER_1_LO"/>
1729	<reg32 offset="0xa84b" name="TP_POWER_COUNTER_1_HI"/>
1730	<reg32 offset="0xa84c" name="TP_POWER_COUNTER_2_LO"/>
1731	<reg32 offset="0xa84d" name="TP_POWER_COUNTER_2_HI"/>
1732	<reg32 offset="0xa84e" name="TP_POWER_COUNTER_3_LO"/>
1733	<reg32 offset="0xa84f" name="TP_POWER_COUNTER_3_HI"/>
1734	<reg32 offset="0xa850" name="RB_POWER_COUNTER_0_LO"/>
1735	<reg32 offset="0xa851" name="RB_POWER_COUNTER_0_HI"/>
1736	<reg32 offset="0xa852" name="RB_POWER_COUNTER_1_LO"/>
1737	<reg32 offset="0xa853" name="RB_POWER_COUNTER_1_HI"/>
1738	<reg32 offset="0xa854" name="RB_POWER_COUNTER_2_LO"/>
1739	<reg32 offset="0xa855" name="RB_POWER_COUNTER_2_HI"/>
1740	<reg32 offset="0xa856" name="RB_POWER_COUNTER_3_LO"/>
1741	<reg32 offset="0xa857" name="RB_POWER_COUNTER_3_HI"/>
1742	<reg32 offset="0xa858" name="CCU_POWER_COUNTER_0_LO"/>
1743	<reg32 offset="0xa859" name="CCU_POWER_COUNTER_0_HI"/>
1744	<reg32 offset="0xa85a" name="CCU_POWER_COUNTER_1_LO"/>
1745	<reg32 offset="0xa85b" name="CCU_POWER_COUNTER_1_HI"/>
1746	<reg32 offset="0xa85c" name="UCHE_POWER_COUNTER_0_LO"/>
1747	<reg32 offset="0xa85d" name="UCHE_POWER_COUNTER_0_HI"/>
1748	<reg32 offset="0xa85e" name="UCHE_POWER_COUNTER_1_LO"/>
1749	<reg32 offset="0xa85f" name="UCHE_POWER_COUNTER_1_HI"/>
1750	<reg32 offset="0xa860" name="UCHE_POWER_COUNTER_2_LO"/>
1751	<reg32 offset="0xa861" name="UCHE_POWER_COUNTER_2_HI"/>
1752	<reg32 offset="0xa862" name="UCHE_POWER_COUNTER_3_LO"/>
1753	<reg32 offset="0xa863" name="UCHE_POWER_COUNTER_3_HI"/>
1754	<reg32 offset="0xa864" name="CP_POWER_COUNTER_0_LO"/>
1755	<reg32 offset="0xa865" name="CP_POWER_COUNTER_0_HI"/>
1756	<reg32 offset="0xa866" name="CP_POWER_COUNTER_1_LO"/>
1757	<reg32 offset="0xa867" name="CP_POWER_COUNTER_1_HI"/>
1758	<reg32 offset="0xa868" name="CP_POWER_COUNTER_2_LO"/>
1759	<reg32 offset="0xa869" name="CP_POWER_COUNTER_2_HI"/>
1760	<reg32 offset="0xa86a" name="CP_POWER_COUNTER_3_LO"/>
1761	<reg32 offset="0xa86b" name="CP_POWER_COUNTER_3_HI"/>
1762	<reg32 offset="0xa86c" name="GPMU_POWER_COUNTER_0_LO"/>
1763	<reg32 offset="0xa86d" name="GPMU_POWER_COUNTER_0_HI"/>
1764	<reg32 offset="0xa86e" name="GPMU_POWER_COUNTER_1_LO"/>
1765	<reg32 offset="0xa86f" name="GPMU_POWER_COUNTER_1_HI"/>
1766	<reg32 offset="0xa870" name="GPMU_POWER_COUNTER_2_LO"/>
1767	<reg32 offset="0xa871" name="GPMU_POWER_COUNTER_2_HI"/>
1768	<reg32 offset="0xa872" name="GPMU_POWER_COUNTER_3_LO"/>
1769	<reg32 offset="0xa873" name="GPMU_POWER_COUNTER_3_HI"/>
1770	<reg32 offset="0xa874" name="GPMU_POWER_COUNTER_4_LO"/>
1771	<reg32 offset="0xa875" name="GPMU_POWER_COUNTER_4_HI"/>
1772	<reg32 offset="0xa876" name="GPMU_POWER_COUNTER_5_LO"/>
1773	<reg32 offset="0xa877" name="GPMU_POWER_COUNTER_5_HI"/>
1774	<reg32 offset="0xa878" name="GPMU_POWER_COUNTER_ENABLE"/>
1775	<reg32 offset="0xa879" name="GPMU_ALWAYS_ON_COUNTER_LO"/>
1776	<reg32 offset="0xa87a" name="GPMU_ALWAYS_ON_COUNTER_HI"/>
1777	<reg32 offset="0xa87b" name="GPMU_ALWAYS_ON_COUNTER_RESET"/>
1778	<reg32 offset="0xa87c" name="GPMU_POWER_COUNTER_SELECT_0"/>
1779	<reg32 offset="0xa87d" name="GPMU_POWER_COUNTER_SELECT_1"/>
1780	<reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
1781	<reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/>
1782	<reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/>
1783	<reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/>
1784	<reg32 offset="0xac02" name="GPMU_TEMP_VAL"/>
1785	<reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/>
1786	<reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/>
1787	<reg32 offset="0xac06" name="GPMU_TEMP_THRESHOLD_INTR_EN_MASK"/>
1788	<reg32 offset="0xac40" name="GPMU_LEAKAGE_TEMP_COEFF_0_1"/>
1789	<reg32 offset="0xac41" name="GPMU_LEAKAGE_TEMP_COEFF_2_3"/>
1790	<reg32 offset="0xac42" name="GPMU_LEAKAGE_VTG_COEFF_0_1"/>
1791	<reg32 offset="0xac43" name="GPMU_LEAKAGE_VTG_COEFF_2_3"/>
1792	<reg32 offset="0xac46" name="GPMU_BASE_LEAKAGE"/>
1793	<reg32 offset="0xac60" name="GPMU_GPMU_VOLTAGE"/>
1794	<reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/>
1795	<reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/>
1796	<reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/>
1797	<reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/>
1798	<reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/>
1799	<reg32 offset="0xb80c" name="GDPM_CONFIG1"/>
1800	<reg32 offset="0xb80d" name="GDPM_CONFIG2"/>
1801	<reg32 offset="0xb80f" name="GDPM_INT_EN"/>
1802	<reg32 offset="0xb811" name="GDPM_INT_MASK"/>
1803	<reg32 offset="0xb9a0" name="GPMU_BEC_ENABLE"/>
1804	<reg32 offset="0xc41a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
1805	<reg32 offset="0xc41d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
1806	<reg32 offset="0xc41f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
1807	<reg32 offset="0xc421" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
1808	<reg32 offset="0xc520" name="GPU_CS_ENABLE_REG"/>
1809	<reg32 offset="0xc557" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
1810
1811
1812	<reg32 offset="0xe000" name="GRAS_CL_CNTL">
1813		<bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1814	</reg32>
1815	<reg32 offset="0xe001" name="UNKNOWN_E001"/> <!-- always 00000000? -->
1816	<reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? -->
1817	<reg32 offset="0xe005" name="GRAS_CNTL">
1818		<!-- see also RB_RENDER_CONTROL0 -->
1819		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1820		<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1821		<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1822		<!--
1823		bit 3 set when blob turns on WCOORD.. which also corresponds to
1824		register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
1825		shader does not use).. possibly providing wcoord in an alternate
1826		way??
1827		Also, when that happens, VARYING bits are turned on as well.
1828		 -->
1829		<bitfield name="SIZE" pos="3" type="boolean"/>
1830		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1831	</reg32>
1832	<reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1833		<bitfield name="HORZ" low="0" high="9" type="uint"/>
1834		<bitfield name="VERT" low="10" high="19" type="uint"/>
1835	</reg32>
1836	<reg32 offset="0xe010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1837	<reg32 offset="0xe011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1838	<reg32 offset="0xe012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1839	<reg32 offset="0xe013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1840	<reg32 offset="0xe014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1841	<reg32 offset="0xe015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1842	<reg32 offset="0xe090" name="GRAS_SU_CNTL">
1843		<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1844		<bitfield name="CULL_BACK" pos="1" type="boolean"/>
1845		<bitfield name="FRONT_CW" pos="2" type="boolean"/>
1846		<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1847		<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1848		<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1849		<!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1850	</reg32>
1851	<reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX">
1852		<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1853		<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1854	</reg32>
1855	<reg32 offset="0xe092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1856	<reg32 offset="0xe093" name="GRAS_SU_LAYERED"/>
1857	<reg32 offset="0xe094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1858		<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1859		<bitfield name="UNK1" pos="1" type="boolean"/>
1860	</reg32>
1861	<reg32 offset="0xe095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1862	<reg32 offset="0xe096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1863	<reg32 offset="0xe097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1864	<!-- duplicates RB_DEPTH_INFO0: -->
1865	<reg32 offset="0xe098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1866		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
1867	</reg32>
1868	<reg32 offset="0xe099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"/> <!-- always 00000000? -->
1869	<!--
1870	guessing about window/screen/extent, I think they can in the end be
1871	used interchangeably?
1872	 -->
1873	<reg32 offset="0xe0a0" name="GRAS_SC_CNTL">
1874		<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1875		<bitfield name="SAMPLES_PASSED" pos="15" type="boolean"/>
1876	</reg32>
1877	<!-- note, 0x4 for binning pass when frag writes z?? -->
1878	<reg32 offset="0xe0a1" name="GRAS_SC_BIN_CNTL"/> <!-- always 00000000? -->
1879	<reg32 offset="0xe0a2" name="GRAS_SC_RAS_MSAA_CNTL">
1880		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1881	</reg32>
1882	<reg32 offset="0xe0a3" name="GRAS_SC_DEST_MSAA_CNTL">
1883		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1884		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1885	</reg32>
1886	<reg32 offset="0xe0a4" name="GRAS_SC_SCREEN_SCISSOR_CNTL"/> <!-- always 00000000? -->
1887	<reg32 offset="0xe0aa" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1888	<reg32 offset="0xe0ab" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1889	<reg32 offset="0xe0ca" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1890	<reg32 offset="0xe0cb" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1891	<reg32 offset="0xe0ea" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1892	<reg32 offset="0xe0eb" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1893
1894	<doc>
1895		LRZ:  (Low Resolution Z ??)
1896		----
1897
1898		I think it serves two functions, early discard of primitives in binning
1899		pass without needing full resolution depth buffer, and also functions as
1900		a depth-prepass, used during the GMEM draws to discard primitives that
1901		would not be visible due to later draws.
1902
1903		The LRZ buffer always seems to be z16 format, regardless of actual
1904		depth buffer format.
1905
1906		Note that LRZ write should be disabled when blend/stencil/etc is enabled,
1907		since the occluded primitive can still contribute to final color value
1908		of a fragment.
1909
1910		Only enabled for GL_LESS/GL_LEQUAL/GL_GREATER/GL_GEQUAL?
1911	</doc>
1912	<reg32 offset="0xe100" name="GRAS_LRZ_CNTL">
1913		<bitfield name="ENABLE" pos="0" type="boolean"/>
1914		<doc>LRZ write also disabled for blend/etc.</doc>
1915		<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1916		<doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1917		<bitfield name="GREATER" pos="2" type="boolean"/>
1918		<!--
1919		b3 set sometimes, when depth buffer isn't cleared.. maybe it
1920		invalidates the LRZ buffer?  (Or just the covered positions?
1921		 -->
1922	</reg32>
1923	<reg32 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1924	<reg32 offset="0xe102" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1925	<!--
1926	lzr pitch is depth pitch (in pixels) / 8 (aligned to 32)..
1927	 -->
1928	<doc>
1929		Pitch is depth width (in pixels) / 8 (aligned to 32).  Height
1930		is also divided by 8 (ie. covers 8x8 pixels)
1931	</doc>
1932	<reg32 offset="0xe103" name="GRAS_LRZ_BUFFER_PITCH" shr="5" type="uint"/>
1933	<reg32 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1934	<reg32 offset="0xe105" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1935
1936	<reg32 offset="0xe140" name="RB_CNTL">
1937		<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1938		<bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
1939		<bitfield name="BYPASS" pos="17" type="boolean"/>
1940	</reg32>
1941	<reg32 offset="0xe141" name="RB_RENDER_CNTL">
1942<!--
1943bit 3 set for normal draws
1944bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
1945	for z32 with no stencil, but maybe in that case separate z/s not used?
1946	see mrt-fbo-* zs=2)
1947 -->
1948		<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1949		<bitfield name="SAMPLES_PASSED" pos="6" type="boolean"/>
1950		<bitfield name="DISABLE_COLOR_PIPE" pos="7" type="boolean"/>
1951		<!-- why everything twice?? maybe read vs write? -->
1952		<!-- UBWC flag buffer enabled for depth/stencil: -->
1953		<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
1954		<bitfield name="FLAG_DEPTH2" pos="15" type="boolean"/>
1955		<!-- bitmask of MRTs using UBWC flag buffer: -->
1956		<bitfield name="FLAG_MRTS" low="16" high="23"/>
1957		<bitfield name="FLAG_MRTS2" low="24" high="31"/>
1958	</reg32>
1959	<reg32 offset="0xe142" name="RB_RAS_MSAA_CNTL">
1960		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1961	</reg32>
1962	<reg32 offset="0xe143" name="RB_DEST_MSAA_CNTL">
1963		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1964		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1965	</reg32>
1966	<!--
1967	note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
1968	name comes from kernel and is probably right)
1969	 -->
1970	<reg32 offset="0xe144" name="RB_RENDER_CONTROL0">
1971		<!-- see also GRAS_CNTL -->
1972		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1973		<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1974		<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1975		<!--
1976		bit 3 set when blob turns on WCOORD.. which also corresponds to
1977		register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
1978		shader does not use).. possibly providing wcoord in an alternate
1979		way??
1980		Also, when that happens, VARYING bits are turned on as well.
1981		 -->
1982		<bitfield name="SIZE" pos="3" type="boolean"/>
1983		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1984	</reg32>
1985	<reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
1986		<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
1987		<bitfield name="FACENESS" pos="1" type="boolean"/>
1988		<bitfield name="SAMPLEID" pos="2" type="boolean"/>
1989	</reg32>
1990	<reg32 offset="0xe146" name="RB_FS_OUTPUT_CNTL">
1991		<!-- bit0 set except for binning pass.. -->
1992		<bitfield name="MRT" low="0" high="3" type="uint"/>
1993		<bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
1994	</reg32>
1995	<reg32 offset="0xe147" name="RB_RENDER_COMPONENTS">
1996		<bitfield name="RT0" low="0" high="3"/>
1997		<bitfield name="RT1" low="4" high="7"/>
1998		<bitfield name="RT2" low="8" high="11"/>
1999		<bitfield name="RT3" low="12" high="15"/>
2000		<bitfield name="RT4" low="16" high="19"/>
2001		<bitfield name="RT5" low="20" high="23"/>
2002		<bitfield name="RT6" low="24" high="27"/>
2003		<bitfield name="RT7" low="28" high="31"/>
2004	</reg32>
2005	<array offset="0xe150" name="RB_MRT" stride="7" length="8">
2006		<reg32 offset="0x0" name="CONTROL">
2007			<bitfield name="BLEND" pos="0" type="boolean"/>
2008			<bitfield name="BLEND2" pos="1" type="boolean"/>
2009			<bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2010			<bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2011			<bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2012		</reg32>
2013		<reg32 offset="0x1" name="BLEND_CONTROL">
2014			<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2015			<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2016			<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2017			<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2018			<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2019			<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2020		</reg32>
2021		<reg32 offset="0x2" name="BUF_INFO">
2022			<!--
2023			not sure if there is a separate COLOR_SWAP field like on a3xx/a4xx,
2024			or if it is inherent in the format.  Will have to play with bits
2025			once we get things working and see what happens.  If it is a diff
2026			field, it doesn't seem to have the same encoding as a3xx/a4xx.
2027			 -->
2028			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2029			<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2030			<bitfield name="DITHER_MODE" low="11" high="12" type="adreno_rb_dither_mode"/>
2031			<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2032			<bitfield name="COLOR_SRGB" pos="15" type="boolean"/>
2033		</reg32>
2034		<!--
2035		at least in gmem, things seem to be aligned to pitch of 64..
2036		maybe an artifact of tiled format used in gmem?
2037		 -->
2038		<reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2039		<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2040		<reg32 offset="0x5" name="BASE_LO"/>
2041		<reg32 offset="0x6" name="BASE_HI"/>
2042	</array>
2043	<reg32 offset="0xe1a0" name="RB_BLEND_RED">
2044		<bitfield name="UINT" low="0" high="7" type="hex"/>
2045		<bitfield name="SINT" low="8" high="15" type="hex"/>
2046		<bitfield name="FLOAT" low="16" high="31" type="float"/>
2047	</reg32>
2048	<reg32 offset="0xe1a1" name="RB_BLEND_RED_F32" type="float"/>
2049	<reg32 offset="0xe1a2" name="RB_BLEND_GREEN">
2050		<bitfield name="UINT" low="0" high="7" type="hex"/>
2051		<bitfield name="SINT" low="8" high="15" type="hex"/>
2052		<bitfield name="FLOAT" low="16" high="31" type="float"/>
2053	</reg32>
2054	<reg32 offset="0xe1a3" name="RB_BLEND_GREEN_F32" type="float"/>
2055	<reg32 offset="0xe1a4" name="RB_BLEND_BLUE">
2056		<bitfield name="UINT" low="0" high="7" type="hex"/>
2057		<bitfield name="SINT" low="8" high="15" type="hex"/>
2058		<bitfield name="FLOAT" low="16" high="31" type="float"/>
2059	</reg32>
2060	<reg32 offset="0xe1a5" name="RB_BLEND_BLUE_F32" type="float"/>
2061	<reg32 offset="0xe1a6" name="RB_BLEND_ALPHA">
2062		<bitfield name="UINT" low="0" high="7" type="hex"/>
2063		<bitfield name="SINT" low="8" high="15" type="hex"/>
2064		<bitfield name="FLOAT" low="16" high="31" type="float"/>
2065	</reg32>
2066	<reg32 offset="0xe1a7" name="RB_BLEND_ALPHA_F32" type="float"/>
2067	<reg32 offset="0xe1a8" name="RB_ALPHA_CONTROL">
2068		<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2069		<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2070		<bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2071	</reg32>
2072	<reg32 offset="0xe1a9" name="RB_BLEND_CNTL">
2073		<!-- per-mrt enable bit -->
2074		<bitfield name="ENABLE_BLEND" low="0" high="7"/>
2075		<bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2076		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2077		<!-- a guess? -->
2078		<bitfield name="SAMPLE_MASK" low="16" high="31"/>
2079	</reg32>
2080	<reg32 offset="0xe1b0" name="RB_DEPTH_PLANE_CNTL">
2081		<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2082		<bitfield name="UNK1" pos="1" type="boolean"/>
2083	</reg32>
2084	<reg32 offset="0xe1b1" name="RB_DEPTH_CNTL">
2085		<bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2086		<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2087		<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2088		<doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
2089		<bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2090	</reg32>
2091	<reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO">
2092		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
2093	</reg32>
2094	<reg32 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE_LO"/>
2095	<reg32 offset="0xe1b4" name="RB_DEPTH_BUFFER_BASE_HI"/>
2096	<reg32 offset="0xe1b5" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2097		<doc>stride of depth/stencil buffer</doc>
2098	</reg32>
2099	<reg32 offset="0xe1b6" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2100		<doc>size of layer</doc>
2101	</reg32>
2102	<reg32 offset="0xe1c0" name="RB_STENCIL_CONTROL">
2103		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2104		<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2105		<!--
2106			set for stencil operations that require read from stencil
2107			buffer, but not for example for stencil clear (which does
2108			not require read).. so guessing this is analogous to
2109			READ_DEST_ENABLE for color buffer..
2110		 -->
2111		<bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2112		<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2113		<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2114		<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2115		<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2116		<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2117		<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2118		<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2119		<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2120	</reg32>
2121	<reg32 offset="0xe1c1" name="RB_STENCIL_INFO">
2122		<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2123	</reg32>
2124	<reg32 offset="0xe1c2" name="RB_STENCIL_BASE_LO"/>
2125	<reg32 offset="0xe1c3" name="RB_STENCIL_BASE_HI"/>
2126	<reg32 offset="0xe1c4" name="RB_STENCIL_PITCH" shr="6" type="uint"/>
2127	<reg32 offset="0xe1c5" name="RB_STENCIL_ARRAY_PITCH" shr="6" type="uint"/>
2128	<reg32 offset="0xe1c6" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
2129	<reg32 offset="0xe1c7" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
2130	<reg32 offset="0xe1d0" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2131	<reg32 offset="0xe1d1" name="RB_SAMPLE_COUNT_CONTROL">
2132		<bitfield name="COPY" pos="1" type="boolean"/>
2133	</reg32>
2134
2135	<doc>
2136		Blits:
2137		------
2138
2139		Blits are triggered by CP_EVENT_WRITE:BLIT, compared to previous
2140		generations where they shared most of the gl pipeline and were
2141		triggered by CP_DRAW_INDX*
2142
2143		For gmem->mem blob uses RB_BLIT_CNTL.BUF to specify src of
2144		blit (ie MRTn, ZS, etc) and RB_BLIT_DST_LO/HI for destination
2145		gpuaddr.  The gmem offset is taken from RB_MRT[n].BASE_LO/HI
2146
2147		For mem->gmem blob uses just MRT0 or ZS and RB_BLIT_DST_LO/HI
2148		for the GMEM offset, and gpuaddr from RB_MRT[0].BASE_LO/HI
2149		(I suppose this is just to avoid trashing RB_MRT[1..7]??)
2150	</doc>
2151	<reg32 offset="0xe210" name="RB_BLIT_CNTL">
2152		<bitfield name="BUF" low="0" high="3" type="a5xx_blit_buf"/>
2153	</reg32>
2154	<reg32 offset="0xe211" name="RB_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2155	<reg32 offset="0xe212" name="RB_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2156	<reg32 offset="0xe213" name="RB_RESOLVE_CNTL_3">
2157		<!-- if b0 set, output is in TILE5_3 format -->
2158		<bitfield name="TILED" pos="0" type="boolean"/>
2159	<!--
2160		0xe213:
2161		        0x0 mem->gmem
2162		        0xf gmem->mem with flag buffer (color)
2163		        0x4 gmem->mem without flag buffer (color)
2164		        0x7 BYPASS mode flag buffer result (ie. on readpix)
2165		            also for gmem->mem preserving tiling
2166	-->
2167	</reg32>
2168	<reg32 offset="0xe214" name="RB_BLIT_DST_LO"/>
2169	<reg32 offset="0xe215" name="RB_BLIT_DST_HI"/>
2170	<reg32 offset="0xe216" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2171	<!-- array-pitch is size of layer -->
2172	<reg32 offset="0xe217" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2173	<reg32 offset="0xe218" name="RB_CLEAR_COLOR_DW0"/>
2174	<reg32 offset="0xe219" name="RB_CLEAR_COLOR_DW1"/>
2175	<reg32 offset="0xe21a" name="RB_CLEAR_COLOR_DW2"/>
2176	<reg32 offset="0xe21b" name="RB_CLEAR_COLOR_DW3"/>
2177	<reg32 offset="0xe21c" name="RB_CLEAR_CNTL">
2178		<bitfield name="FAST_CLEAR" pos="1" type="boolean"/>
2179		<bitfield name="MSAA_RESOLVE" pos="2" type="boolean"/>
2180		<doc>
2181			For MASK, if RB_BLIT_CNTL.BUF=BLIT_ZS:
2182				1 - depth
2183				2 - stencil
2184				3 - depth+stencil
2185			if RB_BLIT_CNTL.BUF=BLIT_MRTn
2186				then probably a component mask, I always see 0xf
2187		</doc>
2188		<bitfield name="MASK" low="4" high="7"/>
2189	</reg32>
2190
2191	<doc>
2192		Buffer Metadata (flag buffers):
2193		-------------------------------
2194
2195		Blob seems to stick some metadata at the front of the buffer,
2196		both z/s and MRT.  I think this is same as UBWC (bandwidth
2197		compression) metadata that mdp 1.7 and later supports.  See
2198		1d3fae5698ce5358caab87a15383b690941697e8 in downstream kernel.
2199		UBWC seems to stand for "universal bandwidth compression".
2200
2201		Before glReadPixels() it does a pair of BYPASS blits (at least
2202		if metadata is used) presumably to resolve metadata.
2203
2204		NOTES: see: getUBwcBlockSize(), getUBwcMetaBufferSize() at
2205		https://android.googlesource.com/platform/hardware/qcom/display/+/android-6.0.1_r40/msm8994/libgralloc/alloc_controller.cpp
2206		(note that bpp in bytes, not bits, so really cpp)
2207
2208		Example Layout 2d w/ mipmap levels:
2209
2210			100x2000, ifmt=GL_RG, fmt=GL_RG16F, type=GL_FLOAT, meta=64x512@0x8000 (7x500)
2211				base=c072e000, offset=16384, size=1703936
2212
2213				color		flags
2214			0	c073a000	c0732000	- level 0 flags is address
2215			1	c0838000	c0834000	  programmed in texture state
2216			2	c0879000	c0877000
2217			3	c089a000	c0899000
2218			4	c08ab000	c08aa000
2219			5	c08b4000	c08b3000
2220			6	c08b9000	c08b8000
2221			7	c08bc000	c08bb000
2222			8	c08be000	c08bd000
2223			9	c08c0000	c08bf000
2224			10	c08c2000	c08c1000
2225
2226		ARRAY_PITCH is the combined size of all the levels plus flags,
2227		so 0xc08c3000 - 0xc0732000 = 0x00191000 (1642496); each level
2228		takes up a minimum of 2 pages (since color and flags parts are
2229		each page aligned.
2230
2231			{ TILE_MODE = TILE5_3 | SWIZ_X = A5XX_TEX_X | SWIZ_Y = A5XX_TEX_Y | SWIZ_Z = A5XX_TEX_ZERO | SWIZ_W = A5XX_TEX_ONE | MIPLVLS = 0 | FMT = TFMT5_16_16_FLOAT | SWAP = WZYX }
2232			{ WIDTH = 100 | HEIGHT = 2000 }
2233			{ FETCHSIZE = TFETCH5_4_BYTE | PITCH = 512 | TYPE = A5XX_TEX_2D }
2234			{ ARRAY_PITCH = 1642496 | 0x18800000 }  - NOTE c2dc always has 0x18800000 but
2235			{ BASE_LO = 0xc0732000 }                  this varies for blob gles driver..
2236			{ BASE_HI = 0 | DEPTH = 1 }               not sure what it is
2237
2238
2239	</doc>
2240	<reg32 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2241	<reg32 offset="0xe241" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2242	<reg32 offset="0xe242" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2243	</reg32>
2244	<array offset="0xe243" name="RB_MRT_FLAG_BUFFER" stride="4" length="8">
2245		<reg32 offset="0" name="ADDR_LO"/>
2246		<reg32 offset="1" name="ADDR_HI"/>
2247		<reg32 offset="2" name="PITCH" shr="6" type="uint"/>
2248		<!-- array-pitch is size of layer -->
2249		<reg32 offset="3" name="ARRAY_PITCH" shr="6" type="uint"/>
2250	</array>
2251	<reg32 offset="0xe263" name="RB_BLIT_FLAG_DST_LO"/>
2252	<reg32 offset="0xe264" name="RB_BLIT_FLAG_DST_HI"/>
2253	<reg32 offset="0xe265" name="RB_BLIT_FLAG_DST_PITCH" shr="6" type="uint"/>
2254	<!-- array-pitch is size of layer -->
2255	<reg32 offset="0xe266" name="RB_BLIT_FLAG_DST_ARRAY_PITCH" shr="6" type="uint"/>
2256
2257	<reg32 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2258	<reg32 offset="0xe268" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2259
2260	<reg32 offset="0xe280" name="VPC_CNTL_0">
2261		<doc>
2262			num of varyings plus four for gl_Position (plus one if gl_PointSize)
2263			plus # of transform-feedback (streamout) varyings if using the
2264			hw streamout (rather than stg instructions in shader)
2265		</doc>
2266		<bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2267		<bitfield name="VARYING" pos="11" type="boolean"/>
2268	</reg32>
2269	<array offset="0xe282" name="VPC_VARYING_INTERP" stride="1" length="8">
2270		<reg32 offset="0x0" name="MODE"/>
2271	</array>
2272	<array offset="0xe28a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2273		<reg32 offset="0x0" name="MODE"/>
2274	</array>
2275	<reg32 offset="0xe292" name="UNKNOWN_E292"/>
2276	<reg32 offset="0xe293" name="UNKNOWN_E293"/>
2277	<array offset="0xe294" name="VPC_VAR" stride="1" length="4">
2278		<!-- one bit per varying component: -->
2279		<reg32 offset="0" name="DISABLE"/>
2280	</array>
2281	<reg32 offset="0xe298" name="VPC_GS_SIV_CNTL"/>
2282	<reg32 offset="0xe29a" name="UNKNOWN_E29A"/>
2283	<reg32 offset="0xe29d" name="VPC_PACK">
2284		<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2285		<!--
2286		This seems to be the OUTLOC for the psize output.  It could possibly
2287		be the max-OUTLOC position, but it is only set when VS writes psize
2288		(and blob always puts psize at highest OUTLOC)
2289		 -->
2290		<bitfield name="PSIZELOC" low="8" high="15" type="uint"/>
2291	</reg32>
2292	<reg32 offset="0xe2a0" name="VPC_FS_PRIMITIVEID_CNTL"/>
2293
2294	<doc>
2295		Stream-Out:
2296		-----------
2297
2298		VPC_SO[0..3] registers setup details about streamout buffers, and
2299		number of components to write to each.
2300
2301		VPC_SO_PROG provides the mapping between output varyings and the SO
2302		buffers.  It is written multiple times (via a CP_CONTEXT_REG_BUNCH
2303		packet, not sure if that matters), each write can handle up to two
2304		components of stream-out output.  Order matches up to OUTLOC,
2305		including padding.  So, if outputting first 3 varyings:
2306
2307			SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0x7 }
2308			SP_VS_OUT[0x1].REG: { A_REGID = r1.w | A_COMPMASK = 0x3 | B_REGID = r2.y | B_COMPMASK = 0xf }
2309			SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 8 | OUTLOC3 = 12 }
2310
2311		Then:
2312
2313			VPC_SO_PROG: { A_BUF = 0 | A_OFF = 0 | A_EN | A_BUF = 0 | B_OFF = 4 | B_EN }
2314			VPC_SO_PROG: { A_BUF = 0 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 12 | B_EN }
2315			VPC_SO_PROG: { A_BUF = 2 | A_OFF = 0 | A_EN | A_BUF = 2 | B_OFF = 4 | B_EN }
2316			VPC_SO_PROG: { A_BUF = 2 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 0 }
2317			VPC_SO_PROG: { A_BUF = 1 | A_OFF = 0 | A_EN | A_BUF = 1 | B_OFF = 4 | B_EN }
2318
2319		Note that varying order is OUTLOC0, OUTLOC2, OUTLOC1, and note
2320		the padding between OUTLOC1 and OUTLOC2.
2321
2322		The BUF bitfield indicates which of the four streamout buffers
2323		to write into at the specified offset.
2324
2325		The VPC_SO[n].FLUSH_BASE_LO/HI is used for hw to write back next
2326		offset which gets loaded back into VPC_SO[n].BUFFER_OFFSET via a
2327		CP_MEM_TO_REG.  Probably can be ignored until we have GS/etc, at
2328		which point we can't calculate the offset on the CPU.
2329	</doc>
2330	<reg32 offset="0xe2a1" name="VPC_SO_BUF_CNTL">
2331		<bitfield name="BUF0" pos="0" type="boolean"/>
2332		<bitfield name="BUF1" pos="3" type="boolean"/>
2333		<bitfield name="BUF2" pos="6" type="boolean"/>
2334		<bitfield name="BUF3" pos="9" type="boolean"/>
2335		<bitfield name="ENABLE" pos="15" type="boolean"/>
2336	</reg32>
2337	<reg32 offset="0xe2a2" name="VPC_SO_OVERRIDE">
2338		<bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2339	</reg32>
2340	<reg32 offset="0xe2a3" name="VPC_SO_CNTL">
2341		<!-- always 0x10000 when SO enabled.. -->
2342		<bitfield name="ENABLE" pos="16" type="boolean"/>
2343	</reg32>
2344	<reg32 offset="0xe2a4" name="VPC_SO_PROG">
2345		<bitfield name="A_BUF" low="0" high="1" type="uint"/>
2346		<bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2347		<bitfield name="A_EN" pos="11" type="boolean"/>
2348		<bitfield name="B_BUF" low="12" high="13" type="uint"/>
2349		<bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2350		<bitfield name="B_EN" pos="23" type="boolean"/>
2351	</reg32>
2352	<array offset="0xe2a7" name="VPC_SO" stride="7" length="4">
2353		<reg32 offset="0" name="BUFFER_BASE_LO"/>
2354		<reg32 offset="1" name="BUFFER_BASE_HI"/>
2355		<reg32 offset="2" name="BUFFER_SIZE"/>
2356		<reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2357		<reg32 offset="4" name="BUFFER_OFFSET"/>
2358		<reg32 offset="5" name="FLUSH_BASE_LO"/>
2359		<reg32 offset="6" name="FLUSH_BASE_HI"/>
2360	</array>
2361
2362	<reg32 offset="0xe384" name="PC_PRIMITIVE_CNTL">
2363		<!-- # of varyings plus four for gl_Position (plus one if gl_PointSize) -->
2364		<bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2365		<bitfield name="PRIMITIVE_RESTART" pos="8" type="boolean"/>
2366		<bitfield name="COUNT_PRIMITIVES" pos="9" type="boolean"/><!-- enabled when gl_PrimitiveIDIn is used -->
2367		<bitfield name="PROVOKING_VTX_LAST" pos="10" type="boolean"/>
2368	</reg32>
2369	<reg32 offset="0xe385" name="PC_PRIM_VTX_CNTL">
2370		<bitfield name="PSIZE" pos="11" type="boolean"/>
2371	</reg32>
2372	<reg32 offset="0xe388" name="PC_RASTER_CNTL">
2373		<bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
2374		<bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
2375		<bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
2376	</reg32>
2377	<reg32 offset="0xe389" name="UNKNOWN_E389"/>
2378	<reg32 offset="0xe38c" name="PC_RESTART_INDEX"/>
2379	<reg32 offset="0xe38d" name="PC_GS_LAYERED"/>
2380	<reg32 offset="0xe38e" name="PC_GS_PARAM">
2381		<bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- vertices - 1 -->
2382		<bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- invoc - 1 -->
2383		<bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
2384	</reg32>
2385	<reg32 offset="0xe38f" name="PC_HS_PARAM">
2386		<bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
2387		<bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
2388		<bitfield name="CW" pos="23" type="boolean"/>
2389		<bitfield name="CONNECTED" pos="24" type="boolean"/>
2390	</reg32>
2391	<reg32 offset="0xe3b0" name="PC_POWER_CNTL"/>
2392
2393	<reg32 offset="0xe400" name="VFD_CONTROL_0">
2394		<bitfield name="VTXCNT" low="0" high="5" type="uint"/>
2395	</reg32>
2396	<reg32 offset="0xe401" name="VFD_CONTROL_1">
2397		<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2398		<bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2399		<bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2400	</reg32>
2401	<reg32 offset="0xe402" name="VFD_CONTROL_2">
2402		<bitfield name="REGID_PATCHID" low="0" high="7" type="a3xx_regid"/><!-- same as VFD_CONTROL_3.REGID_PATCHID? -->
2403	</reg32>
2404	<reg32 offset="0xe403" name="VFD_CONTROL_3">
2405		<bitfield name="REGID_PATCHID" low="8" high="15" type="a3xx_regid"/>
2406		<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2407		<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2408	</reg32>
2409	<reg32 offset="0xe404" name="VFD_CONTROL_4">
2410	</reg32>
2411	<reg32 offset="0xe405" name="VFD_CONTROL_5">
2412		<!-- b0 set if gl_PrimitiveID used in fs ?? -->
2413	</reg32>
2414	<reg32 offset="0xe408" name="VFD_INDEX_OFFSET"/>
2415	<reg32 offset="0xe409" name="VFD_INSTANCE_START_OFFSET"/>
2416	<array offset="0xe40a" name="VFD_FETCH" stride="4" length="32">
2417		<reg32 offset="0x0" name="BASE_LO"/>
2418		<reg32 offset="0x1" name="BASE_HI"/>
2419		<reg32 offset="0x2" name="SIZE" type="uint"/>
2420		<reg32 offset="0x3" name="STRIDE" type="uint"/>
2421	</array>
2422	<array offset="0xe48a" name="VFD_DECODE" stride="2" length="32">
2423		<reg32 offset="0x0" name="INSTR">
2424			<!-- IDX appears to index into VFD_FETCH[] -->
2425			<bitfield name="IDX" low="0" high="4" type="uint"/>
2426			<bitfield name="INSTANCED" pos="17" type="boolean"/>
2427			<bitfield name="FORMAT" low="20" high="27" type="a5xx_vtx_fmt"/>
2428			<bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2429			<bitfield name="UNK30" pos="30" type="boolean"/>
2430			<bitfield name="FLOAT" pos="31" type="boolean"/>
2431		</reg32>
2432		<reg32 offset="0x1" name="STEP_RATE"/> <!-- ??? -->
2433	</array>
2434	<array offset="0xe4ca" name="VFD_DEST_CNTL" stride="1" length="32">
2435		<reg32 offset="0x0" name="INSTR">
2436			<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2437			<bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2438		</reg32>
2439	</array>
2440	<reg32 offset="0xe4f0" name="VFD_POWER_CNTL"/>
2441
2442	<!-- 0x0 for compute, 0x10 for 3d? -->
2443	<reg32 offset="0xe580" name="SP_SP_CNTL"/>
2444
2445	<bitset name="a5xx_xs_config" inline="yes">
2446		<bitfield name="ENABLED" pos="0" type="boolean"/>
2447		<bitfield name="CONSTOBJECTOFFSET" low="1" high="7" type="uint"/>
2448		<bitfield name="SHADEROBJOFFSET" low="8" high="14" type="uint"/>
2449	</bitset>
2450	<bitset name="a5xx_xs_cntl" inline="yes">
2451		<bitfield name="SSBO_ENABLE" pos="0" type="boolean"/>
2452		<!--
2453		no idea high bit.. could be this is amount of on-chip memory used
2454		rather than total size?
2455		 -->
2456		<bitfield name="INSTRLEN" low="1" high="31" type="uint"/>
2457	</bitset>
2458	<bitset name="a5xx_sp_xs_ctrl_reg0" inline="yes">
2459		<!-- bit1 + bit2 set for "buffer" mode (ie. shader small enough to fit internally) -->
2460		<!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
2461		<bitfield name="THREADSIZE" pos="3" type="a3xx_threadsize"/>
2462		<bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
2463		<bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
2464		<bitfield name="VARYING" pos="16" type="boolean"/>
2465		<bitfield name="PIXLODENABLE" pos="20" type="boolean"/>
2466		<!-- seems to be nesting level for flow control:.. -->
2467		<bitfield name="BRANCHSTACK" low="25" high="31" type="uint"/>
2468	</bitset>
2469	<!-- assuming things appear in same relative order as a4xx: -->
2470	<!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. -->
2471	<reg32 offset="0xe584" name="SP_VS_CONFIG" type="a5xx_xs_config"/>
2472	<reg32 offset="0xe585" name="SP_FS_CONFIG" type="a5xx_xs_config"/>
2473	<reg32 offset="0xe586" name="SP_HS_CONFIG" type="a5xx_xs_config"/>
2474	<reg32 offset="0xe587" name="SP_DS_CONFIG" type="a5xx_xs_config"/>
2475	<reg32 offset="0xe588" name="SP_GS_CONFIG" type="a5xx_xs_config"/>
2476	<reg32 offset="0xe589" name="SP_CS_CONFIG" type="a5xx_xs_config"/>
2477	<reg32 offset="0xe58a" name="SP_VS_CONFIG_MAX_CONST"/>
2478	<reg32 offset="0xe58b" name="SP_FS_CONFIG_MAX_CONST"/>
2479	<reg32 offset="0xe590" name="SP_VS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2480	<reg32 offset="0xe592" name="SP_PRIMITIVE_CNTL">
2481		<!-- # of VS outputs including pos/psize -->
2482		<bitfield name="VSOUT" low="0" high="4" type="uint"/>
2483	</reg32>
2484	<array offset="0xe593" name="SP_VS_OUT" stride="1" length="16">
2485		<reg32 offset="0x0" name="REG">
2486			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2487			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2488			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2489			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2490		</reg32>
2491	</array>
2492	<!--
2493	Starting with a5xx, position/psize outputs from shader end up in the
2494	SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2495	the last entries too, except when gl_PointCoord is used, blob inserts
2496	an extra varying after, but with a lower OUTLOC position.  If present,
2497	psize is last, preceded by position.
2498	 -->
2499	<array offset="0xe5a3" name="SP_VS_VPC_DST" stride="1" length="8">
2500		<reg32 offset="0x0" name="REG">
2501			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2502			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2503			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2504			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2505		</reg32>
2506	</array>
2507	<reg32 offset="0xe5ab" name="UNKNOWN_E5AB"/>
2508	<reg32 offset="0xe5ac" name="SP_VS_OBJ_START_LO"/>
2509	<reg32 offset="0xe5ad" name="SP_VS_OBJ_START_HI"/>
2510	<reg32 offset="0xe5c0" name="SP_FS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2511	<reg32 offset="0xe5c2" name="UNKNOWN_E5C2"/>
2512	<reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/>
2513	<reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/>
2514	<reg32 offset="0xe5c9" name="SP_BLEND_CNTL">
2515		<bitfield name="ENABLED" pos="0" type="boolean"/>
2516		<bitfield name="UNK8" pos="8" type="boolean"/>
2517		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2518	</reg32>
2519	<reg32 offset="0xe5ca" name="SP_FS_OUTPUT_CNTL">
2520		<bitfield name="MRT" low="0" high="3" type="uint"/>
2521		<bitfield name="DEPTH_REGID" low="5" high="12" type="a3xx_regid"/>
2522		<bitfield name="SAMPLEMASK_REGID" low="13" high="20" type="a3xx_regid"/>
2523	</reg32>
2524	<array offset="0xe5cb" name="SP_FS_OUTPUT" stride="1" length="8">
2525		<doc>per MRT</doc>
2526		<reg32 offset="0x0" name="REG">
2527			<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
2528			<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
2529		</reg32>
2530	</array>
2531	<array offset="0xe5d3" name="SP_FS_MRT" stride="1" length="8">
2532		<reg32 offset="0" name="REG">
2533			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2534			<bitfield name="COLOR_SINT" pos="8" type="boolean"/>
2535			<bitfield name="COLOR_UINT" pos="9" type="boolean"/>
2536			<bitfield name="COLOR_SRGB" pos="10" type="boolean"/>
2537		</reg32>
2538	</array>
2539	<!--
2540	e5db/e5dc seems to look related to some optimization to do sample from
2541	texture using varying value directly before shader thread starts?  I
2542	guess that could optimize common simple frag shaders..
2543	 -->
2544	<reg32 offset="0xe5db" name="UNKNOWN_E5DB"/>
2545	<reg32 offset="0xe5f0" name="SP_CS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2546	<reg32 offset="0xe5f2" name="UNKNOWN_E5F2"/>
2547	<reg32 offset="0xe5f3" name="SP_CS_OBJ_START_LO"/>
2548	<reg32 offset="0xe5f4" name="SP_CS_OBJ_START_HI"/>
2549	<!-- e5f9 something compute related.. seems to change when HLSQ_CS_CNTL_1 changes -->
2550
2551	<reg32 offset="0xe600" name="SP_HS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2552	<reg32 offset="0xe602" name="UNKNOWN_E602"/>
2553	<reg32 offset="0xe603" name="SP_HS_OBJ_START_LO"/>
2554	<reg32 offset="0xe604" name="SP_HS_OBJ_START_HI"/>
2555	<reg32 offset="0xe610" name="SP_DS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2556	<reg32 offset="0xe62b" name="UNKNOWN_E62B"/>
2557	<reg32 offset="0xe62c" name="SP_DS_OBJ_START_LO"/>
2558	<reg32 offset="0xe62d" name="SP_DS_OBJ_START_HI"/>
2559	<reg32 offset="0xe640" name="SP_GS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2560	<reg32 offset="0xe65b" name="UNKNOWN_E65B"/>
2561	<reg32 offset="0xe65c" name="SP_GS_OBJ_START_LO"/>
2562	<reg32 offset="0xe65d" name="SP_GS_OBJ_START_HI"/>
2563
2564	<reg32 offset="0xe704" name="TPL1_TP_RAS_MSAA_CNTL">
2565		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2566	</reg32>
2567	<reg32 offset="0xe705" name="TPL1_TP_DEST_MSAA_CNTL">
2568		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2569		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2570	</reg32>
2571	<!-- either blob is doing it wrong, or this is not per-stage anymore: -->
2572	<reg32 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_LO"/>
2573	<reg32 offset="0xe707" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_HI"/>
2574
2575	<!--
2576	so these have the same info that is normally in the CP_LOAD_STATE
2577	packets.. not sure if they are normally written by pm4/me or if the
2578	CP_LOAD_STATE mechanism is deprecated?
2579	 -->
2580	<reg32 offset="0xe700" name="TPL1_VS_TEX_COUNT" type="uint"/>
2581	<reg32 offset="0xe701" name="TPL1_HS_TEX_COUNT" type="uint"/>
2582	<reg32 offset="0xe702" name="TPL1_DS_TEX_COUNT" type="uint"/>
2583	<reg32 offset="0xe703" name="TPL1_GS_TEX_COUNT" type="uint"/>
2584
2585	<reg32 offset="0xe722" name="TPL1_VS_TEX_SAMP_LO"/>
2586	<reg32 offset="0xe723" name="TPL1_VS_TEX_SAMP_HI"/>
2587	<reg32 offset="0xe724" name="TPL1_HS_TEX_SAMP_LO"/>
2588	<reg32 offset="0xe725" name="TPL1_HS_TEX_SAMP_HI"/>
2589	<reg32 offset="0xe726" name="TPL1_DS_TEX_SAMP_LO"/>
2590	<reg32 offset="0xe727" name="TPL1_DS_TEX_SAMP_HI"/>
2591	<reg32 offset="0xe728" name="TPL1_GS_TEX_SAMP_LO"/>
2592	<reg32 offset="0xe729" name="TPL1_GS_TEX_SAMP_HI"/>
2593
2594	<reg32 offset="0xe72a" name="TPL1_VS_TEX_CONST_LO"/>
2595	<reg32 offset="0xe72b" name="TPL1_VS_TEX_CONST_HI"/>
2596	<reg32 offset="0xe72c" name="TPL1_HS_TEX_CONST_LO"/>
2597	<reg32 offset="0xe72d" name="TPL1_HS_TEX_CONST_HI"/>
2598	<reg32 offset="0xe72e" name="TPL1_DS_TEX_CONST_LO"/>
2599	<reg32 offset="0xe72f" name="TPL1_DS_TEX_CONST_HI"/>
2600	<reg32 offset="0xe730" name="TPL1_GS_TEX_CONST_LO"/>
2601	<reg32 offset="0xe731" name="TPL1_GS_TEX_CONST_HI"/>
2602
2603	<reg32 offset="0xe750" name="TPL1_FS_TEX_COUNT" type="uint"/>
2604	<reg32 offset="0xe751" name="TPL1_CS_TEX_COUNT" type="uint"/>
2605
2606	<reg32 offset="0xe75a" name="TPL1_FS_TEX_SAMP_LO"/>
2607	<reg32 offset="0xe75b" name="TPL1_FS_TEX_SAMP_HI"/>
2608	<reg32 offset="0xe75c" name="TPL1_CS_TEX_SAMP_LO"/>
2609	<reg32 offset="0xe75d" name="TPL1_CS_TEX_SAMP_HI"/>
2610	<reg32 offset="0xe75e" name="TPL1_FS_TEX_CONST_LO"/>
2611	<reg32 offset="0xe75f" name="TPL1_FS_TEX_CONST_HI"/>
2612	<reg32 offset="0xe760" name="TPL1_CS_TEX_CONST_LO"/>
2613	<reg32 offset="0xe761" name="TPL1_CS_TEX_CONST_HI"/>
2614
2615	<reg32 offset="0xe764" name="TPL1_TP_FS_ROTATION_CNTL"/>
2616
2617	<reg32 offset="0xe784" name="HLSQ_CONTROL_0_REG">
2618		<!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
2619		<bitfield name="FSTHREADSIZE" pos="0" type="a3xx_threadsize"/>
2620		<bitfield name="CSTHREADSIZE" pos="2" type="a3xx_threadsize"/>
2621	</reg32>
2622	<reg32 offset="0xe785" name="HLSQ_CONTROL_1_REG">
2623		<!-- I guess.. not set exactly same as a4xx, but similar: -->
2624		<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="5" type="uint"/>
2625	</reg32>
2626	<reg32 offset="0xe786" name="HLSQ_CONTROL_2_REG">
2627		<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
2628		<!-- SAMPLEID is loaded into a half-precision register: -->
2629		<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
2630		<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
2631		<bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
2632	</reg32>
2633	<reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG">
2634		<!-- register loaded with position (bary.f) -->
2635		<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
2636		<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
2637		<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
2638		<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
2639	</reg32>
2640	<reg32 offset="0xe788" name="HLSQ_CONTROL_4_REG">
2641		<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
2642		<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
2643		<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
2644		<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
2645	</reg32>
2646	<!--
2647	0x020fffff for normal draws, 0x1f00000 for compute.. maybe what state
2648	is enabled?  We could probably try disabling different bits and see
2649	what breaks to figure out which is what:
2650	 -->
2651	<reg32 offset="0xe78a" name="HLSQ_UPDATE_CNTL"/>
2652	<reg32 offset="0xe78b" name="HLSQ_VS_CONFIG" type="a5xx_xs_config"/>
2653	<reg32 offset="0xe78c" name="HLSQ_FS_CONFIG" type="a5xx_xs_config"/>
2654	<reg32 offset="0xe78d" name="HLSQ_HS_CONFIG" type="a5xx_xs_config"/>
2655	<reg32 offset="0xe78e" name="HLSQ_DS_CONFIG" type="a5xx_xs_config"/>
2656	<reg32 offset="0xe78f" name="HLSQ_GS_CONFIG" type="a5xx_xs_config"/>
2657	<reg32 offset="0xe790" name="HLSQ_CS_CONFIG" type="a5xx_xs_config"/>
2658	<reg32 offset="0xe791" name="HLSQ_VS_CNTL" type="a5xx_xs_cntl"/>
2659	<reg32 offset="0xe792" name="HLSQ_FS_CNTL" type="a5xx_xs_cntl"/>
2660	<reg32 offset="0xe793" name="HLSQ_HS_CNTL" type="a5xx_xs_cntl"/>
2661	<reg32 offset="0xe794" name="HLSQ_DS_CNTL" type="a5xx_xs_cntl"/>
2662	<reg32 offset="0xe795" name="HLSQ_GS_CNTL" type="a5xx_xs_cntl"/>
2663	<reg32 offset="0xe796" name="HLSQ_CS_CNTL" type="a5xx_xs_cntl"/>
2664	<reg32 offset="0xe7b9" name="HLSQ_CS_KERNEL_GROUP_X"/>
2665	<reg32 offset="0xe7ba" name="HLSQ_CS_KERNEL_GROUP_Y"/>
2666	<reg32 offset="0xe7bb" name="HLSQ_CS_KERNEL_GROUP_Z"/>
2667	<reg32 offset="0xe7b0" name="HLSQ_CS_NDRANGE_0">
2668		<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
2669		<!-- localsize is value minus one: -->
2670		<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
2671		<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
2672		<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
2673	</reg32>
2674	<reg32 offset="0xe7b1" name="HLSQ_CS_NDRANGE_1">
2675		<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
2676	</reg32>
2677	<reg32 offset="0xe7b2" name="HLSQ_CS_NDRANGE_2">
2678		<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
2679	</reg32>
2680	<reg32 offset="0xe7b3" name="HLSQ_CS_NDRANGE_3">
2681		<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
2682	</reg32>
2683	<reg32 offset="0xe7b4" name="HLSQ_CS_NDRANGE_4">
2684		<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
2685	</reg32>
2686	<reg32 offset="0xe7b5" name="HLSQ_CS_NDRANGE_5">
2687		<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
2688	</reg32>
2689	<reg32 offset="0xe7b6" name="HLSQ_CS_NDRANGE_6">
2690		<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
2691	</reg32>
2692	<reg32 offset="0xe7b7" name="HLSQ_CS_CNTL_0">
2693		<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
2694		<!-- possibly one of these is KERNELDIMCONSTID? -->
2695		<!--
2696		UNK0 appears to be NUMWGCONSTID.. but only works in certain
2697		cases?  Blob doesn't appear to use it, but instead emits
2698		these via const (uniform).  Which requires some shenanigans
2699		for indirect draws when the offset is not strongly aligned
2700		enough to use as EXT_SRC_ADDR in CP_LOAD_STATE
2701		 -->
2702		<bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
2703		<bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
2704		<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
2705	</reg32>
2706	<reg32 offset="0xe7b8" name="HLSQ_CS_CNTL_1"/>
2707	<reg32 offset="0xe7c0" name="UNKNOWN_E7C0"/>
2708	<reg32 offset="0xe7c3" name="HLSQ_VS_CONSTLEN" type="uint"/>
2709	<reg32 offset="0xe7c4" name="HLSQ_VS_INSTRLEN" type="uint"/>
2710	<reg32 offset="0xe7c5" name="UNKNOWN_E7C5"/>
2711	<reg32 offset="0xe7c8" name="HLSQ_HS_CONSTLEN" type="uint"/>
2712	<reg32 offset="0xe7c9" name="HLSQ_HS_INSTRLEN" type="uint"/>
2713	<reg32 offset="0xe7ca" name="UNKNOWN_E7CA"/>
2714	<reg32 offset="0xe7cd" name="HLSQ_DS_CONSTLEN" type="uint"/>
2715	<reg32 offset="0xe7ce" name="HLSQ_DS_INSTRLEN" type="uint"/>
2716	<reg32 offset="0xe7cf" name="UNKNOWN_E7CF"/>
2717	<reg32 offset="0xe7d2" name="HLSQ_GS_CONSTLEN" type="uint"/>
2718	<reg32 offset="0xe7d3" name="HLSQ_GS_INSTRLEN" type="uint"/>
2719	<reg32 offset="0xe7d4" name="UNKNOWN_E7D4"/>
2720	<reg32 offset="0xe7d7" name="HLSQ_FS_CONSTLEN" type="uint"/>
2721	<reg32 offset="0xe7d8" name="HLSQ_FS_INSTRLEN" type="uint"/>
2722	<reg32 offset="0xe7d9" name="UNKNOWN_E7D9"/>
2723	<reg32 offset="0xe7dc" name="HLSQ_CS_CONSTLEN" type="uint"/>
2724	<reg32 offset="0xe7dd" name="HLSQ_CS_INSTRLEN" type="uint"/>
2725
2726	<!--
2727		Separate blit/2d or dma engine?  Seems to get used sometimes for
2728		texture uploads, where a4xx blob would use normal draws.  Used
2729		in render-mode 0x5..
2730
2731		Note seems mostly to be used for small blits, large blits seem
2732		to use the CP_EVENT_WRITE:BLIT style of doing things.  See
2733		cubemap-0003 (40x40) vs cubemap-0004 (256x256).
2734
2735		see cube-0000, cubemap-(1..3 but not 4+), quad-textured-10..17
2736
2737		Other nearby registers are probably color formats, etc.  The
2738		blit coords are in CP packet.  Play more w/ glTexSubImage2D()
2739		to work it out.
2740
2741		Separate this into a different domain??  Would that help to
2742		restrict which registers we dump based on mode?
2743
2744		regs 0x2000 to 0x2004 (plus all-zero regs 0x2005-0x2009) look
2745		like 2nd source for blending?  Used in mipmap generation.. but
2746		maybe layout is a bit different.  (Possibly used for reading
2747		src via sampler, to enable scaling??)  0x2040 also used in this
2748		case.
2749	 -->
2750	<reg32 offset="0x2100" name="RB_2D_BLIT_CNTL"/>  <!-- same as 0x2180 -->
2751	<reg32 offset="0x2101" name="RB_2D_SRC_SOLID_DW0"/>
2752	<reg32 offset="0x2102" name="RB_2D_SRC_SOLID_DW1"/>
2753	<reg32 offset="0x2103" name="RB_2D_SRC_SOLID_DW2"/>
2754	<reg32 offset="0x2104" name="RB_2D_SRC_SOLID_DW3"/>
2755	<reg32 offset="0x2107" name="RB_2D_SRC_INFO">
2756		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2757		<bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2758		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2759		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2760		<bitfield name="FLAGS" pos="12" type="boolean"/>
2761	</reg32>
2762	<reg32 offset="0x2108" name="RB_2D_SRC_LO"/>
2763	<reg32 offset="0x2109" name="RB_2D_SRC_HI"/>
2764	<reg32 offset="0x210a" name="RB_2D_SRC_SIZE">
2765		<bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2766		<bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
2767	</reg32>
2768	<reg32 offset="0x2110" name="RB_2D_DST_INFO">
2769		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2770		<bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2771		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2772		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2773		<bitfield name="FLAGS" pos="12" type="boolean"/>
2774	</reg32>
2775	<reg32 offset="0x2111" name="RB_2D_DST_LO"/>
2776	<reg32 offset="0x2112" name="RB_2D_DST_HI"/>
2777	<reg32 offset="0x2113" name="RB_2D_DST_SIZE">
2778		<bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2779		<bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
2780	</reg32>
2781	<reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/>
2782	<reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/>
2783        <reg32 offset="0x2142" name="RB_2D_SRC_FLAGS_PITCH" shr="6" type="uint"/>
2784	<reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/>
2785	<reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/>
2786        <reg32 offset="0x2145" name="RB_2D_DST_FLAGS_PITCH" shr="6" type="uint"/>
2787	<reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
2788	<!-- looks same as 0x2107: -->
2789	<reg32 offset="0x2181" name="GRAS_2D_SRC_INFO">
2790		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2791		<bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2792		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2793		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2794		<bitfield name="FLAGS" pos="12" type="boolean"/>
2795	</reg32>
2796	<!-- looks same as 0x2110: -->
2797	<reg32 offset="0x2182" name="GRAS_2D_DST_INFO">
2798		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2799		<bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
2800		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2801		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2802		<bitfield name="FLAGS" pos="12" type="boolean"/>
2803	</reg32>
2804<!--
28050x2100 and 0x2180 look like same thing (RB and GRAS versions)..
2806   0x86000000 for copy, 0x00000000 for fill?
2807
28080x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???)
2809 -->
2810	<reg32 offset="0x2100" name="UNKNOWN_2100"/>
2811	<reg32 offset="0x2180" name="UNKNOWN_2180"/>
2812	<reg32 offset="0x2184" name="UNKNOWN_2184"/>
2813</domain>
2814
2815<domain name="A5XX_TEX_SAMP" width="32">
2816	<doc>Texture sampler dwords</doc>
2817	<enum name="a5xx_tex_filter"> <!-- same as a4xx? -->
2818		<value name="A5XX_TEX_NEAREST" value="0"/>
2819		<value name="A5XX_TEX_LINEAR" value="1"/>
2820		<value name="A5XX_TEX_ANISO" value="2"/>
2821	</enum>
2822	<enum name="a5xx_tex_clamp"> <!-- same as a4xx? -->
2823		<value name="A5XX_TEX_REPEAT" value="0"/>
2824		<value name="A5XX_TEX_CLAMP_TO_EDGE" value="1"/>
2825		<value name="A5XX_TEX_MIRROR_REPEAT" value="2"/>
2826		<value name="A5XX_TEX_CLAMP_TO_BORDER" value="3"/>
2827		<value name="A5XX_TEX_MIRROR_CLAMP" value="4"/>
2828	</enum>
2829	<enum name="a5xx_tex_aniso"> <!-- same as a4xx? -->
2830		<value name="A5XX_TEX_ANISO_1" value="0"/>
2831		<value name="A5XX_TEX_ANISO_2" value="1"/>
2832		<value name="A5XX_TEX_ANISO_4" value="2"/>
2833		<value name="A5XX_TEX_ANISO_8" value="3"/>
2834		<value name="A5XX_TEX_ANISO_16" value="4"/>
2835	</enum>
2836	<reg32 offset="0" name="0">
2837		<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
2838		<bitfield name="XY_MAG" low="1" high="2" type="a5xx_tex_filter"/>
2839		<bitfield name="XY_MIN" low="3" high="4" type="a5xx_tex_filter"/>
2840		<bitfield name="WRAP_S" low="5" high="7" type="a5xx_tex_clamp"/>
2841		<bitfield name="WRAP_T" low="8" high="10" type="a5xx_tex_clamp"/>
2842		<bitfield name="WRAP_R" low="11" high="13" type="a5xx_tex_clamp"/>
2843		<bitfield name="ANISO" low="14" high="16" type="a5xx_tex_aniso"/>
2844		<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
2845	</reg32>
2846	<reg32 offset="1" name="1">
2847		<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
2848		<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
2849		<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
2850		<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
2851		<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
2852		<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
2853	</reg32>
2854	<reg32 offset="2" name="2">
2855		<!--
2856		offset into border-color buffer?  Blob always uses 0x80 for FS state
2857		if both VS and FS have border-color.
2858Seems like when both VS and FS have bcolor, one starts 0x300 after other..
2859and 0x80 in TEX_SAMP.2 ..  blob doesn't seem to be able to cope w/ multiple
2860different border-color states per texture..  Looks something like:
28610000: 3f000000 00000000 00000000 3f800000 00008000 ffff0000 00004000 7fff0000
28620020: 00003800 3c000000 80100010 0000f008 ff000080 7f000040 c0000200 00800000
28630040: 00003800 3c000000 00000000 00000000 00000000 00000000 00000000 00000000
2864*
28650300: 3f800000 3f800000 3f800000 3f800000 ffffffff ffffffff 7fff7fff 7fff7fff
28660320: 3c003c00 3c003c00 ffffffff 0000ffff ffffffff 7f7f7f7f ffffffff 00ffffff
28670340: 3c003c00 3c003c00 00000000 00000000 00000000 00000000 00000000 00000000
2868
2869		 -->
2870		<bitfield name="BCOLOR_OFFSET" low="4" high="31"/>
2871	</reg32>
2872	<reg32 offset="3" name="3"/>
2873</domain>
2874
2875<domain name="A5XX_TEX_CONST" width="32">
2876	<doc>Texture constant dwords</doc>
2877	<enum name="a5xx_tex_swiz"> <!-- same as a4xx? -->
2878		<value name="A5XX_TEX_X" value="0"/>
2879		<value name="A5XX_TEX_Y" value="1"/>
2880		<value name="A5XX_TEX_Z" value="2"/>
2881		<value name="A5XX_TEX_W" value="3"/>
2882		<value name="A5XX_TEX_ZERO" value="4"/>
2883		<value name="A5XX_TEX_ONE" value="5"/>
2884	</enum>
2885	<enum name="a5xx_tex_type"> <!-- same as a4xx? -->
2886		<value name="A5XX_TEX_1D" value="0"/>
2887		<value name="A5XX_TEX_2D" value="1"/>
2888		<value name="A5XX_TEX_CUBE" value="2"/>
2889		<value name="A5XX_TEX_3D" value="3"/>
2890	</enum>
2891	<reg32 offset="0" name="0">
2892		<bitfield name="TILE_MODE" low="0" high="1" type="a5xx_tile_mode"/>
2893		<bitfield name="SRGB" pos="2" type="boolean"/>
2894		<bitfield name="SWIZ_X" low="4" high="6" type="a5xx_tex_swiz"/>
2895		<bitfield name="SWIZ_Y" low="7" high="9" type="a5xx_tex_swiz"/>
2896		<bitfield name="SWIZ_Z" low="10" high="12" type="a5xx_tex_swiz"/>
2897		<bitfield name="SWIZ_W" low="13" high="15" type="a5xx_tex_swiz"/>
2898		<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
2899		<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
2900		<bitfield name="FMT" low="22" high="29" type="a5xx_tex_fmt"/>
2901		<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
2902	</reg32>
2903	<reg32 offset="1" name="1">
2904		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
2905		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
2906	</reg32>
2907	<reg32 offset="2" name="2">
2908		<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
2909		<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
2910		<doc>Pitch in bytes (so actually stride)</doc>
2911		<bitfield name="PITCH" low="7" high="28" type="uint"/>
2912		<bitfield name="TYPE" low="29" high="30" type="a5xx_tex_type"/>
2913	</reg32>
2914	<reg32 offset="3" name="3">
2915		<!--
2916		ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
2917		for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
2918		layer size at the point that it stops being reduced moving to
2919		higher (smaller) mipmap levels
2920		 -->
2921		<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
2922		<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
2923		<!--
2924		by default levels with w < 16 are linear
2925		TILE_ALL makes all levels have tiling
2926		seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
2927		 -->
2928		<bitfield name="TILE_ALL" pos="27" type="boolean"/>
2929		<bitfield name="FLAG" pos="28" type="boolean"/>
2930	</reg32>
2931	<reg32 offset="4" name="4">
2932		<bitfield name="BASE_LO" low="5" high="31" shr="5"/>
2933	</reg32>
2934	<reg32 offset="5" name="5">
2935		<bitfield name="BASE_HI" low="0" high="16"/>
2936		<bitfield name="DEPTH" low="17" high="29" type="uint"/>
2937	</reg32>
2938	<reg32 offset="6" name="6"/>
2939	<reg32 offset="7" name="7"/>
2940	<reg32 offset="8" name="8"/>
2941	<reg32 offset="9" name="9"/>
2942	<reg32 offset="10" name="10"/>
2943	<reg32 offset="11" name="11"/>
2944</domain>
2945
2946<!--
2947Note the "SSBO" state blocks are actually used for both images and SSBOs,
2948naming is just because I r/e'd SSBOs first.  I should probably come up
2949with a better name.
2950-->
2951<domain name="A5XX_SSBO_0" width="32">
2952	<reg32 offset="0" name="0">
2953		<bitfield name="BASE_LO" low="5" high="31" shr="5"/>
2954	</reg32>
2955	<reg32 offset="1" name="1">
2956		<!-- no BASE_HI here?  Maybe this is only used for 32b mode? -->
2957		<doc>Pitch in bytes (so actually stride)</doc>
2958		<bitfield name="PITCH" low="0" high="21" type="uint"/>
2959	</reg32>
2960	<reg32 offset="2" name="2">
2961		<bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
2962	</reg32>
2963	<reg32 offset="3" name="3">
2964		<!-- bytes per pixel: -->
2965		<bitfield name="CPP" low="0" high="5" type="uint"/>
2966	</reg32>
2967</domain>
2968
2969<domain name="A5XX_SSBO_1" width="32">
2970	<reg32 offset="0" name="0">
2971		<bitfield name="FMT" low="8" high="15" type="a5xx_tex_fmt"/>
2972		<bitfield name="WIDTH" low="16" high="31" type="uint"/>
2973	</reg32>
2974	<reg32 offset="1" name="1">
2975		<bitfield name="HEIGHT" low="0" high="15" type="uint"/>
2976		<bitfield name="DEPTH" low="16" high="31" type="uint"/>
2977	</reg32>
2978</domain>
2979
2980<domain name="A5XX_SSBO_2" width="32">
2981	<reg32 offset="0" name="0">
2982		<bitfield name="BASE_LO" low="0" high="31"/>
2983	</reg32>
2984	<reg32 offset="1" name="1">
2985		<bitfield name="BASE_HI" low="0" high="31"/>
2986	</reg32>
2987</domain>
2988
2989<domain name="A5XX_UBO" width="32">
2990	<reg32 offset="0" name="0">
2991		<bitfield name="BASE_LO" low="0" high="31"/>
2992	</reg32>
2993	<reg32 offset="1" name="1">
2994		<bitfield name="BASE_HI" low="0" high="16"/>
2995		<!-- size probably in high bits -->
2996	</reg32>
2997</domain>
2998
2999</database>
3000