1 /*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef ART_COMPILER_UTILS_ARM64_ASSEMBLER_ARM64_H_
18 #define ART_COMPILER_UTILS_ARM64_ASSEMBLER_ARM64_H_
19
20 #include <stdint.h>
21 #include <memory>
22 #include <vector>
23
24 #include <android-base/logging.h>
25
26 #include "base/arena_containers.h"
27 #include "base/bit_utils_iterator.h"
28 #include "base/macros.h"
29 #include "dwarf/register.h"
30 #include "offsets.h"
31 #include "utils/arm64/managed_register_arm64.h"
32 #include "utils/assembler.h"
33
34 // TODO(VIXL): Make VIXL compile with -Wshadow.
35 #pragma GCC diagnostic push
36 #pragma GCC diagnostic ignored "-Wshadow"
37 #include "aarch64/disasm-aarch64.h"
38 #include "aarch64/macro-assembler-aarch64.h"
39 #pragma GCC diagnostic pop
40
41 namespace art {
42
43 class Arm64InstructionSetFeatures;
44
45 namespace arm64 {
46
DWARFReg(vixl::aarch64::CPURegister reg)47 static inline dwarf::Reg DWARFReg(vixl::aarch64::CPURegister reg) {
48 if (reg.IsFPRegister()) {
49 return dwarf::Reg::Arm64Fp(reg.GetCode());
50 } else {
51 DCHECK_LT(reg.GetCode(), 31u); // X0 - X30.
52 return dwarf::Reg::Arm64Core(reg.GetCode());
53 }
54 }
55
56 #define MEM_OP(...) vixl::aarch64::MemOperand(__VA_ARGS__)
57
58 enum LoadOperandType {
59 kLoadSignedByte,
60 kLoadUnsignedByte,
61 kLoadSignedHalfword,
62 kLoadUnsignedHalfword,
63 kLoadWord,
64 kLoadCoreWord,
65 kLoadSWord,
66 kLoadDWord
67 };
68
69 enum StoreOperandType {
70 kStoreByte,
71 kStoreHalfword,
72 kStoreWord,
73 kStoreCoreWord,
74 kStoreSWord,
75 kStoreDWord
76 };
77
78 class Arm64Assembler final : public Assembler {
79 public:
80 explicit Arm64Assembler(
81 ArenaAllocator* allocator, const Arm64InstructionSetFeatures* features = nullptr);
82
~Arm64Assembler()83 virtual ~Arm64Assembler() {}
84
GetVIXLAssembler()85 vixl::aarch64::MacroAssembler* GetVIXLAssembler() { return &vixl_masm_; }
86
87 // Finalize the code.
88 void FinalizeCode() override;
89
90 // Size of generated code.
91 size_t CodeSize() const override;
92 const uint8_t* CodeBufferBaseAddress() const override;
93
94 // Copy instructions out of assembly buffer into the given region of memory.
95 void FinalizeInstructions(const MemoryRegion& region) override;
96
97 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs);
98
99 void SpillRegisters(vixl::aarch64::CPURegList registers, int offset);
100 void UnspillRegisters(vixl::aarch64::CPURegList registers, int offset);
101
102 // A helper to save/restore a list of ZRegisters to a specified stack offset location.
103 template <bool is_save>
SaveRestoreZRegisterList(uint32_t vreg_bit_vector,int64_t stack_offset)104 void SaveRestoreZRegisterList(uint32_t vreg_bit_vector, int64_t stack_offset) {
105 if (vreg_bit_vector == 0) {
106 return;
107 }
108 vixl::aarch64::UseScratchRegisterScope temps(GetVIXLAssembler());
109 vixl::aarch64::Register temp = temps.AcquireX();
110 vixl_masm_.Add(temp, vixl::aarch64::sp, stack_offset);
111 size_t slot_no = 0;
112 for (uint32_t i : LowToHighBits(vreg_bit_vector)) {
113 if (is_save) {
114 vixl_masm_.Str(vixl::aarch64::ZRegister(i),
115 vixl::aarch64::SVEMemOperand(temp, slot_no, vixl::aarch64::SVE_MUL_VL));
116 } else {
117 vixl_masm_.Ldr(vixl::aarch64::ZRegister(i),
118 vixl::aarch64::SVEMemOperand(temp, slot_no, vixl::aarch64::SVE_MUL_VL));
119 }
120 slot_no++;
121 }
122 }
123
124 // Jump to address (not setting link register)
125 void JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch);
126
127 //
128 // Heap poisoning.
129 //
130
131 // Poison a heap reference contained in `reg`.
132 void PoisonHeapReference(vixl::aarch64::Register reg);
133 // Unpoison a heap reference contained in `reg`.
134 void UnpoisonHeapReference(vixl::aarch64::Register reg);
135 // Poison a heap reference contained in `reg` if heap poisoning is enabled.
136 void MaybePoisonHeapReference(vixl::aarch64::Register reg);
137 // Unpoison a heap reference contained in `reg` if heap poisoning is enabled.
138 void MaybeUnpoisonHeapReference(vixl::aarch64::Register reg);
139
140 // Emit code checking the status of the Marking Register, and aborting
141 // the program if MR does not match the value stored in the art::Thread
142 // object.
143 //
144 // Argument `temp` is used as a temporary register to generate code.
145 // Argument `code` is used to identify the different occurrences of
146 // MaybeGenerateMarkingRegisterCheck and is passed to the BRK instruction.
147 void GenerateMarkingRegisterCheck(vixl::aarch64::Register temp, int code = 0);
148
Bind(Label * label ATTRIBUTE_UNUSED)149 void Bind(Label* label ATTRIBUTE_UNUSED) override {
150 UNIMPLEMENTED(FATAL) << "Do not use Bind(Label*) for ARM64";
151 }
Jump(Label * label ATTRIBUTE_UNUSED)152 void Jump(Label* label ATTRIBUTE_UNUSED) override {
153 UNIMPLEMENTED(FATAL) << "Do not use Jump(Label*) for ARM64";
154 }
155
Bind(vixl::aarch64::Label * label)156 void Bind(vixl::aarch64::Label* label) {
157 vixl_masm_.Bind(label);
158 }
Jump(vixl::aarch64::Label * label)159 void Jump(vixl::aarch64::Label* label) {
160 vixl_masm_.B(label);
161 }
162
reg_x(int code)163 static vixl::aarch64::Register reg_x(int code) {
164 CHECK(code < kNumberOfXRegisters) << code;
165 if (code == SP) {
166 return vixl::aarch64::sp;
167 } else if (code == XZR) {
168 return vixl::aarch64::xzr;
169 }
170 return vixl::aarch64::XRegister(code);
171 }
172
reg_w(int code)173 static vixl::aarch64::Register reg_w(int code) {
174 CHECK(code < kNumberOfWRegisters) << code;
175 if (code == WSP) {
176 return vixl::aarch64::wsp;
177 } else if (code == WZR) {
178 return vixl::aarch64::wzr;
179 }
180 return vixl::aarch64::WRegister(code);
181 }
182
reg_d(int code)183 static vixl::aarch64::VRegister reg_d(int code) {
184 return vixl::aarch64::DRegister(code);
185 }
186
reg_s(int code)187 static vixl::aarch64::VRegister reg_s(int code) {
188 return vixl::aarch64::SRegister(code);
189 }
190
191 private:
192 // VIXL assembler.
193 vixl::aarch64::MacroAssembler vixl_masm_;
194
195 // Used for testing.
196 friend class Arm64ManagedRegister_VixlRegisters_Test;
197 };
198
199 } // namespace arm64
200 } // namespace art
201
202 #endif // ART_COMPILER_UTILS_ARM64_ASSEMBLER_ARM64_H_
203