1 /* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef BRW_PIPE_CONTROL_DOT_H 25 #define BRW_PIPE_CONTROL_DOT_H 26 27 struct brw_context; 28 struct gen_device_info; 29 struct brw_bo; 30 31 /** @{ 32 * 33 * PIPE_CONTROL operation, a combination MI_FLUSH and register write with 34 * additional flushing control. 35 * 36 * The bits here are not the actual hardware values. The actual values 37 * shift around a bit per-generation, so we just have flags for each 38 * potential operation, and use genxml to encode the actual packet. 39 */ 40 enum pipe_control_flags 41 { 42 PIPE_CONTROL_FLUSH_LLC = (1 << 1), 43 PIPE_CONTROL_LRI_POST_SYNC_OP = (1 << 2), 44 PIPE_CONTROL_STORE_DATA_INDEX = (1 << 3), 45 PIPE_CONTROL_CS_STALL = (1 << 4), 46 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET = (1 << 5), 47 PIPE_CONTROL_SYNC_GFDT = (1 << 6), 48 PIPE_CONTROL_TLB_INVALIDATE = (1 << 7), 49 PIPE_CONTROL_MEDIA_STATE_CLEAR = (1 << 8), 50 PIPE_CONTROL_WRITE_IMMEDIATE = (1 << 9), 51 PIPE_CONTROL_WRITE_DEPTH_COUNT = (1 << 10), 52 PIPE_CONTROL_WRITE_TIMESTAMP = (1 << 11), 53 PIPE_CONTROL_DEPTH_STALL = (1 << 12), 54 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13), 55 PIPE_CONTROL_INSTRUCTION_INVALIDATE = (1 << 14), 56 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15), 57 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16), 58 PIPE_CONTROL_NOTIFY_ENABLE = (1 << 17), 59 PIPE_CONTROL_FLUSH_ENABLE = (1 << 18), 60 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), 61 PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20), 62 PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21), 63 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), 64 PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23), 65 PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24), 66 }; 67 68 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ 69 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \ 70 PIPE_CONTROL_RENDER_TARGET_FLUSH) 71 72 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ 73 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \ 74 PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ 75 PIPE_CONTROL_INSTRUCTION_INVALIDATE) 76 77 /** @} */ 78 79 int brw_init_pipe_control(struct brw_context *brw, 80 const struct gen_device_info *info); 81 void brw_fini_pipe_control(struct brw_context *brw); 82 83 void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags); 84 void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, 85 struct brw_bo *bo, uint32_t offset, 86 uint64_t imm); 87 void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags); 88 void brw_emit_mi_flush(struct brw_context *brw); 89 void brw_emit_post_sync_nonzero_flush(struct brw_context *brw); 90 void brw_emit_depth_stall_flushes(struct brw_context *brw); 91 void gen7_emit_vs_workaround_flush(struct brw_context *brw); 92 void gen7_emit_cs_stall_flush(struct brw_context *brw); 93 void gen7_emit_isp_disable(struct brw_context *brw); 94 95 #endif 96