1 /* 2 * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CPG_REGISTERS_H 8 #define CPG_REGISTERS_H 9 10 /* CPG base address */ 11 #define CPG_BASE (0xE6150000U) 12 13 /* CPG system module stop control 2 */ 14 #define CPG_SMSTPCR2 (CPG_BASE + 0x0138U) 15 /* CPG software reset 2 */ 16 #define CPG_SRCR2 (CPG_BASE + 0x00B0U) 17 /* CPG module stop status 2 */ 18 #define CPG_MSTPSR2 (CPG_BASE + 0x0040U) 19 /* CPG write protect */ 20 #define CPG_CPGWPR (CPG_BASE + 0x0900U) 21 /* CPG write protect control */ 22 #define CPG_CPGWPCR (CPG_BASE + 0x0904U) 23 /* CPG system module stop control 9 */ 24 #define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) 25 /* CPG module stop status 9 */ 26 #define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) 27 28 /* CPG (SECURITY) registers */ 29 30 /* Secure Module Stop Control Register 0 */ 31 #define SCMSTPCR0 (CPG_BASE + 0x0B20U) 32 /* Secure Module Stop Control Register 1 */ 33 #define SCMSTPCR1 (CPG_BASE + 0x0B24U) 34 /* Secure Module Stop Control Register 2 */ 35 #define SCMSTPCR2 (CPG_BASE + 0x0B28U) 36 /* Secure Module Stop Control Register 3 */ 37 #define SCMSTPCR3 (CPG_BASE + 0x0B2CU) 38 /* Secure Module Stop Control Register 4 */ 39 #define SCMSTPCR4 (CPG_BASE + 0x0B30U) 40 /* Secure Module Stop Control Register 5 */ 41 #define SCMSTPCR5 (CPG_BASE + 0x0B34U) 42 /* Secure Module Stop Control Register 6 */ 43 #define SCMSTPCR6 (CPG_BASE + 0x0B38U) 44 /* Secure Module Stop Control Register 7 */ 45 #define SCMSTPCR7 (CPG_BASE + 0x0B3CU) 46 /* Secure Module Stop Control Register 8 */ 47 #define SCMSTPCR8 (CPG_BASE + 0x0B40U) 48 /* Secure Module Stop Control Register 9 */ 49 #define SCMSTPCR9 (CPG_BASE + 0x0B44U) 50 /* Secure Module Stop Control Register 10 */ 51 #define SCMSTPCR10 (CPG_BASE + 0x0B48U) 52 /* Secure Module Stop Control Register 11 */ 53 #define SCMSTPCR11 (CPG_BASE + 0x0B4CU) 54 55 /* CPG (SECURITY) registers */ 56 57 /* Secure Software Reset Access Enable Control Register 0 */ 58 #define SCSRSTECR0 (CPG_BASE + 0x0B80U) 59 /* Secure Software Reset Access Enable Control Register 1 */ 60 #define SCSRSTECR1 (CPG_BASE + 0x0B84U) 61 /* Secure Software Reset Access Enable Control Register 2 */ 62 #define SCSRSTECR2 (CPG_BASE + 0x0B88U) 63 /* Secure Software Reset Access Enable Control Register 3 */ 64 #define SCSRSTECR3 (CPG_BASE + 0x0B8CU) 65 /* Secure Software Reset Access Enable Control Register 4 */ 66 #define SCSRSTECR4 (CPG_BASE + 0x0B90U) 67 /* Secure Software Reset Access Enable Control Register 5 */ 68 #define SCSRSTECR5 (CPG_BASE + 0x0B94U) 69 /* Secure Software Reset Access Enable Control Register 6 */ 70 #define SCSRSTECR6 (CPG_BASE + 0x0B98U) 71 /* Secure Software Reset Access Enable Control Register 7 */ 72 #define SCSRSTECR7 (CPG_BASE + 0x0B9CU) 73 /* Secure Software Reset Access Enable Control Register 8 */ 74 #define SCSRSTECR8 (CPG_BASE + 0x0BA0U) 75 /* Secure Software Reset Access Enable Control Register 9 */ 76 #define SCSRSTECR9 (CPG_BASE + 0x0BA4U) 77 /* Secure Software Reset Access Enable Control Register 10 */ 78 #define SCSRSTECR10 (CPG_BASE + 0x0BA8U) 79 /* Secure Software Reset Access Enable Control Register 11 */ 80 #define SCSRSTECR11 (CPG_BASE + 0x0BACU) 81 82 /* CPG (REALTIME) registers */ 83 84 /* Realtime Module Stop Control Register 0 */ 85 #define RMSTPCR0 (CPG_BASE + 0x0110U) 86 /* Realtime Module Stop Control Register 1 */ 87 #define RMSTPCR1 (CPG_BASE + 0x0114U) 88 /* Realtime Module Stop Control Register 2 */ 89 #define RMSTPCR2 (CPG_BASE + 0x0118U) 90 /* Realtime Module Stop Control Register 3 */ 91 #define RMSTPCR3 (CPG_BASE + 0x011CU) 92 /* Realtime Module Stop Control Register 4 */ 93 #define RMSTPCR4 (CPG_BASE + 0x0120U) 94 /* Realtime Module Stop Control Register 5 */ 95 #define RMSTPCR5 (CPG_BASE + 0x0124U) 96 /* Realtime Module Stop Control Register 6 */ 97 #define RMSTPCR6 (CPG_BASE + 0x0128U) 98 /* Realtime Module Stop Control Register 7 */ 99 #define RMSTPCR7 (CPG_BASE + 0x012CU) 100 /* Realtime Module Stop Control Register 8 */ 101 #define RMSTPCR8 (CPG_BASE + 0x0980U) 102 /* Realtime Module Stop Control Register 9 */ 103 #define RMSTPCR9 (CPG_BASE + 0x0984U) 104 /* Realtime Module Stop Control Register 10 */ 105 #define RMSTPCR10 (CPG_BASE + 0x0988U) 106 /* Realtime Module Stop Control Register 11 */ 107 #define RMSTPCR11 (CPG_BASE + 0x098CU) 108 109 /* CPG (SYSTEM) registers */ 110 111 /* System Module Stop Control Register 0 */ 112 #define SMSTPCR0 (CPG_BASE + 0x0130U) 113 /* System Module Stop Control Register 1 */ 114 #define SMSTPCR1 (CPG_BASE + 0x0134U) 115 /* System Module Stop Control Register 2 */ 116 #define SMSTPCR2 (CPG_BASE + 0x0138U) 117 /* System Module Stop Control Register 3 */ 118 #define SMSTPCR3 (CPG_BASE + 0x013CU) 119 /* System Module Stop Control Register 4 */ 120 #define SMSTPCR4 (CPG_BASE + 0x0140U) 121 /* System Module Stop Control Register 5 */ 122 #define SMSTPCR5 (CPG_BASE + 0x0144U) 123 /* System Module Stop Control Register 6 */ 124 #define SMSTPCR6 (CPG_BASE + 0x0148U) 125 /* System Module Stop Control Register 7 */ 126 #define SMSTPCR7 (CPG_BASE + 0x014CU) 127 /* System Module Stop Control Register 8 */ 128 #define SMSTPCR8 (CPG_BASE + 0x0990U) 129 /* System Module Stop Control Register 9 */ 130 #define SMSTPCR9 (CPG_BASE + 0x0994U) 131 /* System Module Stop Control Register 10 */ 132 #define SMSTPCR10 (CPG_BASE + 0x0998U) 133 /* System Module Stop Control Register 11 */ 134 #define SMSTPCR11 (CPG_BASE + 0x099CU) 135 136 #endif /* CPG_REGISTERS_H */ 137