1; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s 2 3define i64 @dext_add_zext(i32 signext %n) { 4entry: 5 %add = add i32 %n, 1 6 %res = zext i32 %add to i64 7 ret i64 %res 8 9; CHECK-LABEL: dext_add_zext: 10; CHECK: dext $[[R0:[0-9]+]], $[[R0:[0-9]+]], 0, 32 11 12} 13 14define i32 @ext_and24(i32 signext %a) { 15entry: 16 %and = and i32 %a, 16777215 17 ret i32 %and 18 19; CHECK-LABEL: ext_and24: 20; CHECK: ext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 24 21 22} 23 24define i64 @dext_and32(i64 zeroext %a) { 25entry: 26 %and = and i64 %a, 4294967295 27 ret i64 %and 28 29; CHECK-LABEL: dext_and32: 30; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32 31 32} 33 34define i64 @dext_and35(i64 zeroext %a) { 35entry: 36 %and = and i64 %a, 34359738367 37 ret i64 %and 38 39; CHECK-LABEL: dext_and35: 40; CHECK: dextm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 35 41 42} 43 44define i64 @dext_and20(i64 zeroext %a) { 45entry: 46 %and = and i64 %a, 1048575 47 ret i64 %and 48 49; CHECK-LABEL: dext_and20: 50; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 20 51 52} 53 54define i64 @dext_and16(i64 zeroext %a) { 55entry: 56 %and = and i64 %a, 65535 57 ret i64 %and 58 59; CHECK-LABEL: dext_and16: 60; CHECK: andi $[[R0:[0-9]+]], $[[R1:[0-9]+]], 65535 61 62} 63 64define i64 @dext_lsr_and20(i64 zeroext %a) { 65entry: 66 %shr = lshr i64 %a, 5 67 %and = and i64 %shr, 1048575 68 ret i64 %and 69 70; CHECK-LABEL: dext_lsr_and20: 71; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 20 72 73} 74 75define i64 @dext_lsr_and8(i64 zeroext %a) { 76entry: 77 %shr = lshr i64 %a, 40 78 %and = and i64 %shr, 255 79 ret i64 %and 80 81; CHECK-LABEL: dext_lsr_and8: 82; CHECK: dextu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 40, 8 83 84} 85 86define i64 @dext_zext(i32 signext %a) { 87entry: 88 %conv = zext i32 %a to i64 89 ret i64 %conv 90 91; CHECK-LABEL: dext_zext: 92; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32 93 94} 95 96define i64 @dext_and_lsr(i64 zeroext %n) { 97entry: 98 %and = lshr i64 %n, 8 99 %shr = and i64 %and, 4095 100 ret i64 %shr 101 102; CHECK-LABEL: dext_and_lsr: 103; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 12 104 105} 106