1 //===-- Optimizer/Transforms/Passes.h ---------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef OPTIMIZER_TRANSFORMS_PASSES_H 10 #define OPTIMIZER_TRANSFORMS_PASSES_H 11 12 #include "mlir/Pass/Pass.h" 13 #include "mlir/Pass/PassRegistry.h" 14 #include <memory> 15 16 namespace mlir { 17 class BlockAndValueMapping; 18 class Operation; 19 class Pass; 20 class Region; 21 } // namespace mlir 22 23 namespace fir { 24 25 /// Convert fir.select_type to the standard dialect 26 std::unique_ptr<mlir::Pass> createControlFlowLoweringPass(); 27 28 /// Effects aware CSE pass 29 std::unique_ptr<mlir::Pass> createCSEPass(); 30 31 /// Convert FIR loop constructs to the Affine dialect 32 std::unique_ptr<mlir::Pass> createPromoteToAffinePass(); 33 34 /// Convert `fir.do_loop` and `fir.if` to a CFG. This 35 /// conversion enables the `createLowerToCFGPass` to transform these to CFG 36 /// form. 37 std::unique_ptr<mlir::Pass> createFirToCfgPass(); 38 39 /// A pass to convert the FIR dialect from "Mem-SSA" form to "Reg-SSA" 40 /// form. This pass is a port of LLVM's mem2reg pass, but modified for the FIR 41 /// dialect as well as the restructuring of MLIR's representation to present PHI 42 /// nodes as block arguments. 43 std::unique_ptr<mlir::Pass> createMemToRegPass(); 44 45 /// Support for inlining on FIR. 46 bool canLegallyInline(mlir::Operation *op, mlir::Region *reg, 47 mlir::BlockAndValueMapping &map); 48 49 // declarative passes 50 #define GEN_PASS_REGISTRATION 51 #include "flang/Optimizer/Transforms/Passes.h.inc" 52 53 } // namespace fir 54 55 #endif // OPTIMIZER_TRANSFORMS_PASSES_H 56