1 /*
2 * Copyright (c) 2019, ARM Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef GIC600_MULTICHIP_PRIVATE_H
8 #define GIC600_MULTICHIP_PRIVATE_H
9
10 #include <drivers/arm/gic600_multichip.h>
11
12 #include "gicv3_private.h"
13
14 /* GIC600 GICD multichip related offsets */
15 #define GICD_CHIPSR U(0xC000)
16 #define GICD_DCHIPR U(0xC004)
17 #define GICD_CHIPR U(0xC008)
18
19 /* GIC600 GICD multichip related masks */
20 #define GICD_CHIPRx_PUP_BIT BIT_64(1)
21 #define GICD_CHIPRx_SOCKET_STATE BIT_64(0)
22 #define GICD_DCHIPR_PUP_BIT BIT_32(0)
23 #define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5))
24
25 /* GIC600 GICD multichip related shifts */
26 #define GICD_CHIPRx_ADDR_SHIFT 16
27 #define GICD_CHIPSR_RTS_SHIFT 4
28 #define GICD_DCHIPR_RT_OWNER_SHIFT 4
29
30 /*
31 * If GIC v4 extension is enabled, then use SPI macros specific to GIC-Clayton.
32 * Other shifts and mask remains same between GIC-600 and GIC-Clayton.
33 */
34 #if GIC_ENABLE_V4_EXTN
35 #define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 9
36 #define GICD_CHIPRx_SPI_BLOCKS_SHIFT 3
37 #else
38 #define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10
39 #define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5
40 #endif
41
42 #define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0)
43 #define GICD_CHIPSR_RTS_STATE_UPDATING U(1)
44 #define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2)
45
46 /* SPI interrupt id minimum and maximum range */
47 #define GIC600_SPI_ID_MIN 32
48 #define GIC600_SPI_ID_MAX 960
49
50 /* Number of retries for PUP update */
51 #define GICD_PUP_UPDATE_RETRIES 10000
52
53 #define SPI_MIN_INDEX 0
54 #define SPI_MAX_INDEX 1
55
56 #define SPI_BLOCK_MIN_VALUE(spi_id_min) \
57 (((spi_id_min) - GIC600_SPI_ID_MIN) / \
58 GIC600_SPI_ID_MIN)
59 #define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \
60 (((spi_id_max) - (spi_id_min) + 1) / \
61 GIC600_SPI_ID_MIN)
62 #define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \
63 (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \
64 ((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \
65 ((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT))
66
67 /*
68 * Multichip data assertion macros
69 */
70 /* Set bits from 0 to ((spi_id_max + 1) / 32) */
71 #define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1)
72 /* Set bits from 0 to (spi_id_min / 32) */
73 #define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1)
74 /* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */
75 #define BLOCKS_OF_32(spi_id_min, spi_id_max) \
76 SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \
77 SPI_BLOCKS_TILL_MIN(spi_id_min)
78
79 /*******************************************************************************
80 * GIC-600 multichip operation related helper functions
81 ******************************************************************************/
read_gicd_dchipr(uintptr_t base)82 static inline uint32_t read_gicd_dchipr(uintptr_t base)
83 {
84 return mmio_read_32(base + GICD_DCHIPR);
85 }
86
read_gicd_chipr_n(uintptr_t base,uint8_t n)87 static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n)
88 {
89 return mmio_read_64(base + (GICD_CHIPR + (8U * n)));
90 }
91
read_gicd_chipsr(uintptr_t base)92 static inline uint32_t read_gicd_chipsr(uintptr_t base)
93 {
94 return mmio_read_32(base + GICD_CHIPSR);
95 }
96
write_gicd_dchipr(uintptr_t base,uint32_t val)97 static inline void write_gicd_dchipr(uintptr_t base, uint32_t val)
98 {
99 mmio_write_32(base + GICD_DCHIPR, val);
100 }
101
write_gicd_chipr_n(uintptr_t base,uint8_t n,uint64_t val)102 static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val)
103 {
104 mmio_write_64(base + (GICD_CHIPR + (8U * n)), val);
105 }
106
107 #endif /* GIC600_MULTICHIP_PRIVATE_H */
108