1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*****************************************************************************/
22 /* */
23 /* File Name : ih264d_api.c */
24 /* */
25 /* Description : Has all API related functions */
26 /* */
27 /* */
28 /* List of Functions : api_check_struct_sanity */
29 /* ih264d_set_processor */
30 /* ih264d_create */
31 /* ih264d_delete */
32 /* ih264d_init */
33 /* ih264d_map_error */
34 /* ih264d_video_decode */
35 /* ih264d_get_version */
36 /* ih264d_get_display_frame */
37 /* ih264d_set_display_frame */
38 /* ih264d_set_flush_mode */
39 /* ih264d_get_status */
40 /* ih264d_get_buf_info */
41 /* ih264d_set_params */
42 /* ih264d_set_default_params */
43 /* ih264d_reset */
44 /* ih264d_ctl */
45 /* ih264d_rel_display_frame */
46 /* ih264d_set_degrade */
47 /* ih264d_get_frame_dimensions */
48 /* ih264d_set_num_cores */
49 /* ih264d_fill_output_struct_from_context */
50 /* ih264d_api_function */
51 /* */
52 /* Issues / Problems : None */
53 /* */
54 /* Revision History : */
55 /* */
56 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
57 /* 14 10 2008 100356(SKV) Draft */
58 /* */
59 /*****************************************************************************/
60 #include "ih264_typedefs.h"
61 #include "ih264_macros.h"
62 #include "ih264_platform_macros.h"
63 #include "ih264d_tables.h"
64 #include "iv.h"
65 #include "ivd.h"
66 #include "ih264d.h"
67 #include "ih264d_defs.h"
68
69 #include <string.h>
70 #include <limits.h>
71 #include <stddef.h>
72
73 #include "ih264d_inter_pred.h"
74
75 #include "ih264d_structs.h"
76 #include "ih264d_nal.h"
77 #include "ih264d_error_handler.h"
78
79 #include "ih264d_defs.h"
80
81 #include "ithread.h"
82 #include "ih264d_parse_slice.h"
83 #include "ih264d_function_selector.h"
84 #include "ih264_error.h"
85 #include "ih264_disp_mgr.h"
86 #include "ih264_buf_mgr.h"
87 #include "ih264d_deblocking.h"
88 #include "ih264d_parse_cavlc.h"
89 #include "ih264d_parse_cabac.h"
90 #include "ih264d_utils.h"
91 #include "ih264d_format_conv.h"
92 #include "ih264d_parse_headers.h"
93 #include "ih264d_thread_compute_bs.h"
94 #include <assert.h>
95
96
97 /*********************/
98 /* Codec Versioning */
99 /*********************/
100 //Move this to where it is used
101 #define CODEC_NAME "H264VDEC"
102 #define CODEC_RELEASE_TYPE "production"
103 #define CODEC_RELEASE_VER "05.00"
104 #define CODEC_VENDOR "ITTIAM"
105 #define MAXVERSION_STRLEN 511
106 #ifdef ANDROID
107 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
108 snprintf(version_string, MAXVERSION_STRLEN, \
109 "@(#)Id:%s_%s Ver:%s Released by %s", \
110 codec_name, codec_release_type, codec_release_ver, codec_vendor)
111 #else
112 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
113 snprintf(version_string, MAXVERSION_STRLEN, \
114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \
115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
116 #endif
117
118
119 #define MIN_IN_BUFS 1
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125 #define NUM_FRAMES_LIMIT_ENABLED 0
126
127 #if NUM_FRAMES_LIMIT_ENABLED
128 #define NUM_FRAMES_LIMIT 10000
129 #else
130 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
131 #endif
132
133
134 UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136 void *pv_api_ip,
137 void *pv_api_op);
138 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
139 void *pv_api_ip,
140 void *pv_api_op);
141
142 WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
143 void *pv_api_ip,
144 void *pv_api_op);
145
146 WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
147 void *pv_api_ip,
148 void *pv_api_op);
149
150 WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
151 void *pv_api_ip,
152 void *pv_api_op);
153
154 WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
155 void *pv_api_ip,
156 void *pv_api_op);
157
158 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
159
160 WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
161
162 void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
163
164 void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
165 void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
166
167 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
168 void *pv_api_ip,
169 void *pv_api_op);
170
171 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
172 ivd_video_decode_op_t *ps_dec_op);
173
174 /*!
175 **************************************************************************
176 * \if Function name : ih264d_export_sei_params \endif
177 *
178 * \brief
179 * Exports sei params from decoder to application.
180 *
181 * \return
182 * 0 on Success and error code otherwise
183 **************************************************************************
184 */
185
ih264d_export_sei_params(ivd_sei_decode_op_t * ps_sei_decode_op,dec_struct_t * ps_dec)186 void ih264d_export_sei_params(ivd_sei_decode_op_t *ps_sei_decode_op, dec_struct_t *ps_dec)
187 {
188 WORD32 i4_status = IV_SUCCESS;
189 sei *ps_sei = (sei *)ps_dec->pv_disp_sei_params;
190
191 i4_status = ih264d_export_sei_mdcv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
192 i4_status = ih264d_export_sei_cll_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
193 i4_status = ih264d_export_sei_ave_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
194 i4_status = ih264d_export_sei_ccv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
195
196 UNUSED(i4_status);
197 }
198
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)199 static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
200 void *pv_api_ip,
201 void *pv_api_op)
202 {
203 IVD_API_COMMAND_TYPE_T e_cmd;
204 UWORD32 *pu4_api_ip;
205 UWORD32 *pu4_api_op;
206 UWORD32 i, j;
207
208 if(NULL == pv_api_op)
209 return (IV_FAIL);
210
211 if(NULL == pv_api_ip)
212 return (IV_FAIL);
213
214 pu4_api_ip = (UWORD32 *)pv_api_ip;
215 pu4_api_op = (UWORD32 *)pv_api_op;
216 e_cmd = *(pu4_api_ip + 1);
217
218 /* error checks on handle */
219 switch((WORD32)e_cmd)
220 {
221 case IVD_CMD_CREATE:
222 break;
223
224 case IVD_CMD_REL_DISPLAY_FRAME:
225 case IVD_CMD_SET_DISPLAY_FRAME:
226 case IVD_CMD_GET_DISPLAY_FRAME:
227 case IVD_CMD_VIDEO_DECODE:
228 case IVD_CMD_DELETE:
229 case IVD_CMD_VIDEO_CTL:
230 if(ps_handle == NULL)
231 {
232 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
233 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
234 return IV_FAIL;
235 }
236
237 if(ps_handle->u4_size != sizeof(iv_obj_t))
238 {
239 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
240 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
241 return IV_FAIL;
242 }
243
244 if(ps_handle->pv_fxns != ih264d_api_function)
245 {
246 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
247 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
248 return IV_FAIL;
249 }
250
251 if(ps_handle->pv_codec_handle == NULL)
252 {
253 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
254 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
255 return IV_FAIL;
256 }
257 break;
258 default:
259 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
260 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
261 return IV_FAIL;
262 }
263
264 switch((WORD32)e_cmd)
265 {
266 case IVD_CMD_CREATE:
267 {
268 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip;
269 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op;
270
271
272 ps_op->s_ivd_create_op_t.u4_error_code = 0;
273
274 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t))
275 || (ps_ip->s_ivd_create_ip_t.u4_size
276 < sizeof(ivd_create_ip_t)))
277 {
278 ps_op->s_ivd_create_op_t.u4_error_code |= 1
279 << IVD_UNSUPPORTEDPARAM;
280 ps_op->s_ivd_create_op_t.u4_error_code |=
281 IVD_IP_API_STRUCT_SIZE_INCORRECT;
282 H264_DEC_DEBUG_PRINT("\n");
283 return (IV_FAIL);
284 }
285
286 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t))
287 && (ps_op->s_ivd_create_op_t.u4_size
288 != sizeof(ivd_create_op_t)))
289 {
290 ps_op->s_ivd_create_op_t.u4_error_code |= 1
291 << IVD_UNSUPPORTEDPARAM;
292 ps_op->s_ivd_create_op_t.u4_error_code |=
293 IVD_OP_API_STRUCT_SIZE_INCORRECT;
294 H264_DEC_DEBUG_PRINT("\n");
295 return (IV_FAIL);
296 }
297
298
299 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P)
300 && (ps_ip->s_ivd_create_ip_t.e_output_format
301 != IV_YUV_422ILE)
302 && (ps_ip->s_ivd_create_ip_t.e_output_format
303 != IV_RGB_565)
304 && (ps_ip->s_ivd_create_ip_t.e_output_format
305 != IV_YUV_420SP_UV)
306 && (ps_ip->s_ivd_create_ip_t.e_output_format
307 != IV_YUV_420SP_VU))
308 {
309 ps_op->s_ivd_create_op_t.u4_error_code |= 1
310 << IVD_UNSUPPORTEDPARAM;
311 ps_op->s_ivd_create_op_t.u4_error_code |=
312 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
313 H264_DEC_DEBUG_PRINT("\n");
314 return (IV_FAIL);
315 }
316
317 }
318 break;
319
320 case IVD_CMD_GET_DISPLAY_FRAME:
321 {
322 ih264d_get_display_frame_ip_t *ps_ip =
323 (ih264d_get_display_frame_ip_t *)pv_api_ip;
324 ih264d_get_display_frame_op_t *ps_op =
325 (ih264d_get_display_frame_op_t *)pv_api_op;
326
327 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
328
329 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
330 != sizeof(ih264d_get_display_frame_ip_t))
331 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
332 != sizeof(ivd_get_display_frame_ip_t)))
333 {
334 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
335 << IVD_UNSUPPORTEDPARAM;
336 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
337 IVD_IP_API_STRUCT_SIZE_INCORRECT;
338 return (IV_FAIL);
339 }
340
341 if((ps_op->s_ivd_get_display_frame_op_t.u4_size
342 != sizeof(ih264d_get_display_frame_op_t))
343 && (ps_op->s_ivd_get_display_frame_op_t.u4_size
344 != sizeof(ivd_get_display_frame_op_t)))
345 {
346 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
347 << IVD_UNSUPPORTEDPARAM;
348 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
349 IVD_OP_API_STRUCT_SIZE_INCORRECT;
350 return (IV_FAIL);
351 }
352 }
353 break;
354
355 case IVD_CMD_REL_DISPLAY_FRAME:
356 {
357 ih264d_rel_display_frame_ip_t *ps_ip =
358 (ih264d_rel_display_frame_ip_t *)pv_api_ip;
359 ih264d_rel_display_frame_op_t *ps_op =
360 (ih264d_rel_display_frame_op_t *)pv_api_op;
361
362 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
363
364 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
365 != sizeof(ih264d_rel_display_frame_ip_t))
366 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
367 != sizeof(ivd_rel_display_frame_ip_t)))
368 {
369 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
370 << IVD_UNSUPPORTEDPARAM;
371 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
372 IVD_IP_API_STRUCT_SIZE_INCORRECT;
373 return (IV_FAIL);
374 }
375
376 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
377 != sizeof(ih264d_rel_display_frame_op_t))
378 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
379 != sizeof(ivd_rel_display_frame_op_t)))
380 {
381 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
382 << IVD_UNSUPPORTEDPARAM;
383 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
384 IVD_OP_API_STRUCT_SIZE_INCORRECT;
385 return (IV_FAIL);
386 }
387
388 }
389 break;
390
391 case IVD_CMD_SET_DISPLAY_FRAME:
392 {
393 ih264d_set_display_frame_ip_t *ps_ip =
394 (ih264d_set_display_frame_ip_t *)pv_api_ip;
395 ih264d_set_display_frame_op_t *ps_op =
396 (ih264d_set_display_frame_op_t *)pv_api_op;
397 UWORD32 j;
398
399 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
400
401 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
402 != sizeof(ih264d_set_display_frame_ip_t))
403 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
404 != sizeof(ivd_set_display_frame_ip_t)))
405 {
406 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
407 << IVD_UNSUPPORTEDPARAM;
408 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
409 IVD_IP_API_STRUCT_SIZE_INCORRECT;
410 return (IV_FAIL);
411 }
412
413 if((ps_op->s_ivd_set_display_frame_op_t.u4_size
414 != sizeof(ih264d_set_display_frame_op_t))
415 && (ps_op->s_ivd_set_display_frame_op_t.u4_size
416 != sizeof(ivd_set_display_frame_op_t)))
417 {
418 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
419 << IVD_UNSUPPORTEDPARAM;
420 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
421 IVD_OP_API_STRUCT_SIZE_INCORRECT;
422 return (IV_FAIL);
423 }
424
425 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
426 {
427 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
428 << IVD_UNSUPPORTEDPARAM;
429 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
430 IVD_DISP_FRM_ZERO_OP_BUFS;
431 return IV_FAIL;
432 }
433
434 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
435 j++)
436 {
437 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
438 == 0)
439 {
440 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
441 << IVD_UNSUPPORTEDPARAM;
442 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
443 IVD_DISP_FRM_ZERO_OP_BUFS;
444 return IV_FAIL;
445 }
446
447 for(i = 0;
448 i
449 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
450 i++)
451 {
452 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
453 == NULL)
454 {
455 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
456 << IVD_UNSUPPORTEDPARAM;
457 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
458 IVD_DISP_FRM_OP_BUF_NULL;
459 return IV_FAIL;
460 }
461
462 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
463 == 0)
464 {
465 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
466 << IVD_UNSUPPORTEDPARAM;
467 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
468 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
469 return IV_FAIL;
470 }
471 }
472 }
473 }
474 break;
475
476 case IVD_CMD_VIDEO_DECODE:
477 {
478 ih264d_video_decode_ip_t *ps_ip =
479 (ih264d_video_decode_ip_t *)pv_api_ip;
480 ih264d_video_decode_op_t *ps_op =
481 (ih264d_video_decode_op_t *)pv_api_op;
482
483 H264_DEC_DEBUG_PRINT("The input bytes is: %d",
484 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
485 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
486
487 if(ps_ip->s_ivd_video_decode_ip_t.u4_size
488 != sizeof(ih264d_video_decode_ip_t)&&
489 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer))
490 {
491 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
492 << IVD_UNSUPPORTEDPARAM;
493 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
494 IVD_IP_API_STRUCT_SIZE_INCORRECT;
495 return (IV_FAIL);
496 }
497
498 if(ps_op->s_ivd_video_decode_op_t.u4_size
499 != sizeof(ih264d_video_decode_op_t)&&
500 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present))
501 {
502 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
503 << IVD_UNSUPPORTEDPARAM;
504 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
505 IVD_OP_API_STRUCT_SIZE_INCORRECT;
506 return (IV_FAIL);
507 }
508
509 }
510 break;
511
512 case IVD_CMD_DELETE:
513 {
514 ih264d_delete_ip_t *ps_ip =
515 (ih264d_delete_ip_t *)pv_api_ip;
516 ih264d_delete_op_t *ps_op =
517 (ih264d_delete_op_t *)pv_api_op;
518
519 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
520
521 if(ps_ip->s_ivd_delete_ip_t.u4_size
522 != sizeof(ih264d_delete_ip_t))
523 {
524 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
525 << IVD_UNSUPPORTEDPARAM;
526 ps_op->s_ivd_delete_op_t.u4_error_code |=
527 IVD_IP_API_STRUCT_SIZE_INCORRECT;
528 return (IV_FAIL);
529 }
530
531 if(ps_op->s_ivd_delete_op_t.u4_size
532 != sizeof(ih264d_delete_op_t))
533 {
534 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
535 << IVD_UNSUPPORTEDPARAM;
536 ps_op->s_ivd_delete_op_t.u4_error_code |=
537 IVD_OP_API_STRUCT_SIZE_INCORRECT;
538 return (IV_FAIL);
539 }
540
541 }
542 break;
543
544 case IVD_CMD_VIDEO_CTL:
545 {
546 UWORD32 *pu4_ptr_cmd;
547 UWORD32 sub_command;
548
549 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
550 pu4_ptr_cmd += 2;
551 sub_command = *pu4_ptr_cmd;
552
553 switch(sub_command)
554 {
555 case IVD_CMD_CTL_SETPARAMS:
556 {
557 ih264d_ctl_set_config_ip_t *ps_ip;
558 ih264d_ctl_set_config_op_t *ps_op;
559 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
560 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
561
562 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
563 != sizeof(ih264d_ctl_set_config_ip_t))
564 {
565 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
566 << IVD_UNSUPPORTEDPARAM;
567 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
568 IVD_IP_API_STRUCT_SIZE_INCORRECT;
569 return IV_FAIL;
570 }
571 }
572 //no break; is needed here
573 case IVD_CMD_CTL_SETDEFAULT:
574 {
575 ih264d_ctl_set_config_op_t *ps_op;
576 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
577 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
578 != sizeof(ih264d_ctl_set_config_op_t))
579 {
580 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
581 << IVD_UNSUPPORTEDPARAM;
582 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
583 IVD_OP_API_STRUCT_SIZE_INCORRECT;
584 return IV_FAIL;
585 }
586 }
587 break;
588
589 case IVD_CMD_CTL_GETPARAMS:
590 {
591 ih264d_ctl_getstatus_ip_t *ps_ip;
592 ih264d_ctl_getstatus_op_t *ps_op;
593
594 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
595 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
596 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
597 != sizeof(ih264d_ctl_getstatus_ip_t))
598 {
599 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
600 << IVD_UNSUPPORTEDPARAM;
601 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
602 IVD_IP_API_STRUCT_SIZE_INCORRECT;
603 return IV_FAIL;
604 }
605 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
606 != sizeof(ih264d_ctl_getstatus_op_t))
607 {
608 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
609 << IVD_UNSUPPORTEDPARAM;
610 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
611 IVD_OP_API_STRUCT_SIZE_INCORRECT;
612 return IV_FAIL;
613 }
614 }
615 break;
616
617 case IVD_CMD_CTL_GETBUFINFO:
618 {
619 ih264d_ctl_getbufinfo_ip_t *ps_ip;
620 ih264d_ctl_getbufinfo_op_t *ps_op;
621 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
622 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
623
624 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
625 != sizeof(ih264d_ctl_getbufinfo_ip_t))
626 {
627 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
628 << IVD_UNSUPPORTEDPARAM;
629 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
630 IVD_IP_API_STRUCT_SIZE_INCORRECT;
631 return IV_FAIL;
632 }
633 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
634 != sizeof(ih264d_ctl_getbufinfo_op_t))
635 {
636 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
637 << IVD_UNSUPPORTEDPARAM;
638 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
639 IVD_OP_API_STRUCT_SIZE_INCORRECT;
640 return IV_FAIL;
641 }
642 }
643 break;
644
645 case IVD_CMD_CTL_GETVERSION:
646 {
647 ih264d_ctl_getversioninfo_ip_t *ps_ip;
648 ih264d_ctl_getversioninfo_op_t *ps_op;
649 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
650 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
651 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
652 != sizeof(ih264d_ctl_getversioninfo_ip_t))
653 {
654 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
655 << IVD_UNSUPPORTEDPARAM;
656 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
657 IVD_IP_API_STRUCT_SIZE_INCORRECT;
658 return IV_FAIL;
659 }
660 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
661 != sizeof(ih264d_ctl_getversioninfo_op_t))
662 {
663 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
664 << IVD_UNSUPPORTEDPARAM;
665 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
666 IVD_OP_API_STRUCT_SIZE_INCORRECT;
667 return IV_FAIL;
668 }
669 }
670 break;
671
672 case IVD_CMD_CTL_FLUSH:
673 {
674 ih264d_ctl_flush_ip_t *ps_ip;
675 ih264d_ctl_flush_op_t *ps_op;
676 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
677 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
678 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
679 != sizeof(ih264d_ctl_flush_ip_t))
680 {
681 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
682 << IVD_UNSUPPORTEDPARAM;
683 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
684 IVD_IP_API_STRUCT_SIZE_INCORRECT;
685 return IV_FAIL;
686 }
687 if(ps_op->s_ivd_ctl_flush_op_t.u4_size
688 != sizeof(ih264d_ctl_flush_op_t))
689 {
690 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
691 << IVD_UNSUPPORTEDPARAM;
692 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
693 IVD_OP_API_STRUCT_SIZE_INCORRECT;
694 return IV_FAIL;
695 }
696 }
697 break;
698
699 case IVD_CMD_CTL_RESET:
700 {
701 ih264d_ctl_reset_ip_t *ps_ip;
702 ih264d_ctl_reset_op_t *ps_op;
703 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
704 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
705 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
706 != sizeof(ih264d_ctl_reset_ip_t))
707 {
708 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
709 << IVD_UNSUPPORTEDPARAM;
710 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
711 IVD_IP_API_STRUCT_SIZE_INCORRECT;
712 return IV_FAIL;
713 }
714 if(ps_op->s_ivd_ctl_reset_op_t.u4_size
715 != sizeof(ih264d_ctl_reset_op_t))
716 {
717 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
718 << IVD_UNSUPPORTEDPARAM;
719 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
720 IVD_OP_API_STRUCT_SIZE_INCORRECT;
721 return IV_FAIL;
722 }
723 }
724 break;
725
726 case IH264D_CMD_CTL_DEGRADE:
727 {
728 ih264d_ctl_degrade_ip_t *ps_ip;
729 ih264d_ctl_degrade_op_t *ps_op;
730
731 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
732 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
733
734 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
735 {
736 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
737 ps_op->u4_error_code |=
738 IVD_IP_API_STRUCT_SIZE_INCORRECT;
739 return IV_FAIL;
740 }
741
742 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
743 {
744 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
745 ps_op->u4_error_code |=
746 IVD_OP_API_STRUCT_SIZE_INCORRECT;
747 return IV_FAIL;
748 }
749
750 if((ps_ip->i4_degrade_pics < 0)
751 || (ps_ip->i4_degrade_pics > 4)
752 || (ps_ip->i4_nondegrade_interval < 0)
753 || (ps_ip->i4_degrade_type < 0)
754 || (ps_ip->i4_degrade_type > 15))
755 {
756 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
757 return IV_FAIL;
758 }
759
760 break;
761 }
762
763 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
764 {
765 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
766 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
767
768 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
769 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
770
771 if(ps_ip->u4_size
772 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
773 {
774 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
775 ps_op->u4_error_code |=
776 IVD_IP_API_STRUCT_SIZE_INCORRECT;
777 return IV_FAIL;
778 }
779
780 if(ps_op->u4_size
781 != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
782 {
783 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
784 ps_op->u4_error_code |=
785 IVD_OP_API_STRUCT_SIZE_INCORRECT;
786 return IV_FAIL;
787 }
788
789 break;
790 }
791 case IH264D_CMD_CTL_GET_VUI_PARAMS:
792 {
793 ih264d_ctl_get_vui_params_ip_t *ps_ip;
794 ih264d_ctl_get_vui_params_op_t *ps_op;
795
796 ps_ip =
797 (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
798 ps_op =
799 (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
800
801 if(ps_ip->u4_size
802 != sizeof(ih264d_ctl_get_vui_params_ip_t))
803 {
804 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
805 ps_op->u4_error_code |=
806 IVD_IP_API_STRUCT_SIZE_INCORRECT;
807 return IV_FAIL;
808 }
809
810 if(ps_op->u4_size
811 != sizeof(ih264d_ctl_get_vui_params_op_t))
812 {
813 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
814 ps_op->u4_error_code |=
815 IVD_OP_API_STRUCT_SIZE_INCORRECT;
816 return IV_FAIL;
817 }
818
819 break;
820 }
821 case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
822 {
823 ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
824 ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
825
826 ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
827 ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
828
829 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_ip_t))
830 {
831 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
832 ps_op->u4_error_code |=
833 IVD_IP_API_STRUCT_SIZE_INCORRECT;
834 return IV_FAIL;
835 }
836
837 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_op_t))
838 {
839 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
840 ps_op->u4_error_code |=
841 IVD_OP_API_STRUCT_SIZE_INCORRECT;
842 return IV_FAIL;
843 }
844
845 break;
846 }
847
848 case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
849 {
850 ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
851 ih264d_ctl_get_sei_cll_params_op_t *ps_op;
852
853 ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
854 ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
855
856 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_ip_t))
857 {
858 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
859 ps_op->u4_error_code |=
860 IVD_IP_API_STRUCT_SIZE_INCORRECT;
861 return IV_FAIL;
862 }
863
864 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_op_t))
865 {
866 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
867 ps_op->u4_error_code |=
868 IVD_OP_API_STRUCT_SIZE_INCORRECT;
869 return IV_FAIL;
870 }
871
872 break;
873 }
874
875 case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
876 {
877 ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
878 ih264d_ctl_get_sei_ave_params_op_t *ps_op;
879
880 ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
881 ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
882
883 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_ip_t))
884 {
885 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
886 ps_op->u4_error_code |=
887 IVD_IP_API_STRUCT_SIZE_INCORRECT;
888 return IV_FAIL;
889 }
890
891 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_op_t))
892 {
893 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
894 ps_op->u4_error_code |=
895 IVD_OP_API_STRUCT_SIZE_INCORRECT;
896 return IV_FAIL;
897 }
898
899 break;
900 }
901
902 case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
903 {
904 ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
905 ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
906
907 ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
908 ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
909
910 if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_ip_t))
911 {
912 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
913 ps_op->u4_error_code |=
914 IVD_IP_API_STRUCT_SIZE_INCORRECT;
915 return IV_FAIL;
916 }
917
918 if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_op_t))
919 {
920 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
921 ps_op->u4_error_code |=
922 IVD_OP_API_STRUCT_SIZE_INCORRECT;
923 return IV_FAIL;
924 }
925
926 break;
927 }
928
929 case IH264D_CMD_CTL_SET_NUM_CORES:
930 {
931 ih264d_ctl_set_num_cores_ip_t *ps_ip;
932 ih264d_ctl_set_num_cores_op_t *ps_op;
933
934 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
935 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
936
937 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
938 {
939 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
940 ps_op->u4_error_code |=
941 IVD_IP_API_STRUCT_SIZE_INCORRECT;
942 return IV_FAIL;
943 }
944
945 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
946 {
947 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
948 ps_op->u4_error_code |=
949 IVD_OP_API_STRUCT_SIZE_INCORRECT;
950 return IV_FAIL;
951 }
952
953 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
954 && (ps_ip->u4_num_cores != 3)
955 && (ps_ip->u4_num_cores != 4))
956 {
957 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
958 return IV_FAIL;
959 }
960 break;
961 }
962 case IH264D_CMD_CTL_SET_PROCESSOR:
963 {
964 ih264d_ctl_set_processor_ip_t *ps_ip;
965 ih264d_ctl_set_processor_op_t *ps_op;
966
967 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
968 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
969
970 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
971 {
972 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
973 ps_op->u4_error_code |=
974 IVD_IP_API_STRUCT_SIZE_INCORRECT;
975 return IV_FAIL;
976 }
977
978 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
979 {
980 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
981 ps_op->u4_error_code |=
982 IVD_OP_API_STRUCT_SIZE_INCORRECT;
983 return IV_FAIL;
984 }
985
986 break;
987 }
988 default:
989 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
990 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
991 return IV_FAIL;
992 break;
993 }
994 }
995 break;
996 }
997
998 return IV_SUCCESS;
999 }
1000
1001
1002 /**
1003 *******************************************************************************
1004 *
1005 * @brief
1006 * Sets Processor type
1007 *
1008 * @par Description:
1009 * Sets Processor type
1010 *
1011 * @param[in] ps_codec_obj
1012 * Pointer to codec object at API level
1013 *
1014 * @param[in] pv_api_ip
1015 * Pointer to input argument structure
1016 *
1017 * @param[out] pv_api_op
1018 * Pointer to output argument structure
1019 *
1020 * @returns Status
1021 *
1022 * @remarks
1023 *
1024 *
1025 *******************************************************************************
1026 */
1027
ih264d_set_processor(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1028 WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1029 {
1030 ih264d_ctl_set_processor_ip_t *ps_ip;
1031 ih264d_ctl_set_processor_op_t *ps_op;
1032 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1033
1034 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1035 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1036
1037 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1038 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1039
1040 ih264d_init_function_ptr(ps_codec);
1041
1042 ps_op->u4_error_code = 0;
1043 return IV_SUCCESS;
1044 }
1045
1046
1047 /**************************************************************************
1048 * \if Function name : ih264d_init_decoder \endif
1049 *
1050 *
1051 * \brief
1052 * Initializes the decoder
1053 *
1054 * \param apiVersion : Version of the api being used.
1055 * \param errorHandlingMechanism : Mechanism to be used for errror handling.
1056 * \param postFilteringType: Type of post filtering operation to be used.
1057 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1058 * \param uc_dispBufs: Number of Display Buffers.
1059 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1060 * \param p_DispBufAPI: Pointer to Display Buffer API.
1061 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1062 * for memory allocation and freeing.
1063 *
1064 * \return
1065 * 0 on Success and -1 on error
1066 *
1067 **************************************************************************
1068 */
ih264d_init_decoder(void * ps_dec_params)1069 void ih264d_init_decoder(void * ps_dec_params)
1070 {
1071 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1072 dec_slice_params_t *ps_cur_slice;
1073 pocstruct_t *ps_prev_poc, *ps_cur_poc;
1074 WORD32 size;
1075
1076 size = sizeof(pred_info_t) * 2 * 32;
1077 memset(ps_dec->ps_pred, 0 , size);
1078
1079 size = sizeof(disp_mgr_t);
1080 memset(ps_dec->pv_disp_buf_mgr, 0 , size);
1081
1082 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1083 memset(ps_dec->pv_pic_buf_mgr, 0, size);
1084
1085 size = sizeof(dec_err_status_t);
1086 memset(ps_dec->ps_dec_err_status, 0, size);
1087
1088 size = sizeof(sei);
1089 memset(ps_dec->ps_sei, 0, size);
1090
1091 size = sizeof(sei);
1092 memset(ps_dec->ps_sei_parse, 0, size);
1093
1094 size = sizeof(dpb_commands_t);
1095 memset(ps_dec->ps_dpb_cmds, 0, size);
1096
1097 size = sizeof(dec_bit_stream_t);
1098 memset(ps_dec->ps_bitstrm, 0, size);
1099
1100 size = sizeof(dec_slice_params_t);
1101 memset(ps_dec->ps_cur_slice, 0, size);
1102
1103 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1104 memset(ps_dec->pv_scratch_sps_pps, 0, size);
1105
1106 size = sizeof(ctxt_inc_mb_info_t);
1107 memset(ps_dec->ps_left_mb_ctxt_info, 0, size);
1108
1109 size = (sizeof(neighbouradd_t) << 2);
1110 memset(ps_dec->ps_left_mvpred_addr, 0 ,size);
1111
1112 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1113 memset(ps_dec->pv_mv_buf_mgr, 0, size);
1114
1115 /* Free any dynamic buffers that are allocated */
1116 ih264d_free_dynamic_bufs(ps_dec);
1117
1118 {
1119 UWORD8 i;
1120 struct pic_buffer_t *ps_init_dpb;
1121 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0];
1122 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1123 {
1124 ps_init_dpb->pu1_buf1 = NULL;
1125 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1126 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb;
1127 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb;
1128 ps_init_dpb++;
1129 }
1130
1131 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0];
1132 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1133 {
1134 ps_init_dpb->pu1_buf1 = NULL;
1135 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1136 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb;
1137 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb;
1138 ps_init_dpb++;
1139 }
1140 }
1141
1142 ps_cur_slice = ps_dec->ps_cur_slice;
1143 ps_dec->init_done = 0;
1144
1145 ps_dec->u4_num_cores = 1;
1146
1147 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1148
1149 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1150 ps_dec->u4_app_disable_deblk_frm = 0;
1151 ps_dec->i4_degrade_type = 0;
1152 ps_dec->i4_degrade_pics = 0;
1153
1154 memset(ps_dec->ps_pps, 0,
1155 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1156 memset(ps_dec->ps_sps, 0,
1157 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1158
1159 /* Initialization of function pointers ih264d_deblock_picture function*/
1160
1161 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1162 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1163
1164 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1165
1166 ps_dec->u4_num_fld_in_frm = 0;
1167
1168 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1169
1170 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1171 ps_dec->ps_sei->u1_is_valid = 0;
1172
1173 /* decParams Initializations */
1174 ps_dec->ps_cur_pps = NULL;
1175 ps_dec->ps_cur_sps = NULL;
1176 ps_dec->u1_init_dec_flag = 0;
1177 ps_dec->u1_first_slice_in_stream = 1;
1178 ps_dec->u1_last_pic_not_decoded = 0;
1179 ps_dec->u4_app_disp_width = 0;
1180 ps_dec->i4_header_decoded = 0;
1181 ps_dec->u4_total_frames_decoded = 0;
1182
1183 ps_dec->i4_error_code = 0;
1184 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1185 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1186
1187 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1188 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1189 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1190 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1191 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1192
1193 ps_dec->u1_pr_sl_type = 0xFF;
1194 ps_dec->u2_mbx = 0xffff;
1195 ps_dec->u2_mby = 0;
1196 ps_dec->u2_total_mbs_coded = 0;
1197
1198 /* POC initializations */
1199 ps_prev_poc = &ps_dec->s_prev_pic_poc;
1200 ps_cur_poc = &ps_dec->s_cur_pic_poc;
1201 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1202 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1203 ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1204 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1205 ps_prev_poc->i4_delta_pic_order_cnt[0] =
1206 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1207 ps_prev_poc->i4_delta_pic_order_cnt[1] =
1208 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1209 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1210 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1211 0;
1212 ps_prev_poc->i4_bottom_field_order_count =
1213 ps_cur_poc->i4_bottom_field_order_count = 0;
1214 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1215 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1216 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1217 ps_cur_slice->u1_mmco_equalto5 = 0;
1218 ps_cur_slice->u2_frame_num = 0;
1219
1220 ps_dec->i4_max_poc = 0;
1221 ps_dec->i4_prev_max_display_seq = 0;
1222 ps_dec->u1_recon_mb_grp = 4;
1223 ps_dec->i4_reorder_depth = -1;
1224
1225 /* Field PIC initializations */
1226 ps_dec->u1_second_field = 0;
1227 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1228
1229 /* Set the cropping parameters as zero */
1230 ps_dec->u2_crop_offset_y = 0;
1231 ps_dec->u2_crop_offset_uv = 0;
1232
1233 /* The Initial Frame Rate Info is not Present */
1234 ps_dec->i4_vui_frame_rate = -1;
1235 ps_dec->i4_pic_type = NA_SLICE;
1236 ps_dec->i4_frametype = IV_NA_FRAME;
1237 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1238
1239 ps_dec->u1_res_changed = 0;
1240
1241
1242 ps_dec->u1_frame_decoded_flag = 0;
1243
1244 /* Set the default frame seek mask mode */
1245 ps_dec->u4_skip_frm_mask = SKIP_NONE;
1246
1247 /********************************************************/
1248 /* Initialize CAVLC residual decoding function pointers */
1249 /********************************************************/
1250 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1251 ps_dec->pf_cavlc_4x4res_block[1] =
1252 ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1253 ps_dec->pf_cavlc_4x4res_block[2] =
1254 ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1255
1256 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1257 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1258
1259 ps_dec->pf_cavlc_parse_8x8block[0] =
1260 ih264d_cavlc_parse_8x8block_none_available;
1261 ps_dec->pf_cavlc_parse_8x8block[1] =
1262 ih264d_cavlc_parse_8x8block_left_available;
1263 ps_dec->pf_cavlc_parse_8x8block[2] =
1264 ih264d_cavlc_parse_8x8block_top_available;
1265 ps_dec->pf_cavlc_parse_8x8block[3] =
1266 ih264d_cavlc_parse_8x8block_both_available;
1267
1268 /***************************************************************************/
1269 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1270 /***************************************************************************/
1271 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1272 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1273
1274 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1275 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1276
1277 ps_dec->pf_fill_bs_xtra_left_edge[0] =
1278 ih264d_fill_bs_xtra_left_edge_cur_frm;
1279 ps_dec->pf_fill_bs_xtra_left_edge[1] =
1280 ih264d_fill_bs_xtra_left_edge_cur_fld;
1281
1282 /* Initialize Reference Pic Buffers */
1283 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1284
1285 ps_dec->u2_prv_frame_num = 0;
1286 ps_dec->u1_top_bottom_decoded = 0;
1287 ps_dec->u1_dangling_field = 0;
1288
1289 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1290
1291 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1292 ps_dec->pi1_left_ref_idx_ctxt_inc =
1293 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1294 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1295
1296 /* ! */
1297 /* Initializing flush frame u4_flag */
1298 ps_dec->u1_flushfrm = 0;
1299
1300 {
1301 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1302 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1303 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1304 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1305 }
1306
1307 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1308 memset(ps_dec->u4_disp_buf_mapping, 0,
1309 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1310 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1311 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1312 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
1313
1314 ih264d_init_arch(ps_dec);
1315 ih264d_init_function_ptr(ps_dec);
1316 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
1317 ps_dec->init_done = 1;
1318
1319 }
ih264d_free_static_bufs(iv_obj_t * dec_hdl)1320 WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl)
1321 {
1322 dec_struct_t *ps_dec;
1323
1324 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1325 void *pv_mem_ctxt;
1326
1327 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1328 pf_aligned_free = ps_dec->pf_aligned_free;
1329 pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1330
1331 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps);
1332 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps);
1333 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle);
1334 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle);
1335 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr);
1336 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred);
1337 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr);
1338 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr);
1339 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base);
1340 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status);
1341 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei);
1342 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei_parse);
1343 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds);
1344 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm);
1345 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice);
1346 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps);
1347 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static);
1348 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base);
1349 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t);
1350 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info);
1351 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base);
1352 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1);
1353 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer);
1354 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base);
1355 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat);
1356 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat);
1357 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr);
1358 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr);
1359 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base);
1360 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle);
1361
1362 if(dec_hdl)
1363 {
1364 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1365 }
1366 return IV_SUCCESS;
1367 }
1368 /*****************************************************************************/
1369 /* */
1370 /* Function Name : ih264d_create */
1371 /* */
1372 /* Description : creates decoder */
1373 /* */
1374 /* Inputs :iv_obj_t decoder handle */
1375 /* :pv_api_ip pointer to input structure */
1376 /* :pv_api_op pointer to output structure */
1377 /* Outputs : */
1378 /* Returns : void */
1379 /* */
1380 /* Issues : none */
1381 /* */
1382 /* Revision History: */
1383 /* */
1384 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1385 /* 22 10 2008 100356 Draft */
1386 /* */
1387 /*****************************************************************************/
ih264d_allocate_static_bufs(iv_obj_t ** dec_hdl,void * pv_api_ip,void * pv_api_op)1388 WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op)
1389 {
1390 ih264d_create_ip_t *ps_create_ip;
1391 ih264d_create_op_t *ps_create_op;
1392 void *pv_buf;
1393 UWORD8 *pu1_buf;
1394 dec_struct_t *ps_dec;
1395 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size);
1396 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1397 void *pv_mem_ctxt;
1398 WORD32 size;
1399
1400 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1401 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1402
1403 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1404
1405 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc;
1406 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1407 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1408
1409 /* Initialize return handle to NULL */
1410 ps_create_op->s_ivd_create_op_t.pv_handle = NULL;
1411 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t));
1412 RETURN_IF((NULL == pv_buf), IV_FAIL);
1413 memset(pv_buf, 0, sizeof(iv_obj_t));
1414 *dec_hdl = (iv_obj_t *)pv_buf;
1415 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl;
1416
1417 (*dec_hdl)->pv_codec_handle = NULL;
1418 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t));
1419 RETURN_IF((NULL == pv_buf), IV_FAIL);
1420 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf;
1421 ps_dec = (dec_struct_t *)pv_buf;
1422
1423 memset(ps_dec, 0, sizeof(dec_struct_t));
1424
1425 #ifndef LOGO_EN
1426 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf;
1427 #else
1428 ps_dec->u4_share_disp_buf = 0;
1429 #endif
1430
1431 ps_dec->u1_chroma_format =
1432 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format);
1433
1434 if((ps_dec->u1_chroma_format != IV_YUV_420P)
1435 && (ps_dec->u1_chroma_format
1436 != IV_YUV_420SP_UV)
1437 && (ps_dec->u1_chroma_format
1438 != IV_YUV_420SP_VU))
1439 {
1440 ps_dec->u4_share_disp_buf = 0;
1441 }
1442
1443 ps_dec->pf_aligned_alloc = pf_aligned_alloc;
1444 ps_dec->pf_aligned_free = pf_aligned_free;
1445 ps_dec->pv_mem_ctxt = pv_mem_ctxt;
1446
1447
1448 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
1449 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1450 RETURN_IF((NULL == pv_buf), IV_FAIL);
1451 memset(pv_buf, 0, size);
1452 ps_dec->ps_sps = pv_buf;
1453
1454 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
1455 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1456 RETURN_IF((NULL == pv_buf), IV_FAIL);
1457 memset(pv_buf, 0, size);
1458 ps_dec->ps_pps = pv_buf;
1459
1460 size = ithread_get_handle_size();
1461 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1462 RETURN_IF((NULL == pv_buf), IV_FAIL);
1463 memset(pv_buf, 0, size);
1464 ps_dec->pv_dec_thread_handle = pv_buf;
1465
1466 size = ithread_get_handle_size();
1467 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1468 RETURN_IF((NULL == pv_buf), IV_FAIL);
1469 memset(pv_buf, 0, size);
1470 ps_dec->pv_bs_deblk_thread_handle = pv_buf;
1471
1472 size = sizeof(dpb_manager_t);
1473 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1474 RETURN_IF((NULL == pv_buf), IV_FAIL);
1475 memset(pv_buf, 0, size);
1476 ps_dec->ps_dpb_mgr = pv_buf;
1477
1478 size = sizeof(pred_info_t) * 2 * 32;
1479 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1480 RETURN_IF((NULL == pv_buf), IV_FAIL);
1481 memset(pv_buf, 0, size);
1482 ps_dec->ps_pred = pv_buf;
1483
1484 size = sizeof(disp_mgr_t);
1485 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1486 RETURN_IF((NULL == pv_buf), IV_FAIL);
1487 memset(pv_buf, 0, size);
1488 ps_dec->pv_disp_buf_mgr = pv_buf;
1489
1490 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1491 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1492 RETURN_IF((NULL == pv_buf), IV_FAIL);
1493 memset(pv_buf, 0, size);
1494 ps_dec->pv_pic_buf_mgr = pv_buf;
1495
1496 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
1497 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1498 RETURN_IF((NULL == pv_buf), IV_FAIL);
1499 memset(pv_buf, 0, size);
1500 ps_dec->ps_pic_buf_base = pv_buf;
1501
1502 size = sizeof(dec_err_status_t);
1503 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1504 RETURN_IF((NULL == pv_buf), IV_FAIL);
1505 memset(pv_buf, 0, size);
1506 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf;
1507
1508 size = sizeof(sei);
1509 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1510 RETURN_IF((NULL == pv_buf), IV_FAIL);
1511 memset(pv_buf, 0, size);
1512 ps_dec->ps_sei = (sei *)pv_buf;
1513
1514 size = sizeof(sei);
1515 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1516 RETURN_IF((NULL == pv_buf), IV_FAIL);
1517 memset(pv_buf, 0, size);
1518 ps_dec->ps_sei_parse = (sei *)pv_buf;
1519
1520 size = sizeof(dpb_commands_t);
1521 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1522 RETURN_IF((NULL == pv_buf), IV_FAIL);
1523 memset(pv_buf, 0, size);
1524 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf;
1525
1526 size = sizeof(dec_bit_stream_t);
1527 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1528 RETURN_IF((NULL == pv_buf), IV_FAIL);
1529 memset(pv_buf, 0, size);
1530 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf;
1531
1532 size = sizeof(dec_slice_params_t);
1533 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1534 RETURN_IF((NULL == pv_buf), IV_FAIL);
1535 memset(pv_buf, 0, size);
1536 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf;
1537
1538 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1539 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1540 RETURN_IF((NULL == pv_buf), IV_FAIL);
1541 memset(pv_buf, 0, size);
1542 ps_dec->pv_scratch_sps_pps = pv_buf;
1543
1544
1545 ps_dec->u4_static_bits_buf_size = 256000;
1546 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size);
1547 RETURN_IF((NULL == pv_buf), IV_FAIL);
1548 memset(pv_buf, 0, ps_dec->u4_static_bits_buf_size);
1549 ps_dec->pu1_bits_buf_static = pv_buf;
1550
1551
1552 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC)
1553 * sizeof(void *));
1554 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1555 RETURN_IF((NULL == pv_buf), IV_FAIL);
1556 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf;
1557 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size);
1558
1559 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
1560
1561
1562 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
1563 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1564 RETURN_IF((NULL == pv_buf), IV_FAIL);
1565 memset(pv_buf, 0, size);
1566 ps_dec->p_cabac_ctxt_table_t = pv_buf;
1567
1568
1569
1570 size = sizeof(ctxt_inc_mb_info_t);
1571 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1572 RETURN_IF((NULL == pv_buf), IV_FAIL);
1573 memset(pv_buf, 0, size);
1574 ps_dec->ps_left_mb_ctxt_info = pv_buf;
1575
1576
1577
1578 size = MAX_REF_BUF_SIZE * 2;
1579 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1580 RETURN_IF((NULL == pv_buf), IV_FAIL);
1581 memset(pv_buf, 0, size);
1582 ps_dec->pu1_ref_buff_base = pv_buf;
1583 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
1584
1585
1586 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
1587 * PRED_BUFFER_HEIGHT * 2);
1588 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1589 RETURN_IF((NULL == pv_buf), IV_FAIL);
1590 memset(pv_buf, 0, size);
1591 ps_dec->pi2_pred1 = pv_buf;
1592
1593
1594 size = sizeof(UWORD8) * (MB_LUM_SIZE);
1595 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1596 RETURN_IF((NULL == pv_buf), IV_FAIL);
1597 memset(pv_buf, 0, size);
1598 ps_dec->pu1_temp_mc_buffer = pv_buf;
1599
1600
1601
1602
1603 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
1604 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1605 RETURN_IF((NULL == pv_buf), IV_FAIL);
1606 memset(pv_buf, 0, size);
1607
1608 ps_dec->pu1_init_dpb_base = pv_buf;
1609 pu1_buf = pv_buf;
1610 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf;
1611
1612 pu1_buf += size / 2;
1613 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf;
1614
1615 size = (sizeof(UWORD32) * 2 * 3
1616 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
1617 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1618 RETURN_IF((NULL == pv_buf), IV_FAIL);
1619 memset(pv_buf, 0, size);
1620 ps_dec->pu4_mbaff_wt_mat = pv_buf;
1621
1622 size = sizeof(UWORD32) * 2 * 3
1623 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
1624 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1625 RETURN_IF((NULL == pv_buf), IV_FAIL);
1626 memset(pv_buf, 0, size);
1627 ps_dec->pu4_wts_ofsts_mat = pv_buf;
1628
1629
1630 size = (sizeof(neighbouradd_t) << 2);
1631 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1632 RETURN_IF((NULL == pv_buf), IV_FAIL);
1633 memset(pv_buf, 0, size);
1634 ps_dec->ps_left_mvpred_addr = pv_buf;
1635
1636
1637 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1638 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1639 RETURN_IF((NULL == pv_buf), IV_FAIL);
1640 memset(pv_buf, 0, size);
1641 ps_dec->pv_mv_buf_mgr = pv_buf;
1642
1643
1644 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
1645 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1646 RETURN_IF((NULL == pv_buf), IV_FAIL);
1647 ps_dec->ps_col_mv_base = pv_buf;
1648 memset(ps_dec->ps_col_mv_base, 0, size);
1649
1650 ih264d_init_decoder(ps_dec);
1651
1652 return IV_SUCCESS;
1653 }
1654
1655
1656 /*****************************************************************************/
1657 /* */
1658 /* Function Name : ih264d_create */
1659 /* */
1660 /* Description : creates decoder */
1661 /* */
1662 /* Inputs :iv_obj_t decoder handle */
1663 /* :pv_api_ip pointer to input structure */
1664 /* :pv_api_op pointer to output structure */
1665 /* Outputs : */
1666 /* Returns : void */
1667 /* */
1668 /* Issues : none */
1669 /* */
1670 /* Revision History: */
1671 /* */
1672 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1673 /* 22 10 2008 100356 Draft */
1674 /* */
1675 /*****************************************************************************/
ih264d_create(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1676 WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1677 {
1678 ih264d_create_ip_t *ps_create_ip;
1679 ih264d_create_op_t *ps_create_op;
1680
1681 WORD32 ret;
1682
1683 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1684 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1685
1686 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1687 dec_hdl = NULL;
1688 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op);
1689
1690 /* If allocation of some buffer fails, then free buffers allocated till then */
1691 if(IV_FAIL == ret)
1692 {
1693 if(dec_hdl)
1694 {
1695 if(dec_hdl->pv_codec_handle)
1696 {
1697 ih264d_free_static_bufs(dec_hdl);
1698 }
1699 else
1700 {
1701 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1702 void *pv_mem_ctxt;
1703
1704 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1705 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1706 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1707 }
1708 }
1709 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED;
1710 ps_create_op->s_ivd_create_op_t.u4_error_code |= 1 << IVD_FATALERROR;
1711
1712 return IV_FAIL;
1713 }
1714
1715 return IV_SUCCESS;
1716 }
1717
1718 /*****************************************************************************/
1719 /* */
1720 /* Function Name : ih264d_map_error */
1721 /* */
1722 /* Description : Maps error codes to IVD error groups */
1723 /* */
1724 /* Inputs : */
1725 /* Globals : <Does it use any global variables?> */
1726 /* Outputs : */
1727 /* Returns : void */
1728 /* */
1729 /* Issues : none */
1730 /* */
1731 /* Revision History: */
1732 /* */
1733 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1734 /* 22 10 2008 100356 Draft */
1735 /* */
1736 /*****************************************************************************/
ih264d_map_error(UWORD32 i4_err_status)1737 UWORD32 ih264d_map_error(UWORD32 i4_err_status)
1738 {
1739 UWORD32 temp = 0;
1740
1741 switch(i4_err_status)
1742 {
1743 case ERROR_MEM_ALLOC_ISRAM_T:
1744 case ERROR_MEM_ALLOC_SDRAM_T:
1745 case ERROR_BUF_MGR:
1746 case ERROR_MB_GROUP_ASSGN_T:
1747 case ERROR_FRAME_LIMIT_OVER:
1748 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
1749 case ERROR_PROFILE_NOT_SUPPORTED:
1750 case ERROR_INIT_NOT_DONE:
1751 case IVD_MEM_ALLOC_FAILED:
1752 case ERROR_FEATURE_UNAVAIL:
1753 case IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED:
1754 temp = 1 << IVD_FATALERROR;
1755 H264_DEC_DEBUG_PRINT("\nFatal Error\n");
1756 break;
1757
1758 case ERROR_DBP_MANAGER_T:
1759 case ERROR_GAPS_IN_FRM_NUM:
1760 case ERROR_UNKNOWN_NAL:
1761 case ERROR_INV_MB_SLC_GRP_T:
1762 case ERROR_MULTIPLE_SLC_GRP_T:
1763 case ERROR_UNKNOWN_LEVEL:
1764 case ERROR_UNAVAIL_PICBUF_T:
1765 case ERROR_UNAVAIL_MVBUF_T:
1766 case ERROR_UNAVAIL_DISPBUF_T:
1767 case ERROR_NUM_REF:
1768 case ERROR_REFIDX_ORDER_T:
1769 case ERROR_PIC0_NOT_FOUND_T:
1770 case ERROR_MB_TYPE:
1771 case ERROR_SUB_MB_TYPE:
1772 case ERROR_CBP:
1773 case ERROR_REF_IDX:
1774 case ERROR_NUM_MV:
1775 case ERROR_CHROMA_PRED_MODE:
1776 case ERROR_INTRAPRED:
1777 case ERROR_NEXT_MB_ADDRESS_T:
1778 case ERROR_MB_ADDRESS_T:
1779 case ERROR_PIC1_NOT_FOUND_T:
1780 case ERROR_CAVLC_NUM_COEFF_T:
1781 case ERROR_CAVLC_SCAN_POS_T:
1782 case ERROR_PRED_WEIGHT_TABLE_T:
1783 case ERROR_CORRUPTED_SLICE:
1784 temp = 1 << IVD_CORRUPTEDDATA;
1785 break;
1786
1787 case ERROR_NOT_SUPP_RESOLUTION:
1788 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
1789 temp = 1 << IVD_UNSUPPORTEDINPUT;
1790 break;
1791
1792 case ERROR_INVALID_PIC_PARAM:
1793 case ERROR_INVALID_SEQ_PARAM:
1794 case ERROR_EGC_EXCEED_32_1_T:
1795 case ERROR_EGC_EXCEED_32_2_T:
1796 case ERROR_INV_RANGE_TEV_T:
1797 case ERROR_INV_SLC_TYPE_T:
1798 case ERROR_INV_POC_TYPE_T:
1799 case ERROR_INV_RANGE_QP_T:
1800 case ERROR_INV_SPS_PPS_T:
1801 case ERROR_INV_SLICE_HDR_T:
1802 case ERROR_INV_SEI_MDCV_PARAMS:
1803 case ERROR_INV_SEI_CLL_PARAMS:
1804 case ERROR_INV_SEI_AVE_PARAMS:
1805 case ERROR_INV_SEI_CCV_PARAMS:
1806 temp = 1 << IVD_CORRUPTEDHEADER;
1807 break;
1808
1809 case ERROR_EOB_FLUSHBITS_T:
1810 case ERROR_EOB_GETBITS_T:
1811 case ERROR_EOB_GETBIT_T:
1812 case ERROR_EOB_BYPASS_T:
1813 case ERROR_EOB_DECISION_T:
1814 case ERROR_EOB_TERMINATE_T:
1815 case ERROR_EOB_READCOEFF4X4CAB_T:
1816 temp = 1 << IVD_INSUFFICIENTDATA;
1817 break;
1818 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
1819 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
1820 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
1821 break;
1822
1823 case ERROR_DANGLING_FIELD_IN_PIC:
1824 temp = 1 << IVD_APPLIEDCONCEALMENT;
1825 break;
1826
1827 }
1828
1829 return temp;
1830
1831 }
1832
ih264d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,UWORD8 u1_chroma_format,UWORD32 * p_buf_size)1833 UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
1834 UWORD32 pic_ht,
1835 UWORD8 u1_chroma_format,
1836 UWORD32 *p_buf_size)
1837 {
1838 UWORD32 u4_min_num_out_bufs = 0;
1839
1840 if(u1_chroma_format == IV_YUV_420P)
1841 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1842 else if(u1_chroma_format == IV_YUV_422ILE)
1843 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1844 else if(u1_chroma_format == IV_RGB_565)
1845 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1846 else if((u1_chroma_format == IV_YUV_420SP_UV)
1847 || (u1_chroma_format == IV_YUV_420SP_VU))
1848 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
1849
1850 if(u1_chroma_format == IV_YUV_420P)
1851 {
1852 p_buf_size[0] = (pic_wd * pic_ht);
1853 p_buf_size[1] = (pic_wd * pic_ht) >> 2;
1854 p_buf_size[2] = (pic_wd * pic_ht) >> 2;
1855 }
1856 else if(u1_chroma_format == IV_YUV_422ILE)
1857 {
1858 p_buf_size[0] = (pic_wd * pic_ht) * 2;
1859 p_buf_size[1] = p_buf_size[2] = 0;
1860 }
1861 else if(u1_chroma_format == IV_RGB_565)
1862 {
1863 p_buf_size[0] = (pic_wd * pic_ht) * 2;
1864 p_buf_size[1] = p_buf_size[2] = 0;
1865 }
1866 else if((u1_chroma_format == IV_YUV_420SP_UV)
1867 || (u1_chroma_format == IV_YUV_420SP_VU))
1868 {
1869 p_buf_size[0] = (pic_wd * pic_ht);
1870 p_buf_size[1] = (pic_wd * pic_ht) >> 1;
1871 p_buf_size[2] = 0;
1872 }
1873
1874 return u4_min_num_out_bufs;
1875 }
1876
check_app_out_buf_size(dec_struct_t * ps_dec)1877 WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
1878 {
1879 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1880 UWORD32 u4_min_num_out_bufs, i;
1881 UWORD32 pic_wd, pic_ht;
1882
1883 if(0 == ps_dec->u4_share_disp_buf)
1884 {
1885 pic_wd = ps_dec->u2_disp_width;
1886 pic_ht = ps_dec->u2_disp_height;
1887
1888 }
1889 else
1890 {
1891 pic_wd = ps_dec->u2_frm_wd_y;
1892 pic_ht = ps_dec->u2_frm_ht_y;
1893 }
1894
1895 if(ps_dec->u4_app_disp_width > pic_wd)
1896 pic_wd = ps_dec->u4_app_disp_width;
1897
1898 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
1899 ps_dec->u1_chroma_format,
1900 &au4_min_out_buf_size[0]);
1901
1902
1903 if(0 == ps_dec->u4_share_disp_buf)
1904 {
1905 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
1906 return IV_FAIL;
1907
1908 for(i = 0; i < u4_min_num_out_bufs; i++)
1909 {
1910 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
1911 < au4_min_out_buf_size[i])
1912 return (IV_FAIL);
1913 }
1914 }
1915 else
1916 {
1917 if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs)
1918 return IV_FAIL;
1919
1920 for(i = 0; i < u4_min_num_out_bufs; i++)
1921 {
1922 /* We need to check only with the disp_buffer[0], because we have
1923 * already ensured that all the buffers are of the same size in
1924 * ih264d_set_display_frame.
1925 */
1926 if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i])
1927 return (IV_FAIL);
1928 }
1929
1930 }
1931
1932 return (IV_SUCCESS);
1933 }
1934
1935
1936 /*****************************************************************************/
1937 /* */
1938 /* Function Name : ih264d_video_decode */
1939 /* */
1940 /* Description : handle video decode API command */
1941 /* */
1942 /* Inputs :iv_obj_t decoder handle */
1943 /* :pv_api_ip pointer to input structure */
1944 /* :pv_api_op pointer to output structure */
1945 /* Outputs : */
1946 /* Returns : void */
1947 /* */
1948 /* Issues : none */
1949 /* */
1950 /* Revision History: */
1951 /* */
1952 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1953 /* 22 10 2008 100356 Draft */
1954 /* */
1955 /*****************************************************************************/
1956
ih264d_video_decode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1957 WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1958 {
1959 /* ! */
1960
1961 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
1962
1963 WORD32 i4_err_status = 0;
1964 UWORD8 *pu1_buf = NULL;
1965 WORD32 buflen;
1966 UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
1967
1968 UWORD32 bytes_consumed = 0;
1969 UWORD32 cur_slice_is_nonref = 0;
1970 UWORD32 u4_next_is_aud;
1971 UWORD32 u4_first_start_code_found = 0;
1972 WORD32 ret = 0,api_ret_value = IV_SUCCESS;
1973 WORD32 header_data_left = 0,frame_data_left = 0;
1974 UWORD8 *pu1_bitstrm_buf;
1975 ih264d_video_decode_ip_t *ps_h264d_dec_ip;
1976 ih264d_video_decode_op_t *ps_h264d_dec_op;
1977 ivd_video_decode_ip_t *ps_dec_ip;
1978 ivd_video_decode_op_t *ps_dec_op;
1979
1980 ithread_set_name((void*)"Parse_thread");
1981
1982 ps_h264d_dec_ip = (ih264d_video_decode_ip_t *)pv_api_ip;
1983 ps_h264d_dec_op = (ih264d_video_decode_op_t *)pv_api_op;
1984 ps_dec_ip = &ps_h264d_dec_ip->s_ivd_video_decode_ip_t;
1985 ps_dec_op = &ps_h264d_dec_op->s_ivd_video_decode_op_t;
1986
1987 {
1988 UWORD32 u4_size;
1989 u4_size = ps_dec_op->u4_size;
1990 memset(ps_h264d_dec_op, 0, sizeof(ih264d_video_decode_op_t));
1991 ps_dec_op->u4_size = u4_size;
1992 }
1993
1994 ps_dec->pv_dec_out = ps_dec_op;
1995 if(ps_dec->init_done != 1)
1996 {
1997 return IV_FAIL;
1998 }
1999
2000 /*Data memory barries instruction,so that bitstream write by the application is complete*/
2001 DATA_SYNC();
2002
2003 if(0 == ps_dec->u1_flushfrm)
2004 {
2005 if(ps_dec_ip->pv_stream_buffer == NULL)
2006 {
2007 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2008 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2009 return IV_FAIL;
2010 }
2011 if(ps_dec_ip->u4_num_Bytes <= 0)
2012 {
2013 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2014 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2015 return IV_FAIL;
2016
2017 }
2018 }
2019 ps_dec->u1_pic_decode_done = 0;
2020
2021 ps_dec_op->u4_num_bytes_consumed = 0;
2022 ps_dec_op->i4_reorder_depth = -1;
2023 ps_dec_op->i4_display_index = DEFAULT_POC;
2024 ps_dec->ps_out_buffer = NULL;
2025
2026 if(ps_dec_ip->u4_size
2027 >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2028 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2029
2030 ps_dec->u4_fmt_conv_cur_row = 0;
2031
2032 ps_dec->u4_output_present = 0;
2033 ps_dec->s_disp_op.u4_error_code = 1;
2034 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2035 if(0 == ps_dec->u4_share_disp_buf
2036 && ps_dec->i4_decode_header == 0)
2037 {
2038 UWORD32 i;
2039 if((ps_dec->ps_out_buffer->u4_num_bufs == 0) ||
2040 (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS))
2041 {
2042 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2043 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2044 return IV_FAIL;
2045 }
2046
2047 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2048 {
2049 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2050 {
2051 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2052 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2053 return IV_FAIL;
2054 }
2055
2056 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2057 {
2058 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2059 ps_dec_op->u4_error_code |=
2060 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2061 return IV_FAIL;
2062 }
2063 }
2064 }
2065
2066 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2067 {
2068 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2069 return IV_FAIL;
2070 }
2071
2072 /* ! */
2073 ps_dec->u4_ts = ps_dec_ip->u4_ts;
2074
2075 ps_dec_op->u4_error_code = 0;
2076 ps_dec_op->e_pic_type = IV_NA_FRAME;
2077 ps_dec_op->u4_output_present = 0;
2078 ps_dec_op->u4_frame_decoded_flag = 0;
2079
2080 ps_dec->i4_frametype = IV_NA_FRAME;
2081 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
2082
2083 ps_dec->u4_slice_start_code_found = 0;
2084
2085 /* In case the deocder is not in flush mode(in shared mode),
2086 then decoder has to pick up a buffer to write current frame.
2087 Check if a frame is available in such cases */
2088
2089 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2090 && ps_dec->u1_flushfrm == 0)
2091 {
2092 UWORD32 i;
2093
2094 WORD32 disp_avail = 0, free_id;
2095
2096 /* Check if at least one buffer is available with the codec */
2097 /* If not then return to application with error */
2098 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2099 {
2100 if(0 == ps_dec->u4_disp_buf_mapping[i]
2101 || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2102 {
2103 disp_avail = 1;
2104 break;
2105 }
2106
2107 }
2108
2109 if(0 == disp_avail)
2110 {
2111 /* If something is queued for display wait for that buffer to be returned */
2112
2113 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2114 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2115 return (IV_FAIL);
2116 }
2117
2118 while(1)
2119 {
2120 pic_buffer_t *ps_pic_buf;
2121 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2122 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2123
2124 if(ps_pic_buf == NULL)
2125 {
2126 UWORD32 i, display_queued = 0;
2127
2128 /* check if any buffer was given for display which is not returned yet */
2129 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2130 {
2131 if(0 != ps_dec->u4_disp_buf_mapping[i])
2132 {
2133 display_queued = 1;
2134 break;
2135 }
2136 }
2137 /* If some buffer is queued for display, then codec has to singal an error and wait
2138 for that buffer to be returned.
2139 If nothing is queued for display then codec has ownership of all display buffers
2140 and it can reuse any of the existing buffers and continue decoding */
2141
2142 if(1 == display_queued)
2143 {
2144 /* If something is queued for display wait for that buffer to be returned */
2145 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2146 ps_dec_op->u4_error_code |= (1
2147 << IVD_UNSUPPORTEDPARAM);
2148 return (IV_FAIL);
2149 }
2150 }
2151 else
2152 {
2153 /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2154 if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2155 {
2156 ih264_buf_mgr_set_status(
2157 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2158 free_id,
2159 BUF_MGR_IO);
2160 }
2161 else
2162 {
2163 /**
2164 * Found a free buffer for present call. Release it now.
2165 * Will be again obtained later.
2166 */
2167 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2168 free_id,
2169 BUF_MGR_IO);
2170 break;
2171 }
2172 }
2173 }
2174
2175 }
2176
2177 if(ps_dec->u1_flushfrm)
2178 {
2179 if(ps_dec->u1_init_dec_flag == 0)
2180 {
2181 /*Come out of flush mode and return*/
2182 ps_dec->u1_flushfrm = 0;
2183 return (IV_FAIL);
2184 }
2185
2186
2187
2188 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2189 &(ps_dec->s_disp_op));
2190 if(0 == ps_dec->s_disp_op.u4_error_code)
2191 {
2192 /* check output buffer size given by the application */
2193 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2194 {
2195 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2196 return (IV_FAIL);
2197 }
2198
2199 ps_dec->u4_fmt_conv_cur_row = 0;
2200 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2201 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2202 ps_dec->u4_fmt_conv_cur_row,
2203 ps_dec->u4_fmt_conv_num_rows);
2204 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2205 ps_dec->u4_output_present = 1;
2206
2207 }
2208 ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
2209
2210 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2211
2212 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2213 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2214 ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2215 ps_dec_op->i4_display_index = ps_dec->i4_display_index;
2216
2217 ps_dec_op->u4_new_seq = 0;
2218
2219 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2220 ps_dec_op->u4_progressive_frame_flag =
2221 ps_dec->s_disp_op.u4_progressive_frame_flag;
2222 ps_dec_op->e_output_format =
2223 ps_dec->s_disp_op.e_output_format;
2224 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2225 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2226 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2227 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2228
2229 /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2230 ps_dec_op->u4_is_ref_flag = -1;
2231 ps_dec_op->e_pic_type = IV_NA_FRAME;
2232 ps_dec_op->u4_frame_decoded_flag = 0;
2233
2234 if(0 == ps_dec->s_disp_op.u4_error_code)
2235 {
2236 return (IV_SUCCESS);
2237 }
2238 else
2239 return (IV_FAIL);
2240
2241 }
2242 if(ps_dec->u1_res_changed == 1)
2243 {
2244 /*if resolution has changed and all buffers have been flushed, reset decoder*/
2245 ih264d_init_decoder(ps_dec);
2246 }
2247
2248 ps_dec->u2_cur_mb_addr = 0;
2249 ps_dec->u2_total_mbs_coded = 0;
2250 ps_dec->u2_cur_slice_num = 0;
2251 ps_dec->cur_dec_mb_num = 0;
2252 ps_dec->cur_recon_mb_num = 0;
2253 ps_dec->u4_first_slice_in_pic = 1;
2254 ps_dec->u1_slice_header_done = 0;
2255 ps_dec->u1_dangling_field = 0;
2256
2257 ps_dec->u4_dec_thread_created = 0;
2258 ps_dec->u4_bs_deblk_thread_created = 0;
2259 ps_dec->u4_cur_bs_mb_num = 0;
2260 ps_dec->u4_start_recon_deblk = 0;
2261 ps_dec->u4_sps_cnt_in_process = 0;
2262
2263 DEBUG_THREADS_PRINTF(" Starting process call\n");
2264
2265
2266 ps_dec->u4_pic_buf_got = 0;
2267
2268 do
2269 {
2270 WORD32 buf_size;
2271
2272 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2273 + ps_dec_op->u4_num_bytes_consumed;
2274
2275 u4_max_ofst = ps_dec_ip->u4_num_Bytes
2276 - ps_dec_op->u4_num_bytes_consumed;
2277
2278 /* If dynamic bitstream buffer is not allocated and
2279 * header decode is done, then allocate dynamic bitstream buffer
2280 */
2281 if((NULL == ps_dec->pu1_bits_buf_dynamic) &&
2282 (ps_dec->i4_header_decoded & 1))
2283 {
2284 WORD32 size;
2285
2286 void *pv_buf;
2287 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2288 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2);
2289 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128,
2290 size + EXTRA_BS_OFFSET);
2291 RETURN_IF((NULL == pv_buf), IV_FAIL);
2292 memset(pv_buf, 0, size + EXTRA_BS_OFFSET);
2293 ps_dec->pu1_bits_buf_dynamic = pv_buf;
2294 ps_dec->u4_dynamic_bits_buf_size = size;
2295 }
2296
2297 if(ps_dec->pu1_bits_buf_dynamic)
2298 {
2299 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic;
2300 buf_size = ps_dec->u4_dynamic_bits_buf_size;
2301 }
2302 else
2303 {
2304 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static;
2305 buf_size = ps_dec->u4_static_bits_buf_size;
2306 }
2307
2308 u4_next_is_aud = 0;
2309
2310 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2311 &u4_length_of_start_code,
2312 &u4_next_is_aud);
2313
2314 if(buflen == -1)
2315 buflen = 0;
2316 /* Ignore bytes beyond the allocated size of intermediate buffer */
2317 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2318 end of the buffer, which will be memset to 0 after emulation prevention */
2319 buflen = MIN(buflen, buf_size - 8);
2320
2321 bytes_consumed = buflen + u4_length_of_start_code;
2322 ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2323
2324 if(buflen)
2325 {
2326 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2327 buflen);
2328 /* Decoder may read extra 8 bytes near end of the frame */
2329 if((buflen + 8) < buf_size)
2330 {
2331 memset(pu1_bitstrm_buf + buflen, 0, 8);
2332 }
2333 u4_first_start_code_found = 1;
2334
2335 }
2336 else
2337 {
2338 /*start code not found*/
2339
2340 if(u4_first_start_code_found == 0)
2341 {
2342 /*no start codes found in current process call*/
2343
2344 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2345 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2346
2347 if(ps_dec->u4_pic_buf_got == 0)
2348 {
2349
2350 ih264d_fill_output_struct_from_context(ps_dec,
2351 ps_dec_op);
2352
2353 ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2354 ps_dec_op->u4_frame_decoded_flag = 0;
2355
2356 return (IV_FAIL);
2357 }
2358 else
2359 {
2360 ps_dec->u1_pic_decode_done = 1;
2361 continue;
2362 }
2363 }
2364 else
2365 {
2366 /* a start code has already been found earlier in the same process call*/
2367 frame_data_left = 0;
2368 header_data_left = 0;
2369 continue;
2370 }
2371
2372 }
2373
2374 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
2375 pu1_bitstrm_buf, buflen);
2376 if(ret != OK)
2377 {
2378 UWORD32 error = ih264d_map_error(ret);
2379 ps_dec_op->u4_error_code = error | ret;
2380 api_ret_value = IV_FAIL;
2381
2382 if((ret == IVD_RES_CHANGED)
2383 || (ret == IVD_MEM_ALLOC_FAILED)
2384 || (ret == ERROR_UNAVAIL_PICBUF_T)
2385 || (ret == ERROR_UNAVAIL_MVBUF_T)
2386 || (ret == ERROR_INV_SPS_PPS_T)
2387 || (ret == ERROR_FEATURE_UNAVAIL)
2388 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
2389 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
2390 {
2391 ps_dec->u4_slice_start_code_found = 0;
2392 break;
2393 }
2394
2395 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
2396 {
2397 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2398 api_ret_value = IV_FAIL;
2399 break;
2400 }
2401
2402 if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
2403 {
2404 api_ret_value = IV_FAIL;
2405 break;
2406 }
2407
2408 }
2409
2410 header_data_left = ((ps_dec->i4_decode_header == 1)
2411 && (ps_dec->i4_header_decoded != 3)
2412 && (ps_dec_op->u4_num_bytes_consumed
2413 < ps_dec_ip->u4_num_Bytes));
2414 frame_data_left = (((ps_dec->i4_decode_header == 0)
2415 && ((ps_dec->u1_pic_decode_done == 0)
2416 || (u4_next_is_aud == 1)))
2417 && (ps_dec_op->u4_num_bytes_consumed
2418 < ps_dec_ip->u4_num_Bytes));
2419 }
2420 while(( header_data_left == 1)||(frame_data_left == 1));
2421
2422 if((ps_dec->u4_pic_buf_got == 1)
2423 && (ret != IVD_MEM_ALLOC_FAILED)
2424 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2425 {
2426 // last slice - missing/corruption
2427 WORD32 num_mb_skipped;
2428 WORD32 prev_slice_err;
2429 pocstruct_t temp_poc;
2430 WORD32 ret1;
2431 WORD32 ht_in_mbs;
2432 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
2433 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2434 - ps_dec->u2_total_mbs_coded;
2435
2436 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
2437 prev_slice_err = 1;
2438 else
2439 prev_slice_err = 2;
2440
2441 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0))
2442 prev_slice_err = 1;
2443
2444 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
2445 &temp_poc, prev_slice_err);
2446
2447 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
2448 (ret1 == ERROR_INV_SPS_PPS_T))
2449 {
2450 ret = ret1;
2451 }
2452 }
2453
2454 if((ret == IVD_RES_CHANGED)
2455 || (ret == IVD_MEM_ALLOC_FAILED)
2456 || (ret == ERROR_UNAVAIL_PICBUF_T)
2457 || (ret == ERROR_UNAVAIL_MVBUF_T)
2458 || (ret == ERROR_INV_SPS_PPS_T))
2459 {
2460
2461 /* signal the decode thread */
2462 ih264d_signal_decode_thread(ps_dec);
2463 /* close deblock thread if it is not closed yet */
2464 if(ps_dec->u4_num_cores == 3)
2465 {
2466 ih264d_signal_bs_deblk_thread(ps_dec);
2467 }
2468 /* dont consume bitstream for change in resolution case */
2469 if(ret == IVD_RES_CHANGED)
2470 {
2471 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2472 }
2473 return IV_FAIL;
2474 }
2475
2476
2477 if(ps_dec->u1_separate_parse)
2478 {
2479 /* If Format conversion is not complete,
2480 complete it here */
2481 if(ps_dec->u4_num_cores == 2)
2482 {
2483
2484 /*do deblocking of all mbs*/
2485 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
2486 {
2487 UWORD32 u4_num_mbs,u4_max_addr;
2488 tfr_ctxt_t s_tfr_ctxt;
2489 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
2490 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
2491
2492 /*BS is done for all mbs while parsing*/
2493 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
2494 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
2495
2496
2497 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
2498 ps_dec->u2_frm_wd_in_mbs, 0);
2499
2500
2501 u4_num_mbs = u4_max_addr
2502 - ps_dec->u4_cur_deblk_mb_num + 1;
2503
2504 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
2505
2506 if(u4_num_mbs != 0)
2507 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
2508 ps_tfr_cxt,1);
2509
2510 ps_dec->u4_start_recon_deblk = 0;
2511
2512 }
2513
2514 }
2515
2516 /*signal the decode thread*/
2517 ih264d_signal_decode_thread(ps_dec);
2518 /* close deblock thread if it is not closed yet*/
2519 if(ps_dec->u4_num_cores == 3)
2520 {
2521 ih264d_signal_bs_deblk_thread(ps_dec);
2522 }
2523 }
2524
2525
2526 DATA_SYNC();
2527
2528
2529 if((ps_dec_op->u4_error_code & 0xff)
2530 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
2531 {
2532 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2533 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2534 ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2535 }
2536
2537 //Report if header (sps and pps) has not been decoded yet
2538 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
2539 {
2540 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2541 api_ret_value = IV_FAIL;
2542 }
2543
2544 if((ps_dec->u4_pic_buf_got == 1)
2545 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
2546 {
2547 /*
2548 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2549 */
2550
2551 if(ps_dec->ps_cur_slice->u1_field_pic_flag)
2552 {
2553 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
2554 {
2555 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
2556 }
2557 else
2558 {
2559 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
2560 }
2561 }
2562 else
2563 {
2564 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
2565 }
2566
2567 /* if new frame in not found (if we are still getting slices from previous frame)
2568 * ih264d_deblock_display is not called. Such frames will not be added to reference /display
2569 */
2570 if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
2571 {
2572 /* Calling Function to deblock Picture and Display */
2573 ret = ih264d_deblock_display(ps_dec);
2574 }
2575
2576
2577 /*set to complete ,as we dont support partial frame decode*/
2578 if(ps_dec->i4_header_decoded == 3)
2579 {
2580 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
2581 }
2582
2583 /*Update the i4_frametype at the end of picture*/
2584 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
2585 {
2586 ps_dec->i4_frametype = IV_IDR_FRAME;
2587 }
2588 else if(ps_dec->i4_pic_type == B_SLICE)
2589 {
2590 ps_dec->i4_frametype = IV_B_FRAME;
2591 }
2592 else if(ps_dec->i4_pic_type == P_SLICE)
2593 {
2594 ps_dec->i4_frametype = IV_P_FRAME;
2595 }
2596 else if(ps_dec->i4_pic_type == I_SLICE)
2597 {
2598 ps_dec->i4_frametype = IV_I_FRAME;
2599 }
2600 else
2601 {
2602 H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
2603 }
2604
2605 //Update the content type
2606 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
2607
2608 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
2609 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
2610 - ps_dec->ps_cur_slice->u1_field_pic_flag;
2611
2612 }
2613
2614 /* close deblock thread if it is not closed yet*/
2615 if(ps_dec->u4_num_cores == 3)
2616 {
2617 ih264d_signal_bs_deblk_thread(ps_dec);
2618 }
2619
2620
2621 {
2622 /* In case the decoder is configured to run in low delay mode,
2623 * then get display buffer and then format convert.
2624 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
2625 */
2626
2627 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
2628 && ps_dec->u1_init_dec_flag)
2629 {
2630
2631 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2632 &(ps_dec->s_disp_op));
2633 if(0 == ps_dec->s_disp_op.u4_error_code)
2634 {
2635 ps_dec->u4_fmt_conv_cur_row = 0;
2636 ps_dec->u4_output_present = 1;
2637 }
2638 }
2639
2640 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2641
2642 /* If Format conversion is not complete,
2643 complete it here */
2644 if(ps_dec->u4_output_present &&
2645 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
2646 {
2647 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
2648 - ps_dec->u4_fmt_conv_cur_row;
2649 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2650 ps_dec->u4_fmt_conv_cur_row,
2651 ps_dec->u4_fmt_conv_num_rows);
2652 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2653 }
2654
2655 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2656 }
2657
2658 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
2659 {
2660 ps_dec_op->u4_progressive_frame_flag = 1;
2661 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2662 {
2663 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
2664 && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
2665 ps_dec_op->u4_progressive_frame_flag = 0;
2666
2667 }
2668 }
2669
2670 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2671 {
2672 ps_dec->u1_top_bottom_decoded = 0;
2673 }
2674 /*--------------------------------------------------------------------*/
2675 /* Do End of Pic processing. */
2676 /* Should be called only if frame was decoded in previous process call*/
2677 /*--------------------------------------------------------------------*/
2678 if(ps_dec->u4_pic_buf_got == 1)
2679 {
2680 if(1 == ps_dec->u1_last_pic_not_decoded)
2681 {
2682 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
2683
2684 if(ret != OK)
2685 return ret;
2686
2687 ret = ih264d_end_of_pic(ps_dec);
2688 if(ret != OK)
2689 return ret;
2690 }
2691 else
2692 {
2693 ret = ih264d_end_of_pic(ps_dec);
2694 if(ret != OK)
2695 return ret;
2696 }
2697
2698 }
2699
2700
2701 /*Data memory barrier instruction,so that yuv write by the library is complete*/
2702 DATA_SYNC();
2703
2704 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
2705 ps_dec_op->u4_num_bytes_consumed);
2706 return api_ret_value;
2707 }
2708
ih264d_get_version(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2709 WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2710 {
2711 char version_string[MAXVERSION_STRLEN + 1];
2712 UWORD32 version_string_len;
2713
2714 ivd_ctl_getversioninfo_ip_t *ps_ip;
2715 ivd_ctl_getversioninfo_op_t *ps_op;
2716
2717 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
2718 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
2719 UNUSED(dec_hdl);
2720 ps_op->u4_error_code = IV_SUCCESS;
2721
2722 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
2723 CODEC_VENDOR);
2724
2725 if((WORD32)ps_ip->u4_version_buffer_size <= 0)
2726 {
2727 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2728 return (IV_FAIL);
2729 }
2730
2731 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1;
2732
2733 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
2734 {
2735 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
2736 ps_op->u4_error_code = IV_SUCCESS;
2737 }
2738 else
2739 {
2740 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2741 return IV_FAIL;
2742 }
2743 return (IV_SUCCESS);
2744 }
2745
2746 /*****************************************************************************/
2747 /* */
2748 /* Function Name : ih264d_get_display_frame */
2749 /* */
2750 /* Description : */
2751 /* Inputs :iv_obj_t decoder handle */
2752 /* :pv_api_ip pointer to input structure */
2753 /* :pv_api_op pointer to output structure */
2754 /* Outputs : */
2755 /* Returns : void */
2756 /* */
2757 /* Issues : none */
2758 /* */
2759 /* Revision History: */
2760 /* */
2761 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2762 /* 22 10 2008 100356 Draft */
2763 /* */
2764 /*****************************************************************************/
ih264d_get_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2765 WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
2766 void *pv_api_ip,
2767 void *pv_api_op)
2768 {
2769
2770 UNUSED(dec_hdl);
2771 UNUSED(pv_api_ip);
2772 UNUSED(pv_api_op);
2773 // This function is no longer needed, output is returned in the process()
2774 return IV_FAIL;
2775 }
2776
2777 /*****************************************************************************/
2778 /* */
2779 /* Function Name : ih264d_set_display_frame */
2780 /* */
2781 /* Description : */
2782 /* */
2783 /* Inputs :iv_obj_t decoder handle */
2784 /* :pv_api_ip pointer to input structure */
2785 /* :pv_api_op pointer to output structure */
2786 /* Outputs : */
2787 /* Returns : void */
2788 /* */
2789 /* Issues : none */
2790 /* */
2791 /* Revision History: */
2792 /* */
2793 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2794 /* 22 10 2008 100356 Draft */
2795 /* */
2796 /*****************************************************************************/
ih264d_set_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2797 WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
2798 void *pv_api_ip,
2799 void *pv_api_op)
2800 {
2801
2802 UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs;
2803 ivd_set_display_frame_ip_t *dec_disp_ip;
2804 ivd_set_display_frame_op_t *dec_disp_op;
2805
2806 UWORD32 i;
2807 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2808
2809 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
2810 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
2811 dec_disp_op->u4_error_code = 0;
2812
2813
2814 ps_dec->u4_num_disp_bufs = 0;
2815 if(ps_dec->u4_share_disp_buf)
2816 {
2817 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
2818
2819 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
2820
2821 ps_dec->u4_num_disp_bufs = u4_num_bufs;
2822
2823 /* Get the number and sizes of the first buffer. Compare this with the
2824 * rest to make sure all the buffers are of the same size.
2825 */
2826 u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
2827
2828 u4_disp_buf_size[0] =
2829 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
2830 u4_disp_buf_size[1] =
2831 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
2832 u4_disp_buf_size[2] =
2833 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
2834
2835 for(i = 0; i < u4_num_bufs; i++)
2836 {
2837 if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs)
2838 {
2839 return IV_FAIL;
2840 }
2841
2842 if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
2843 != u4_disp_buf_size[0])
2844 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
2845 != u4_disp_buf_size[1])
2846 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
2847 != u4_disp_buf_size[2]))
2848 {
2849 return IV_FAIL;
2850 }
2851
2852 ps_dec->disp_bufs[i].u4_num_bufs =
2853 dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
2854
2855 ps_dec->disp_bufs[i].buf[0] =
2856 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
2857 ps_dec->disp_bufs[i].buf[1] =
2858 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
2859 ps_dec->disp_bufs[i].buf[2] =
2860 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
2861
2862 ps_dec->disp_bufs[i].u4_bufsize[0] =
2863 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
2864 ps_dec->disp_bufs[i].u4_bufsize[1] =
2865 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
2866 ps_dec->disp_bufs[i].u4_bufsize[2] =
2867 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
2868
2869 }
2870 }
2871 return IV_SUCCESS;
2872
2873 }
2874
2875 /*****************************************************************************/
2876 /* */
2877 /* Function Name : ih264d_set_flush_mode */
2878 /* */
2879 /* Description : */
2880 /* */
2881 /* Inputs :iv_obj_t decoder handle */
2882 /* :pv_api_ip pointer to input structure */
2883 /* :pv_api_op pointer to output structure */
2884 /* Globals : <Does it use any global variables?> */
2885 /* Outputs : */
2886 /* Returns : void */
2887 /* */
2888 /* Issues : none */
2889 /* */
2890 /* Revision History: */
2891 /* */
2892 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2893 /* 22 10 2008 100356 Draft */
2894 /* */
2895 /*****************************************************************************/
ih264d_set_flush_mode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2896 WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2897 {
2898 dec_struct_t * ps_dec;
2899 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
2900 ps_ctl_op->u4_error_code = 0;
2901
2902 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2903 UNUSED(pv_api_ip);
2904 /* ! */
2905 /* Signal flush frame control call */
2906 ps_dec->u1_flushfrm = 1;
2907
2908 if(ps_dec->u1_init_dec_flag == 1)
2909 {
2910 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs);
2911 ih264d_release_display_bufs(ps_dec);
2912 }
2913
2914 ps_ctl_op->u4_error_code = 0;
2915
2916 /* Ignore dangling fields during flush */
2917 ps_dec->u1_top_bottom_decoded = 0;
2918
2919 return IV_SUCCESS;
2920 }
2921
2922 /*****************************************************************************/
2923 /* */
2924 /* Function Name : ih264d_get_status */
2925 /* */
2926 /* Description : */
2927 /* */
2928 /* Inputs :iv_obj_t decoder handle */
2929 /* :pv_api_ip pointer to input structure */
2930 /* :pv_api_op pointer to output structure */
2931 /* Globals : <Does it use any global variables?> */
2932 /* Outputs : */
2933 /* Returns : void */
2934 /* */
2935 /* Issues : none */
2936 /* */
2937 /* Revision History: */
2938 /* */
2939 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2940 /* 22 10 2008 100356 Draft */
2941 /* */
2942 /*****************************************************************************/
2943
ih264d_get_status(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2944 WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2945 {
2946
2947 UWORD32 i;
2948 dec_struct_t * ps_dec;
2949 UWORD32 pic_wd, pic_ht;
2950 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
2951 UNUSED(pv_api_ip);
2952 ps_ctl_op->u4_error_code = 0;
2953
2954 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2955
2956
2957 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2958 {
2959 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
2960 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
2961
2962 if(0 == ps_dec->u4_share_disp_buf)
2963 {
2964 pic_wd = ps_dec->u2_disp_width;
2965 pic_ht = ps_dec->u2_disp_height;
2966
2967 }
2968 else
2969 {
2970 pic_wd = ps_dec->u2_frm_wd_y;
2971 pic_ht = ps_dec->u2_frm_ht_y;
2972 }
2973 }
2974 else
2975 {
2976 pic_wd = 0;
2977 pic_ht = 0;
2978
2979 ps_ctl_op->u4_pic_ht = pic_wd;
2980 ps_ctl_op->u4_pic_wd = pic_ht;
2981
2982 if(1 == ps_dec->u4_share_disp_buf)
2983 {
2984 pic_wd += (PAD_LEN_Y_H << 1);
2985 pic_ht += (PAD_LEN_Y_V << 2);
2986
2987 }
2988
2989 }
2990
2991 if(ps_dec->u4_app_disp_width > pic_wd)
2992 pic_wd = ps_dec->u4_app_disp_width;
2993 if(0 == ps_dec->u4_share_disp_buf)
2994 ps_ctl_op->u4_num_disp_bufs = 1;
2995 else
2996 {
2997 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2998 {
2999 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3000 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3001 {
3002 ps_ctl_op->u4_num_disp_bufs =
3003 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3004 }
3005 else
3006 {
3007 /*if VUI is not present assume maximum possible refrence frames for the level,
3008 * as max reorder frames*/
3009 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3010 }
3011
3012 ps_ctl_op->u4_num_disp_bufs +=
3013 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3014 }
3015 else
3016 {
3017 ps_ctl_op->u4_num_disp_bufs = 32;
3018 }
3019 ps_ctl_op->u4_num_disp_bufs = MAX(
3020 ps_ctl_op->u4_num_disp_bufs, 6);
3021 ps_ctl_op->u4_num_disp_bufs = MIN(
3022 ps_ctl_op->u4_num_disp_bufs, 32);
3023 }
3024
3025 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3026
3027 ps_ctl_op->u4_frame_rate = 0; //make it proper
3028 ps_ctl_op->u4_bit_rate = 0; //make it proper
3029 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3030 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3031 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3032
3033 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3034 {
3035 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3036 }
3037 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3038 {
3039 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3040 }
3041 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3042 {
3043 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3044 }
3045 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3046 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3047 {
3048 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3049 }
3050
3051 else
3052 {
3053 //Invalid chroma format; Error code may be updated, verify in testing if needed
3054 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3055 return IV_FAIL;
3056 }
3057
3058 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3059 {
3060 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3061 }
3062
3063 /*!*/
3064 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3065 {
3066 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3067 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3068 >> 2;
3069 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3070 >> 2;
3071 }
3072 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3073 {
3074 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3075 * 2;
3076 ps_ctl_op->u4_min_out_buf_size[1] =
3077 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3078 }
3079 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3080 {
3081 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3082 * 2;
3083 ps_ctl_op->u4_min_out_buf_size[1] =
3084 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3085 }
3086 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3087 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3088 {
3089 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3090 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3091 >> 1;
3092 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3093 }
3094
3095 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3096 return IV_SUCCESS;
3097 }
3098
3099 /*****************************************************************************/
3100 /* */
3101 /* Function Name : ih264d_get_buf_info */
3102 /* */
3103 /* Description : */
3104 /* */
3105 /* Inputs :iv_obj_t decoder handle */
3106 /* :pv_api_ip pointer to input structure */
3107 /* :pv_api_op pointer to output structure */
3108 /* Globals : <Does it use any global variables?> */
3109 /* Outputs : */
3110 /* Returns : void */
3111 /* */
3112 /* Issues : none */
3113 /* */
3114 /* Revision History: */
3115 /* */
3116 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3117 /* 22 10 2008 100356 Draft */
3118 /* */
3119 /*****************************************************************************/
ih264d_get_buf_info(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3120 WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3121 {
3122
3123 dec_struct_t * ps_dec;
3124 UWORD8 i = 0; // Default for 420P format
3125 UWORD16 pic_wd, pic_ht;
3126 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3127 (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3128 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
3129 UNUSED(pv_api_ip);
3130
3131 ps_ctl_op->u4_error_code = 0;
3132
3133 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3134
3135 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3136
3137
3138 ps_ctl_op->u4_num_disp_bufs = 1;
3139
3140
3141 pic_wd = 0;
3142 pic_ht = 0;
3143
3144 if(ps_dec->i4_header_decoded == 3)
3145 {
3146
3147 if(0 == ps_dec->u4_share_disp_buf)
3148 {
3149 pic_wd = ps_dec->u2_disp_width;
3150 pic_ht = ps_dec->u2_disp_height;
3151
3152 }
3153 else
3154 {
3155 pic_wd = ps_dec->u2_frm_wd_y;
3156 pic_ht = ps_dec->u2_frm_ht_y;
3157 }
3158
3159 }
3160
3161 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3162 {
3163 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3164 }
3165 if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3166 pic_wd = ps_dec->u4_app_disp_width;
3167
3168 if(0 == ps_dec->u4_share_disp_buf)
3169 ps_ctl_op->u4_num_disp_bufs = 1;
3170 else
3171 {
3172 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3173 {
3174 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3175 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3176 {
3177 ps_ctl_op->u4_num_disp_bufs =
3178 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3179 }
3180 else
3181 {
3182 /*if VUI is not present assume maximum possible refrence frames for the level,
3183 * as max reorder frames*/
3184 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3185 }
3186
3187 ps_ctl_op->u4_num_disp_bufs +=
3188 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3189
3190 }
3191 else
3192 {
3193 ps_ctl_op->u4_num_disp_bufs = 32;
3194
3195 }
3196
3197 ps_ctl_op->u4_num_disp_bufs = MAX(
3198 ps_ctl_op->u4_num_disp_bufs, 6);
3199 ps_ctl_op->u4_num_disp_bufs = MIN(
3200 ps_ctl_op->u4_num_disp_bufs, 32);
3201 }
3202
3203 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3204 pic_wd, pic_ht, ps_dec->u1_chroma_format,
3205 &au4_min_out_buf_size[0]);
3206
3207 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3208 {
3209 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3210 }
3211
3212 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3213
3214 return IV_SUCCESS;
3215 }
3216
3217 /*****************************************************************************/
3218 /* */
3219 /* Function Name : ih264d_set_params */
3220 /* */
3221 /* Description : */
3222 /* */
3223 /* Inputs :iv_obj_t decoder handle */
3224 /* :pv_api_ip pointer to input structure */
3225 /* :pv_api_op pointer to output structure */
3226 /* Outputs : */
3227 /* Returns : void */
3228 /* */
3229 /* Issues : none */
3230 /* */
3231 /* Revision History: */
3232 /* */
3233 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3234 /* 22 10 2008 100356 Draft */
3235 /* */
3236 /*****************************************************************************/
ih264d_set_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3237 WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3238 {
3239
3240 dec_struct_t * ps_dec;
3241 WORD32 ret = IV_SUCCESS;
3242
3243 ih264d_ctl_set_config_ip_t *ps_h264d_ctl_ip =
3244 (ih264d_ctl_set_config_ip_t *)pv_api_ip;
3245 ih264d_ctl_set_config_op_t *ps_h264d_ctl_op =
3246 (ih264d_ctl_set_config_op_t *)pv_api_op;;
3247 ivd_ctl_set_config_ip_t *ps_ctl_ip =
3248 &ps_h264d_ctl_ip->s_ivd_ctl_set_config_ip_t;
3249 ivd_ctl_set_config_op_t *ps_ctl_op =
3250 &ps_h264d_ctl_op->s_ivd_ctl_set_config_op_t;
3251
3252 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3253
3254 ps_dec->u4_skip_frm_mask = 0;
3255
3256 ps_ctl_op->u4_error_code = 0;
3257
3258 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
3259 {
3260 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3261 ret = IV_FAIL;
3262 }
3263
3264 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_disp_width)
3265 {
3266 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3267 }
3268 else if(0 == ps_dec->i4_header_decoded)
3269 {
3270 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3271 }
3272 else if(ps_ctl_ip->u4_disp_wd == 0)
3273 {
3274 ps_dec->u4_app_disp_width = 0;
3275 }
3276 else
3277 {
3278 /*
3279 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
3280 * does not propogate.
3281 */
3282 ps_dec->u4_app_disp_width = 0;
3283 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3284 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3285 ret = IV_FAIL;
3286 }
3287
3288 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
3289 ps_dec->i4_decode_header = 0;
3290 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
3291 ps_dec->i4_decode_header = 1;
3292 else
3293 {
3294 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3295 ps_dec->i4_decode_header = 1;
3296 ret = IV_FAIL;
3297 }
3298 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
3299
3300 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
3301 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
3302 {
3303 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3304 ret = IV_FAIL;
3305 }
3306 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode;
3307 return ret;
3308
3309 }
3310
3311 /*****************************************************************************/
3312 /* */
3313 /* Function Name : ih264d_set_default_params */
3314 /* */
3315 /* Description : */
3316 /* */
3317 /* Inputs :iv_obj_t decoder handle */
3318 /* :pv_api_ip pointer to input structure */
3319 /* :pv_api_op pointer to output structure */
3320 /* Outputs : */
3321 /* Returns : void */
3322 /* */
3323 /* Issues : none */
3324 /* */
3325 /* Revision History: */
3326 /* */
3327 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3328 /* 08 08 2011 100421 Copied from set_params */
3329 /* */
3330 /*****************************************************************************/
ih264d_set_default_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3331 WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
3332 void *pv_api_ip,
3333 void *pv_api_op)
3334 {
3335
3336 dec_struct_t * ps_dec;
3337 WORD32 ret = IV_SUCCESS;
3338
3339 ivd_ctl_set_config_op_t *ps_ctl_op =
3340 (ivd_ctl_set_config_op_t *)pv_api_op;
3341 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3342 UNUSED(pv_api_ip);
3343
3344
3345 {
3346 ps_dec->u4_app_disp_width = 0;
3347 ps_dec->u4_skip_frm_mask = 0;
3348 ps_dec->i4_decode_header = 1;
3349
3350 ps_ctl_op->u4_error_code = 0;
3351 }
3352
3353
3354 return ret;
3355 }
3356 /*****************************************************************************/
3357 /* */
3358 /* Function Name : ih264d_reset */
3359 /* */
3360 /* Description : */
3361 /* */
3362 /* Inputs :iv_obj_t decoder handle */
3363 /* :pv_api_ip pointer to input structure */
3364 /* :pv_api_op pointer to output structure */
3365 /* Globals : <Does it use any global variables?> */
3366 /* Outputs : */
3367 /* Returns : void */
3368 /* */
3369 /* Issues : none */
3370 /* */
3371 /* Revision History: */
3372 /* */
3373 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3374 /* 22 10 2008 100356 Draft */
3375 /* */
3376 /*****************************************************************************/
ih264d_delete(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3377 WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3378 {
3379 dec_struct_t *ps_dec;
3380 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip;
3381 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op;
3382
3383 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3384 UNUSED(ps_ip);
3385 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
3386 ih264d_free_dynamic_bufs(ps_dec);
3387 ih264d_free_static_bufs(dec_hdl);
3388 return IV_SUCCESS;
3389 }
3390 /*****************************************************************************/
3391 /* */
3392 /* Function Name : ih264d_reset */
3393 /* */
3394 /* Description : */
3395 /* */
3396 /* Inputs :iv_obj_t decoder handle */
3397 /* :pv_api_ip pointer to input structure */
3398 /* :pv_api_op pointer to output structure */
3399 /* Globals : <Does it use any global variables?> */
3400 /* Outputs : */
3401 /* Returns : void */
3402 /* */
3403 /* Issues : none */
3404 /* */
3405 /* Revision History: */
3406 /* */
3407 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3408 /* 22 10 2008 100356 Draft */
3409 /* */
3410 /*****************************************************************************/
ih264d_reset(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3411 WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3412 {
3413 dec_struct_t * ps_dec;
3414 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3415 UNUSED(pv_api_ip);
3416 ps_ctl_op->u4_error_code = 0;
3417
3418 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3419
3420 if(ps_dec != NULL)
3421 {
3422 ih264d_init_decoder(ps_dec);
3423 }
3424 else
3425 {
3426 H264_DEC_DEBUG_PRINT(
3427 "\nReset called without Initializing the decoder\n");
3428 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3429 }
3430
3431 return IV_SUCCESS;
3432 }
3433
3434 /*****************************************************************************/
3435 /* */
3436 /* Function Name : ih264d_ctl */
3437 /* */
3438 /* Description : */
3439 /* */
3440 /* Inputs :iv_obj_t decoder handle */
3441 /* :pv_api_ip pointer to input structure */
3442 /* :pv_api_op pointer to output structure */
3443 /* Outputs : */
3444 /* Returns : void */
3445 /* */
3446 /* Issues : none */
3447 /* */
3448 /* Revision History: */
3449 /* */
3450 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3451 /* 22 10 2008 100356 Draft */
3452 /* */
3453 /*****************************************************************************/
ih264d_ctl(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3454 WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3455 {
3456 ivd_ctl_set_config_ip_t *ps_ctl_ip;
3457 ivd_ctl_set_config_op_t *ps_ctl_op;
3458 WORD32 ret = IV_SUCCESS;
3459 UWORD32 subcommand;
3460 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3461
3462 if(ps_dec->init_done != 1)
3463 {
3464 //Return proper Error Code
3465 return IV_FAIL;
3466 }
3467 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
3468 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3469 ps_ctl_op->u4_error_code = 0;
3470 subcommand = ps_ctl_ip->e_sub_cmd;
3471
3472 switch(subcommand)
3473 {
3474 case IVD_CMD_CTL_GETPARAMS:
3475 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
3476 (void *)pv_api_op);
3477 break;
3478 case IVD_CMD_CTL_SETPARAMS:
3479 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
3480 (void *)pv_api_op);
3481 break;
3482 case IVD_CMD_CTL_RESET:
3483 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
3484 break;
3485 case IVD_CMD_CTL_SETDEFAULT:
3486 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
3487 (void *)pv_api_op);
3488 break;
3489 case IVD_CMD_CTL_FLUSH:
3490 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
3491 (void *)pv_api_op);
3492 break;
3493 case IVD_CMD_CTL_GETBUFINFO:
3494 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
3495 (void *)pv_api_op);
3496 break;
3497 case IVD_CMD_CTL_GETVERSION:
3498 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
3499 (void *)pv_api_op);
3500 break;
3501 case IH264D_CMD_CTL_DEGRADE:
3502 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
3503 (void *)pv_api_op);
3504 break;
3505
3506 case IH264D_CMD_CTL_SET_NUM_CORES:
3507 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
3508 (void *)pv_api_op);
3509 break;
3510 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3511 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
3512 (void *)pv_api_op);
3513 break;
3514 case IH264D_CMD_CTL_GET_VUI_PARAMS:
3515 ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip,
3516 (void *)pv_api_op);
3517 break;
3518 case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
3519 ret = ih264d_get_sei_mdcv_params(dec_hdl, (void *)pv_api_ip,
3520 (void *)pv_api_op);
3521 break;
3522 case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
3523 ret = ih264d_get_sei_cll_params(dec_hdl, (void *)pv_api_ip,
3524 (void *)pv_api_op);
3525 break;
3526 case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
3527 ret = ih264d_get_sei_ave_params(dec_hdl, (void *)pv_api_ip,
3528 (void *)pv_api_op);
3529 break;
3530 case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
3531 ret = ih264d_get_sei_ccv_params(dec_hdl, (void *)pv_api_ip,
3532 (void *)pv_api_op);
3533 break;
3534 case IH264D_CMD_CTL_SET_PROCESSOR:
3535 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
3536 (void *)pv_api_op);
3537 break;
3538 default:
3539 H264_DEC_DEBUG_PRINT("\ndo nothing\n")
3540 ;
3541 break;
3542 }
3543
3544 return ret;
3545 }
3546 /*****************************************************************************/
3547 /* */
3548 /* Function Name : ih264d_rel_display_frame */
3549 /* */
3550 /* Description : */
3551 /* */
3552 /* Inputs :iv_obj_t decoder handle */
3553 /* :pv_api_ip pointer to input structure */
3554 /* :pv_api_op pointer to output structure */
3555 /* Outputs : */
3556 /* Returns : void */
3557 /* */
3558 /* Issues : none */
3559 /* */
3560 /* Revision History: */
3561 /* */
3562 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3563 /* 22 10 2008 100356 Draft */
3564 /* */
3565 /*****************************************************************************/
ih264d_rel_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3566 WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
3567 void *pv_api_ip,
3568 void *pv_api_op)
3569 {
3570
3571 ivd_rel_display_frame_ip_t *ps_rel_ip;
3572 ivd_rel_display_frame_op_t *ps_rel_op;
3573 UWORD32 buf_released = 0;
3574
3575 UWORD32 u4_ts = 0;
3576 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3577
3578 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
3579 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
3580 ps_rel_op->u4_error_code = 0;
3581 u4_ts = ps_rel_ip->u4_disp_buf_id;
3582
3583 if(0 == ps_dec->u4_share_disp_buf)
3584 {
3585 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3586 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
3587 return IV_SUCCESS;
3588 }
3589
3590 if(ps_dec->pv_pic_buf_mgr != NULL)
3591 {
3592 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
3593 {
3594 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
3595 ps_rel_ip->u4_disp_buf_id,
3596 BUF_MGR_IO);
3597 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3598 buf_released = 1;
3599 }
3600 }
3601
3602 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
3603 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
3604
3605 return IV_SUCCESS;
3606 }
3607
3608 /**
3609 *******************************************************************************
3610 *
3611 * @brief
3612 * Sets degrade params
3613 *
3614 * @par Description:
3615 * Sets degrade params.
3616 * Refer to ih264d_ctl_degrade_ip_t definition for details
3617 *
3618 * @param[in] ps_codec_obj
3619 * Pointer to codec object at API level
3620 *
3621 * @param[in] pv_api_ip
3622 * Pointer to input argument structure
3623 *
3624 * @param[out] pv_api_op
3625 * Pointer to output argument structure
3626 *
3627 * @returns Status
3628 *
3629 * @remarks
3630 *
3631 *
3632 *******************************************************************************
3633 */
3634
ih264d_set_degrade(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)3635 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
3636 void *pv_api_ip,
3637 void *pv_api_op)
3638 {
3639 ih264d_ctl_degrade_ip_t *ps_ip;
3640 ih264d_ctl_degrade_op_t *ps_op;
3641 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
3642
3643 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
3644 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
3645
3646 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
3647 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
3648 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
3649
3650 ps_op->u4_error_code = 0;
3651 ps_codec->i4_degrade_pic_cnt = 0;
3652
3653 return IV_SUCCESS;
3654 }
3655
ih264d_get_frame_dimensions(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3656 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
3657 void *pv_api_ip,
3658 void *pv_api_op)
3659 {
3660 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
3661 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
3662 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3663 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
3664
3665 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3666
3667 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3668 UNUSED(ps_ip);
3669 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3670 {
3671 disp_wd = ps_dec->u2_disp_width;
3672 disp_ht = ps_dec->u2_disp_height;
3673
3674 if(0 == ps_dec->u4_share_disp_buf)
3675 {
3676 buffer_wd = disp_wd;
3677 buffer_ht = disp_ht;
3678 }
3679 else
3680 {
3681 buffer_wd = ps_dec->u2_frm_wd_y;
3682 buffer_ht = ps_dec->u2_frm_ht_y;
3683 }
3684 }
3685 else
3686 {
3687 disp_wd = 0;
3688 disp_ht = 0;
3689
3690 if(0 == ps_dec->u4_share_disp_buf)
3691 {
3692 buffer_wd = disp_wd;
3693 buffer_ht = disp_ht;
3694 }
3695 else
3696 {
3697 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
3698 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
3699 }
3700 }
3701 if(ps_dec->u4_app_disp_width > buffer_wd)
3702 buffer_wd = ps_dec->u4_app_disp_width;
3703
3704 if(0 == ps_dec->u4_share_disp_buf)
3705 {
3706 x_offset = 0;
3707 y_offset = 0;
3708 }
3709 else
3710 {
3711 y_offset = (PAD_LEN_Y_V << 1);
3712 x_offset = PAD_LEN_Y_H;
3713
3714 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
3715 && (0 != ps_dec->u2_crop_offset_y))
3716 {
3717 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
3718 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
3719 }
3720 }
3721
3722 ps_op->u4_disp_wd[0] = disp_wd;
3723 ps_op->u4_disp_ht[0] = disp_ht;
3724 ps_op->u4_buffer_wd[0] = buffer_wd;
3725 ps_op->u4_buffer_ht[0] = buffer_ht;
3726 ps_op->u4_x_offset[0] = x_offset;
3727 ps_op->u4_y_offset[0] = y_offset;
3728
3729 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
3730 >> 1);
3731 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
3732 >> 1);
3733 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
3734 >> 1);
3735 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
3736 >> 1);
3737 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
3738 (ps_op->u4_x_offset[0] >> 1);
3739 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
3740 (ps_op->u4_y_offset[0] >> 1);
3741
3742 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3743 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3744 {
3745 ps_op->u4_disp_wd[2] = 0;
3746 ps_op->u4_disp_ht[2] = 0;
3747 ps_op->u4_buffer_wd[2] = 0;
3748 ps_op->u4_buffer_ht[2] = 0;
3749 ps_op->u4_x_offset[2] = 0;
3750 ps_op->u4_y_offset[2] = 0;
3751
3752 ps_op->u4_disp_wd[1] <<= 1;
3753 ps_op->u4_buffer_wd[1] <<= 1;
3754 ps_op->u4_x_offset[1] <<= 1;
3755 }
3756
3757 return IV_SUCCESS;
3758
3759 }
3760
ih264d_get_vui_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3761 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
3762 void *pv_api_ip,
3763 void *pv_api_op)
3764 {
3765 ih264d_ctl_get_vui_params_ip_t *ps_ip;
3766 ih264d_ctl_get_vui_params_op_t *ps_op;
3767 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3768 dec_seq_params_t *ps_sps;
3769 vui_t *ps_vui;
3770 WORD32 i;
3771 UWORD32 u4_size;
3772
3773 ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
3774 ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
3775 UNUSED(ps_ip);
3776
3777 u4_size = ps_op->u4_size;
3778 memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t));
3779 ps_op->u4_size = u4_size;
3780
3781 if(NULL == ps_dec->ps_cur_sps)
3782 {
3783 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
3784 return IV_FAIL;
3785 }
3786
3787 ps_sps = ps_dec->ps_cur_sps;
3788 if((0 == ps_sps->u1_is_valid)
3789 || (0 == ps_sps->u1_vui_parameters_present_flag))
3790 {
3791 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
3792 return IV_FAIL;
3793 }
3794
3795 ps_vui = &ps_sps->s_vui;
3796
3797 ps_op->u1_aspect_ratio_idc = ps_vui->u1_aspect_ratio_idc;
3798 ps_op->u2_sar_width = ps_vui->u2_sar_width;
3799 ps_op->u2_sar_height = ps_vui->u2_sar_height;
3800 ps_op->u1_overscan_appropriate_flag = ps_vui->u1_overscan_appropriate_flag;
3801 ps_op->u1_video_format = ps_vui->u1_video_format;
3802 ps_op->u1_video_full_range_flag = ps_vui->u1_video_full_range_flag;
3803 ps_op->u1_colour_primaries = ps_vui->u1_colour_primaries;
3804 ps_op->u1_tfr_chars = ps_vui->u1_tfr_chars;
3805 ps_op->u1_matrix_coeffs = ps_vui->u1_matrix_coeffs;
3806 ps_op->u1_cr_top_field = ps_vui->u1_cr_top_field;
3807 ps_op->u1_cr_bottom_field = ps_vui->u1_cr_bottom_field;
3808 ps_op->u4_num_units_in_tick = ps_vui->u4_num_units_in_tick;
3809 ps_op->u4_time_scale = ps_vui->u4_time_scale;
3810 ps_op->u1_fixed_frame_rate_flag = ps_vui->u1_fixed_frame_rate_flag;
3811 ps_op->u1_nal_hrd_params_present = ps_vui->u1_nal_hrd_params_present;
3812 ps_op->u1_vcl_hrd_params_present = ps_vui->u1_vcl_hrd_params_present;
3813 ps_op->u1_low_delay_hrd_flag = ps_vui->u1_low_delay_hrd_flag;
3814 ps_op->u1_pic_struct_present_flag = ps_vui->u1_pic_struct_present_flag;
3815 ps_op->u1_bitstream_restriction_flag = ps_vui->u1_bitstream_restriction_flag;
3816 ps_op->u1_mv_over_pic_boundaries_flag = ps_vui->u1_mv_over_pic_boundaries_flag;
3817 ps_op->u4_max_bytes_per_pic_denom = ps_vui->u4_max_bytes_per_pic_denom;
3818 ps_op->u4_max_bits_per_mb_denom = ps_vui->u4_max_bits_per_mb_denom;
3819 ps_op->u4_log2_max_mv_length_horz = ps_vui->u4_log2_max_mv_length_horz;
3820 ps_op->u4_log2_max_mv_length_vert = ps_vui->u4_log2_max_mv_length_vert;
3821 ps_op->u4_num_reorder_frames = ps_vui->u4_num_reorder_frames;
3822 ps_op->u4_max_dec_frame_buffering = ps_vui->u4_max_dec_frame_buffering;
3823
3824 return IV_SUCCESS;
3825 }
3826 /*****************************************************************************/
3827 /* */
3828 /* Function Name : ih264d_get_sei_mdcv_params */
3829 /* */
3830 /* Description : This function populates SEI mdcv message in */
3831 /* output structure */
3832 /* Inputs : iv_obj_t decoder handle */
3833 /* : pv_api_ip pointer to input structure */
3834 /* : pv_api_op pointer to output structure */
3835 /* Outputs : */
3836 /* Returns : returns 0; 1 with error code when MDCV is not present */
3837 /* */
3838 /* Issues : none */
3839 /* */
3840 /* Revision History: */
3841 /* */
3842 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3843 /* */
3844 /* */
3845 /*****************************************************************************/
ih264d_get_sei_mdcv_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3846 WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
3847 void *pv_api_ip,
3848 void *pv_api_op)
3849 {
3850 ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
3851 ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
3852 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3853 sei_mdcv_params_t *ps_sei_mdcv;
3854 WORD32 i4_count;
3855
3856 ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
3857 ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
3858 UNUSED(ps_ip);
3859
3860 if(0 == ps_dec->s_sei_export.u1_sei_mdcv_params_present_flag)
3861 {
3862 ps_op->u4_error_code = ERROR_SEI_MDCV_PARAMS_NOT_FOUND;
3863 return IV_FAIL;
3864 }
3865
3866 ps_sei_mdcv = &ps_dec->s_sei_export.s_sei_mdcv_params;
3867
3868 for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
3869 {
3870 ps_op->au2_display_primaries_x[i4_count] = ps_sei_mdcv->au2_display_primaries_x[i4_count];
3871 ps_op->au2_display_primaries_y[i4_count] = ps_sei_mdcv->au2_display_primaries_y[i4_count];
3872 }
3873
3874 ps_op->u2_white_point_x = ps_sei_mdcv->u2_white_point_x;
3875 ps_op->u2_white_point_y = ps_sei_mdcv->u2_white_point_y;
3876 ps_op->u4_max_display_mastering_luminance = ps_sei_mdcv->u4_max_display_mastering_luminance;
3877 ps_op->u4_min_display_mastering_luminance = ps_sei_mdcv->u4_min_display_mastering_luminance;
3878
3879 return IV_SUCCESS;
3880 }
3881
3882 /*****************************************************************************/
3883 /* */
3884 /* Function Name : ih264d_get_sei_cll_params */
3885 /* */
3886 /* Description : This function populates SEI cll message in */
3887 /* output structure */
3888 /* Inputs : iv_obj_t decoder handle */
3889 /* : pv_api_ip pointer to input structure */
3890 /* : pv_api_op pointer to output structure */
3891 /* Outputs : */
3892 /* Returns : returns 0; 1 with error code when CLL is not present */
3893 /* */
3894 /* Issues : none */
3895 /* */
3896 /* Revision History: */
3897 /* */
3898 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3899 /* */
3900 /* */
3901 /*****************************************************************************/
ih264d_get_sei_cll_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3902 WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
3903 void *pv_api_ip,
3904 void *pv_api_op)
3905 {
3906 ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
3907 ih264d_ctl_get_sei_cll_params_op_t *ps_op;
3908 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3909 sei_cll_params_t *ps_sei_cll;
3910
3911 ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
3912 ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
3913 UNUSED(ps_ip);
3914
3915 if(0 == ps_dec->s_sei_export.u1_sei_cll_params_present_flag)
3916 {
3917 ps_op->u4_error_code = ERROR_SEI_CLL_PARAMS_NOT_FOUND;
3918 return IV_FAIL;
3919 }
3920
3921 ps_sei_cll = &ps_dec->s_sei_export.s_sei_cll_params;
3922
3923 ps_op->u2_max_content_light_level = ps_sei_cll->u2_max_content_light_level;
3924 ps_op->u2_max_pic_average_light_level = ps_sei_cll->u2_max_pic_average_light_level;
3925
3926 return IV_SUCCESS;
3927 }
3928
3929 /*****************************************************************************/
3930 /* */
3931 /* Function Name : ih264d_get_sei_ave_params */
3932 /* */
3933 /* Description : This function populates SEI ave message in */
3934 /* output structure */
3935 /* Inputs : iv_obj_t decoder handle */
3936 /* : pv_api_ip pointer to input structure */
3937 /* : pv_api_op pointer to output structure */
3938 /* Outputs : */
3939 /* Returns : returns 0; 1 with error code when AVE is not present */
3940 /* */
3941 /* Issues : none */
3942 /* */
3943 /* Revision History: */
3944 /* */
3945 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3946 /* */
3947 /* */
3948 /*****************************************************************************/
ih264d_get_sei_ave_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3949 WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
3950 void *pv_api_ip,
3951 void *pv_api_op)
3952 {
3953 ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
3954 ih264d_ctl_get_sei_ave_params_op_t *ps_op;
3955 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3956 sei_ave_params_t *ps_sei_ave;
3957
3958 ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
3959 ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
3960 UNUSED(ps_ip);
3961
3962 if(0 == ps_dec->s_sei_export.u1_sei_ave_params_present_flag)
3963 {
3964 ps_op->u4_error_code = ERROR_SEI_AVE_PARAMS_NOT_FOUND;
3965 return IV_FAIL;
3966 }
3967
3968 ps_sei_ave = &ps_dec->s_sei_export.s_sei_ave_params;
3969
3970 ps_op->u4_ambient_illuminance = ps_sei_ave->u4_ambient_illuminance;
3971 ps_op->u2_ambient_light_x = ps_sei_ave->u2_ambient_light_x;
3972 ps_op->u2_ambient_light_y = ps_sei_ave->u2_ambient_light_y;
3973
3974 return IV_SUCCESS;
3975 }
3976
3977 /*****************************************************************************/
3978 /* */
3979 /* Function Name : ih264d_get_sei_ccv_params */
3980 /* */
3981 /* Description : This function populates SEI mdcv message in */
3982 /* output structure */
3983 /* Inputs : iv_obj_t decoder handle */
3984 /* : pv_api_ip pointer to input structure */
3985 /* : pv_api_op pointer to output structure */
3986 /* Outputs : */
3987 /* Returns : returns 0; 1 with error code when CCV is not present */
3988 /* */
3989 /* Issues : none */
3990 /* */
3991 /* Revision History: */
3992 /* */
3993 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3994 /* */
3995 /* */
3996 /*****************************************************************************/
ih264d_get_sei_ccv_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3997 WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
3998 void *pv_api_ip,
3999 void *pv_api_op)
4000 {
4001 ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
4002 ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
4003 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4004 sei_ccv_params_t *ps_sei_ccv;
4005 WORD32 i4_count;
4006
4007 ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
4008 ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
4009 UNUSED(ps_ip);
4010
4011 if(0 == ps_dec->s_sei_export.u1_sei_ccv_params_present_flag)
4012 {
4013 ps_op->u4_error_code = ERROR_SEI_CCV_PARAMS_NOT_FOUND;
4014 return IV_FAIL;
4015 }
4016
4017 ps_sei_ccv = &ps_dec->s_sei_export.s_sei_ccv_params;
4018
4019 ps_op->u1_ccv_cancel_flag = ps_sei_ccv->u1_ccv_cancel_flag;
4020
4021 if(0 == ps_op->u1_ccv_cancel_flag)
4022 {
4023 ps_op->u1_ccv_persistence_flag = ps_sei_ccv->u1_ccv_persistence_flag;
4024 ps_op->u1_ccv_primaries_present_flag = ps_sei_ccv->u1_ccv_primaries_present_flag;
4025 ps_op->u1_ccv_min_luminance_value_present_flag =
4026 ps_sei_ccv->u1_ccv_min_luminance_value_present_flag;
4027 ps_op->u1_ccv_max_luminance_value_present_flag =
4028 ps_sei_ccv->u1_ccv_max_luminance_value_present_flag;
4029 ps_op->u1_ccv_avg_luminance_value_present_flag =
4030 ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag;
4031 ps_op->u1_ccv_reserved_zero_2bits = ps_sei_ccv->u1_ccv_reserved_zero_2bits;
4032
4033 if(1 == ps_sei_ccv->u1_ccv_primaries_present_flag)
4034 {
4035 for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
4036 {
4037 ps_op->ai4_ccv_primaries_x[i4_count] = ps_sei_ccv->ai4_ccv_primaries_x[i4_count];
4038 ps_op->ai4_ccv_primaries_y[i4_count] = ps_sei_ccv->ai4_ccv_primaries_y[i4_count];
4039 }
4040 }
4041
4042 if(1 == ps_sei_ccv->u1_ccv_min_luminance_value_present_flag)
4043 {
4044 ps_op->u4_ccv_min_luminance_value = ps_sei_ccv->u4_ccv_min_luminance_value;
4045 }
4046 if(1 == ps_sei_ccv->u1_ccv_max_luminance_value_present_flag)
4047 {
4048 ps_op->u4_ccv_max_luminance_value = ps_sei_ccv->u4_ccv_max_luminance_value;
4049 }
4050 if(1 == ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag)
4051 {
4052 ps_op->u4_ccv_avg_luminance_value = ps_sei_ccv->u4_ccv_avg_luminance_value;
4053 }
4054 }
4055
4056 return IV_SUCCESS;
4057 }
4058
ih264d_set_num_cores(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4059 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4060 {
4061 ih264d_ctl_set_num_cores_ip_t *ps_ip;
4062 ih264d_ctl_set_num_cores_op_t *ps_op;
4063 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4064
4065 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4066 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4067 ps_op->u4_error_code = 0;
4068 ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4069 if(ps_dec->u4_num_cores == 1)
4070 {
4071 ps_dec->u1_separate_parse = 0;
4072 }
4073 else
4074 {
4075 ps_dec->u1_separate_parse = 1;
4076 }
4077
4078 /*using only upto three threads currently*/
4079 if(ps_dec->u4_num_cores > 3)
4080 ps_dec->u4_num_cores = 3;
4081
4082 return IV_SUCCESS;
4083 }
4084
ih264d_fill_output_struct_from_context(dec_struct_t * ps_dec,ivd_video_decode_op_t * ps_dec_op)4085 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4086 ivd_video_decode_op_t *ps_dec_op)
4087 {
4088 if((ps_dec_op->u4_error_code & 0xff)
4089 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4090 {
4091 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4092 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4093 }
4094 ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
4095 ps_dec_op->i4_display_index = ps_dec->i4_display_index;
4096 ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4097
4098 ps_dec_op->u4_new_seq = 0;
4099 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4100 ps_dec_op->u4_progressive_frame_flag =
4101 ps_dec->s_disp_op.u4_progressive_frame_flag;
4102
4103 ps_dec_op->u4_is_ref_flag = 1;
4104 if(ps_dec_op->u4_frame_decoded_flag)
4105 {
4106 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4107 ps_dec_op->u4_is_ref_flag = 0;
4108 }
4109
4110 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4111 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4112 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4113 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4114 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4115
4116 ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
4117 }
4118
4119 /*****************************************************************************/
4120 /* */
4121 /* Function Name : ih264d_api_function */
4122 /* */
4123 /* Description : */
4124 /* */
4125 /* Inputs :iv_obj_t decoder handle */
4126 /* :pv_api_ip pointer to input structure */
4127 /* :pv_api_op pointer to output structure */
4128 /* Outputs : */
4129 /* Returns : void */
4130 /* */
4131 /* Issues : none */
4132 /* */
4133 /* Revision History: */
4134 /* */
4135 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4136 /* 22 10 2008 100356 Draft */
4137 /* */
4138 /*****************************************************************************/
ih264d_api_function(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4139 IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4140 void *pv_api_ip,
4141 void *pv_api_op)
4142 {
4143 UWORD32 command;
4144 UWORD32 *pu2_ptr_cmd;
4145 UWORD32 u4_api_ret;
4146 IV_API_CALL_STATUS_T e_status;
4147 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4148
4149 if(e_status != IV_SUCCESS)
4150 {
4151 UWORD32 *ptr_err;
4152
4153 ptr_err = (UWORD32 *)pv_api_op;
4154 UNUSED(ptr_err);
4155 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4156 return IV_FAIL;
4157 }
4158
4159 pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4160 pu2_ptr_cmd++;
4161
4162 command = *pu2_ptr_cmd;
4163 // H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4164 switch(command)
4165 {
4166
4167 case IVD_CMD_CREATE:
4168 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip,
4169 (void *)pv_api_op);
4170 break;
4171 case IVD_CMD_DELETE:
4172 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip,
4173 (void *)pv_api_op);
4174 break;
4175
4176 case IVD_CMD_VIDEO_DECODE:
4177 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4178 (void *)pv_api_op);
4179 break;
4180
4181 case IVD_CMD_GET_DISPLAY_FRAME:
4182 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4183 (void *)pv_api_op);
4184
4185 break;
4186
4187 case IVD_CMD_SET_DISPLAY_FRAME:
4188 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4189 (void *)pv_api_op);
4190
4191 break;
4192
4193 case IVD_CMD_REL_DISPLAY_FRAME:
4194 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4195 (void *)pv_api_op);
4196 break;
4197
4198 case IVD_CMD_VIDEO_CTL:
4199 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4200 (void *)pv_api_op);
4201 break;
4202 default:
4203 u4_api_ret = IV_FAIL;
4204 break;
4205 }
4206
4207 return u4_api_ret;
4208 }
4209